CN113779918A - SoC simulation method, device, computing equipment and computer storage medium - Google Patents
SoC simulation method, device, computing equipment and computer storage medium Download PDFInfo
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Abstract
The embodiment of the application provides a SoC simulation method, a device, a computing device and a computer storage medium. Wherein, the name of the target file is determined; acquiring a file list to be simulated; if the file list name of the file list is the same as the target file name, determining all files in the file list as files to be replaced; generating a function file according to the file content of the file to be replaced, wherein the function file comprises an output port with a signal value and does not comprise logic content in the file to be replaced; replacing the file to be replaced with the function file in the file list; and executing simulation operation on the file list after replacing the file so as to output a stable signal corresponding to the signal value when the function file is simulated. The technical scheme provided by the embodiment of the application can reduce the simulation scale, accelerate the simulation and improve the chip verification efficiency.
Description
Technical Field
The embodiment of the application relates to the technical field of chip verification, in particular to a method and a device for SoC simulation, computing equipment and a computer storage medium.
Background
With the development of front-end and back-end technologies of Chip design, Chip design has been developed from the integration of transistors to the integration of logic gates, and has also been developed to the integration of Intellectual Property cores (IP cores for short), i.e., System-on-Chip (SoC) design technologies. The SoC integration based on the IP core can effectively reduce the development cost of electronic products, shorten the development period and improve the competitiveness of the products. However, as the production process becomes more complex and the chip scale becomes larger, the verification complexity of the SoC increases exponentially. In general, the SoC verification process mainly includes the following three simulation cycles: register-to-registers Logic (RTL) behavioral Level simulation, Gate-Level simulation (GLS) simulation, and timing simulation, so that the longer the simulation time, the lower the SoC verification efficiency. That is, the SoC simulation time becomes the bottleneck of chip verification, and directly determines the efficiency and period of SoC development.
Currently, to increase the speed of SoC simulation, the prior art solution usually adopts a way of reducing simulation options in the simulation script to increase the simulation efficiency.
However, in the scheme in the prior art, by means of a simulation option in the simulation script, not only is part of simulation functions sacrificed and the accuracy of the simulation result is reduced, but also the simulation efficiency is not obviously improved.
Disclosure of Invention
The embodiment of the application provides a SoC simulation method, a SoC simulation device, a computing device and a computer storage medium, which are used for solving the problem of low simulation efficiency in the prior art.
In a first aspect, an embodiment of the present application provides an SoC simulation method, including:
determining a target file name;
acquiring a file list to be simulated;
if the file list name of the file list is the same as the target file name, determining all files in the file list as files to be replaced;
generating a function file according to the file content of the file to be replaced, wherein the function file comprises an output port with a signal value and does not comprise logic content in the file to be replaced;
replacing the file to be replaced with the function file in the file list;
and executing simulation operation on the file list after replacing the file so as to output a stable signal corresponding to the signal value when the function file is simulated.
Optionally, the method further comprises:
when the file list name of the file list is different from the target file name, carrying out environment analysis on the file list;
and if the file list contains the file with the file name identical to the target file name through analysis, determining the file as the file to be replaced.
Optionally, the method further comprises: and if the file list does not contain the file with the file name same as the target file name, feeding back error reporting information.
Optionally, the generating the function file according to the file content of the file to be replaced includes:
reading the content of the file to be replaced according to lines;
when the parameter keywords are read, storing the content corresponding to the parameter keywords;
when an input keyword is read, storing the content corresponding to the input keyword;
when the output keywords are read, storing the content corresponding to the output keywords;
and adding the assignment content of the output port in the content corresponding to the parameter keyword, the content corresponding to the input keyword or the content corresponding to the output keyword to generate a function file.
Optionally, the assignment content of the output port may include a plurality of output ports, and each output port sets the same signal value, so that the function file outputs a stable signal corresponding to the signal value in the simulation process.
Optionally, the determining the target file name includes:
and determining the name of the target file according to the files which are not required to be covered in the simulation process or the target file which has no influence on the simulation result.
Optionally, after the determining the target file name, further comprising:
and adding the control command aiming at the target file name to a named line of the simulation script.
In a second aspect, an embodiment of the present application provides an SoC emulation apparatus, including:
a determination unit configured to determine a target file name;
the device comprises an acquisition unit, a simulation unit and a control unit, wherein the acquisition unit is used for acquiring a file list to be simulated;
the determining unit is further configured to determine all files in the file list as files to be replaced if the file list name of the file list is the same as the target file name;
a generating unit, configured to generate a function file according to file content of the file to be replaced, where the function file includes an output port with a signal value and does not include logic content in the file to be replaced;
the replacing unit is used for replacing the file to be replaced with the function file in the file list;
and the simulation unit is used for executing simulation operation on the file list after replacing the file so as to output a stable signal corresponding to the signal value when the function file is simulated.
In a third aspect, an embodiment of the present application provides a computing device, including a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are for execution by the processing component to implement the SoC emulation method as described above.
In a fourth aspect, an embodiment of the present application provides a computer storage medium, which stores a computer program, and when the computer program is executed by a computer, the SoC simulation method described above is implemented.
The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions.
In the embodiment of the application, the name of a target file is determined; acquiring a file list to be simulated; if the file list name of the file list is the same as the target file name, determining all files in the file list as files to be replaced; generating a function file according to the file content of the file to be replaced, wherein the function file comprises an output port with a signal value and does not comprise logic content in the file to be replaced; replacing the file to be replaced with the function file in the file list; and executing simulation operation on the file list after replacing the file so as to output a stable signal corresponding to the signal value when the function file is simulated, thereby reducing the simulation scale, accelerating the simulation and improving the chip verification efficiency.
These and other aspects of the present application will be more readily apparent from the following description of the embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of an embodiment of an SoC simulation method according to an embodiment of the present application;
fig. 2 is a flowchart of another embodiment of an SoC simulation method according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an embodiment of an SoC simulation apparatus according to the present disclosure;
fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In some of the flows described in the specification and claims of this application and in the above-described figures, a number of operations are included that occur in a particular order, but it should be clearly understood that these operations may be performed out of order or in parallel as they occur herein, the number of operations, e.g., 101, 102, etc., merely being used to distinguish between various operations, and the number itself does not represent any order of performance. Additionally, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel. It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.
In order to facilitate understanding of the technical solutions of the present application, the following first explains technical terms that may appear in the embodiments of the present application:
system on Chip (SoC): often referred to as a system-on-a-chip, is an integrated circuit with a dedicated target that contains the complete system and has the entire contents of the embedded software.
In a narrow sense, the system is the chip integration of the core of an information system, and the key components of the system are integrated on one chip. The academic circles at home and abroad generally tend to define the SoC as integrating a microprocessor, an analog IP core, a digital IP core and a memory (or an off-chip memory control interface) on a single chip, which is usually custom-made or standard product oriented to a specific application.
RTL behavioral level simulation (RTL simulation for short): also called functional simulation, this stage of simulation can be used to check the correctness of syntax errors in the code and the behavior of the code, without including delay information. The simulation at this stage can also be made device independent if some of the special underlying elements associated with the device are not instantiated. The files required in performing the RTL simulation include: verilog source files written, and test files (tb files). If an ip core such as pl, memory, dsp, etc. is used, the device library file needs to be mounted.
Gate level simulation: also called netlist simulation or post-synthesis simulation, is simulation of adding tb file to netlist file (file in v format) generated after synthesis, and the netlist file is related to devices, so that a correlator device library file needs to be mounted when gate-level simulation is performed. The files required in performing netlist simulation include: a netlist file, and a tb file. The device library file needs to be mounted.
Time sequence simulation: also called post-simulation. The netlist file is delayed, and the simulation contains delay information. The files required in the time sequence simulation include: netlist file and tb file and delay file sdo (mounted using script). The device library file needs to be mounted.
UPF (unified Power Format) file: the method is mainly used for describing the power supply condition of the RTL behavioral simulation code. In the UPF file, a power domain (power _ domain), a power switch (power _ switch), a power isolation (power _ isolation), and the like in the RTL behavioral level simulation code are described. In short, inside the UPF file, the power supply relationship of the hierarchical structure is simulated at different RTL behavioral levels in the whole chip by describing through codes.
It should be noted that the simulation process of the present application is applicable to RTL behavioral level simulation, and may also be applicable to RTL behavioral level simulation with a UPF file. If the port of the netlist is regular and the reset register list without timing sequence check is clear, the simulation process of the application can also be suitable for netlist simulation.
Aiming at the problem of low efficiency of the current SoC simulation, the application aims to realize a method for really accelerating the simulation on the premise of not influencing the SoC simulation function.
In order to achieve the above purpose, the present application considers that logic function modules in an SoC chip are usually responsible for by different engineers, and development cycles of each logic function module are different, even a part of the logic function modules are only in an assumed stage and are not formally developed, and if a problem that a chip verification cycle is too long is caused by performing simulation after all logic function modules are developed, the present application can perform simulation on the developed logic function modules, and for other function modules which do not need to be covered or logic function modules which have no influence on a simulation result (such as modules which are not formally developed or are not developed), the present application can replace files in which the logic function modules are located with function files (the function files are also understood as empty digital logic files), and input the replaced file list to a simulator for simulation, so that the chip verification cycle is not influenced, and the simulation process can be carried out without simulating the logic content in the original file (the file where the module does not need to be covered or has no influence on the simulation result), thereby reducing the simulation scale and accelerating the simulation.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a flowchart of an embodiment of an SoC simulation method provided in the present application, where the method may include the following steps:
101. the target file name is determined.
In this step, the target file name is determined according to the file which is not needed to be covered by the simulation process or the target file which has no influence on the simulation result, wherein the file which is not needed to be covered by the simulation process or the target file which has no influence on the simulation result can be an unfinished file or an undeveloped file.
In the embodiment of the application, the progress of each logic function module in the file list to be simulated can be checked, the modules which do not need to be covered or have no influence on the simulation result can be analyzed, the files where the modules which do not need to be covered or have no influence on the simulation result are determined as the target files, and the file names of the target files are used as the target file names.
Further, after the determining the target file name, the method further includes: and adding the control command aiming at the target file name to a named line of the simulation script. For example, in practical applications, the control command includes a do nothing option command, where the do nothing option command is used to control making the target file into a function file (that is, a do nothing digital logic file), specifically, the do nothing option command may be added to the simulation top-level script command line, so that during simulation, the do nothing option command is called through the simulation command, and the script can automatically query the target file and perform subsequent replacement operations. For example, the make-empty option command is-empty ap _ sys _ top, where "ap _ sys _ top" is the target file name, and "-empty _ sys _ top" means that the file with the target file name ap _ sys _ top is made into an empty digital logic file.
102. And acquiring a file list to be simulated.
In the embodiment of the present application, the file list format is.f, and the file list to be emulated may include a plurality of files (the file format is.v). For example, the file list of axi _1xn _ top.f may include axi _1xn.v, axi _1xn _ arb.v, axi _1xn _ id _ os _ ctrl.v, axi _1xn _ r.v, axi _1xn _ top.v, and axi _1xn _ w.v, where axi _1xn _ top.v is the top file of the file list, that is, axi _1xn _ top.v includes the code for instantiating the other files (axi _1xn.v, axi _1xn _ arb.v, axi _1xn _ id _ os _ ctrl.v, axi _1xn _ r.v, axi _1xn _ w.v), that is, the logical content.
It should be noted that, in the embodiment of the present application, a file list to be simulated is only a subfile list, and the SoC simulation method of the present application is only described with respect to one subfile list. That is, in practical applications, the emulator automatically and recursively expands all the file lists to be emulated (i.e. sub-file lists) input into the emulation software into a digital logic source file list (i.e. top-level file list), and then performs the following steps 103 and 105 on the digital logic source file list, with the difference that: in step 103, the file list name of each subfile list in the digital logic source file list needs to be traversed to be the same as the target file name, in step 104, the files to be replaced in the subfile list are replaced, in step 105, a new digital logic source file list is generated from all the replaced subfiles, and a simulation operation is performed on the new digital logic source file list.
103. And if the file list name of the file list is the same as the target file name, determining all files in the file list as files to be replaced.
In this step, the file to be replaced is represented as a file that needs to be replaced. Usually, the files to be replaced include files that are not needed to be covered by the simulation process or files that have no effect on the simulation result, such as incomplete files or undeveloped files, and therefore, the files need to be replaced so as to reduce the simulation scale and speed up the simulation.
In the embodiment of the present application, it is determined whether the file list name of the file list is the same as the target file name by determining whether the file list name of the file list to be replaced is named by the file name of the top-level file, and the top-level file includes the logic content for instantiating the objects of other files in the file list. For example, a file list is axi _1xn _ top.f, the file list further includes axi _1xn.v, axi _1xn _ arb.v, axi _1xn _ id _ os _ ctrl.v, axi _1xn _ r.v, axi _1xn _ top.v, and axi _1xn _ w.v, and the top-level file is axi _1xn _ top.v as an example, the top-level file axi _1xn _ top.v includes a code for instantiating a module in axi _1xn.v, axi _1xn _ arb.v, axi _1xn _ id _ os _ rl.v, axi _1xn _ r.v, and axi _1xn _ w.v, so if the name of the instantiated file is the same as the name of the top-level file, the name of the file is determined as the top-level file to be replaced, that the file is also determined as the top-level file to be replaced.
It should be noted that the target file is different from the file to be replaced in that the target file may be the file to be replaced, but the file to be replaced is not necessarily the target file. Examples are as follows: taking the name of the target file "axi _1xn _ top" as an example, axi _1xn _ top.v is the target file and the file to be replaced, but since the top-level file axi _1xn _ top.v includes codes for instantiating modules in axi _1xn.v, axi _1xn _ arb.v, axi _1xn _ id _ os _ ctrl.v, axi _1xn _ r.v and axi _1xn _ w.v, it is necessary to determine not only the top-level file as the file to be replaced, but also determine the file where the module instantiated in the top-level file is located as the file to be replaced, that is, besides axi _1xn _ top.v as the file to be replaced, axi _1xn _ 63v, axi _1xn _ arb _1xn _ top.v, axi _1xn _ ctrl.v and w.v are also files to be replaced. In short, in the above example, the target file includes axi _1xn _ top.v, and the files to be replaced include axi _1xn _ top.v, axi _1xn.v, axi _1xn _ arb.v, axi _1xn _ id _ os _ ctrl.v, axi _1xn _ r.v, and axi _1xn _ w.v.
104. And generating the function file according to the file content of the file to be replaced, wherein the function file comprises an output port with a signal value and does not comprise the logic content in the file to be replaced.
In this step, the function file is an empty digital logic file, specifically a digital logic file that only contains output ports with signal values, and does not contain any logic content. The signal value may be set according to requirements, for example, the signal value may include 0 or 1. By setting the signal value, the function file outputs a stable signal corresponding to the signal value in the simulation process, and the influence of an unstable signal generated by an unassigned output port on a simulation result is avoided.
For example, when the file name of the file to be replaced is "axi _1xn _ w", the file list of the file list
When the name is "axi _1xn _ w", the file list name of the file list and the target file
The names are the same, so the files in axi _1xn _ top.f (such as axi _1xn.v, axi _1xn _ arb.v, axi _1xn _ id _ os _ ctrl.v, axi _1xn _ r.v, axi _1xn _ top.v, and axi _1xn _ w.v) are all determined as the files to be replaced, and the function files are generated according to the file contents of the files to be replaced.
As an alternative, the process of generating the function file according to the file content of the file to be replaced may include: reading the content of the file to be replaced according to lines; when the parameter keywords are read, storing the content corresponding to the parameter keywords; when an input keyword is read, storing the content corresponding to the input keyword; when the output keywords are read, storing the content corresponding to the output keywords; and generating a temporary function file based on the content corresponding to the parameter keyword, the content corresponding to the input keyword or the content corresponding to the output keyword, and adding assignment content of an output port in the temporary function file to generate a function file.
For example, the following code is included in the file to be replaced (by way of example only, and the ". multidot.... in the following examples" means omitted):
module axi_1xn_top(/*autoarg*/
csysreq,auto_gt_en,ptest_icgmode......)；
......；
Input csysreq；
Output csysack；
......；
axi_1xn#(......)；
......；
in the above code, "csysreq, auto _ gt _ en, ptest _ icgmode" is a parameter keyword, and therefore, when the parameter keyword is read, the parameter keyword is saved, "Input" is represented as an Input keyword, and "Output" is represented as an Output keyword, and therefore, when the Input keyword is read, the content corresponding to the Input keyword is saved, and when the Output keyword is read, the content corresponding to the Output keyword is saved. "axi _1xn # (..); "represents a process of instantiating the file axi _1xn.v, when the content is read, the file is not stored until the last line of the content of the file to be replaced is executed, and the assignment content of the output port is added in the content corresponding to the parameter keyword, the content corresponding to the input keyword or the content corresponding to the output keyword so as to generate the function file.
The output port in the file to be replaced may be a value output by running logic content, and the assignment of the output port in the function file is a signal value set by itself, for example, the signal value may include 0 or 1.
It should be noted that, when the content of the file to be replaced is read in a row, the logic content instantiated by the object in the file to be replaced is not read, and only the empty logic contents such as the parameter keyword, the input value, and the output value in the file to be replaced are read, in addition, the assignment content of the output port may include a plurality of output ports, and each output port sets the same signal value, so that the purpose of this is to enable the functional file to replace the file to be replaced to output the stable signal corresponding to the signal value in the subsequent simulation process, and the logic content in the file to be replaced does not need to be simulated, thereby not only reducing the simulation scale and accelerating the simulation, but also not affecting the verification cycle of the whole SoC chip because of the file to be replaced.
In practical application, the process of generating the functional file according to the file content of the file to be replaced can be completed by setting an automatic script. In addition, the function file may be generated in other manners, which is not limited in the present application.
105. And replacing the file to be replaced with the function file in the file list.
In this step, the file to be replaced may be replaced with the function file by setting a replacement script in the file list. The file to be replaced comprises logic content, wherein the logic content can comprise code for performing instantiation process on the module.
In the embodiment of the application, the to-be-replaced file includes a process of instantiating an object to a plurality of files (such as axi _1xn.v, axi _1xn _ arb.v, axi _1xn _ id _ os _ ctrl.v, axi _1xn _ r.v, axi _1xn _ top.v, and axi _1xn _ w.v).
106. And executing simulation operation on the file list after replacing the file so as to output a stable signal corresponding to the signal value when the function file is simulated.
In the embodiment of the application, the simulation operation is executed on the file list after the file is replaced, so that the logic content in the file to be replaced does not need to be simulated in the simulation process, the simulation scale is reduced, the simulation process is accelerated, meanwhile, the function file is used for replacing the file to be replaced to output the stable signal corresponding to the signal value, the problem that the file to be replaced (for example, when the file to be replaced comprises an undeveloped logic function module, the file to be replaced cannot be simulated at the moment, and if the file to be replaced needs a long time after the logic function module is developed) cannot participate in the simulation, so that the verification period of the SoC chip is prolonged is solved, and the chip verification efficiency is improved.
In the technical solutions provided by the above embodiments of the present application, the name of the target file is determined; acquiring a file list to be simulated; if the file list name of the file list is the same as the target file name, determining all files in the file list as files to be replaced, and generating the function file according to the file content of the files to be replaced, wherein the function file comprises an output port with a signal value and does not comprise logic content in the files to be replaced; replacing the file to be replaced with the function file in the file list; and executing simulation operation on the file list after the file is replaced so that the functional file replaces the file to be replaced in the simulation process to output a stable signal corresponding to the signal value, and logic content in the file to be replaced does not need to be simulated, so that the simulation scale can be reduced, the simulation is accelerated, and the chip verification efficiency is improved.
Further, an embodiment of the present application also provides a flowchart of another embodiment of an SoC simulation method, as shown in fig. 2, the method may include the following steps:
201. the target file name is determined.
In the steps of the present embodiment, the portions are the same as those of the above steps 101-105, and the present embodiment will not be described in detail here, and refer to the description of the above embodiments specifically.
202. And acquiring a file list to be simulated.
203. Judging whether the file list name of the file list is the same as the target file name, if so, executing step 204; if not, go to step 205.
In this step, if it is determined that the file list name of the file list is the same as the target file name, it indicates that all files in the file list need to be replaced with functional files; if the file list name of the file list is judged to be different from the target file name, the fact that part of files in the file list need to be replaced by functional files is indicated.
204. Determining all files in the file list as files to be replaced, generating the function file according to the file content of the files to be replaced, wherein the function file comprises an output port with a signal value and does not comprise the logic content in the files to be replaced, and continuing to execute step 208.
In step 204, the generating the function file according to the file content of the file to be replaced includes:
2041. and reading the content of the file to be replaced according to lines.
2042. And when the parameter keywords are read, storing the content corresponding to the parameter keywords.
2043. And when the input keywords are read, storing the contents corresponding to the input keywords.
2044. And when the output keywords are read, storing the contents corresponding to the output keywords.
2045. And generating a temporary function file based on the content corresponding to the parameter keyword, the content corresponding to the input keyword or the content corresponding to the output keyword, and adding assignment content of an output port in the temporary function file to generate a function file.
In this step, the assignment content of the output port may include a plurality of output ports, and each output port sets the same signal value, so that the function file outputs a stable signal corresponding to the signal value in the simulation process.
For practical application of the above steps 2041 to 2045, reference may be made to the example in step 103.
205. Performing environment analysis on the file list, judging whether a file with a file name identical to the target file name is included in the file list or not, if so, executing a step 206; if not, go to step 207.
In this step, if the file list is analyzed to include a file with a file name that is the same as the target file name, it is indicated that part of the files in the file list need to be replaced with function files. If the file list does not contain the file with the file name identical to the target file name, the fact that all or part of the files to be replaced do not need to be replaced by the functional files is indicated, and the contradiction is caused by the input command for making the null option, and therefore error information is fed back.
In the embodiment of the application, as a possible implementation scheme, environment analysis can be performed on the file list through the automatic script, after the environment analysis is performed, the file name of each file in the file list can be obtained, and whether the file name of each file in the file list is the same as the target file name or not is sequentially traversed, so that the file to be replaced is determined.
206. And determining the file as a file to be replaced, generating the function file according to the file content of the file to be replaced, and continuing to execute the step 208.
In this step, the process of generating the functional file according to the file content of the file to be replaced may refer to step 2041-2045.
In this embodiment, the difference between this step and step 204 is that step 204 determines all files in the file list as files to be replaced, and this step only needs to determine a certain file in the file list as a file to be replaced, that is, subsequent simulation operations are still required for non-replacement files in the file list.
207. And feeding back error reporting information.
In this step, the error information is used to prompt the user that the file name of no file in the current file list to be simulated is the same as the target file name, so that the user can continue to obtain other file lists to be simulated, and the above step 203 is executed again.
In this embodiment of the application, the feedback form of the error information may include multiple forms, for example, the error information "not queried about the file to be replaced" is displayed on a page, or an alarm information is sent to prompt the user that the file to be replaced is not queried about by the user, which is not limited in this embodiment of the application.
208. And replacing the file to be replaced with the function file in the file list.
209. And executing simulation operation on the file list after replacing the file so as to output a stable signal corresponding to the signal value when the function file is simulated.
In the embodiments of the present application, reference may be made to the embodiment of fig. 1 for the description of the same steps, which is not described in detail in the embodiments of the present application.
Fig. 3 is a schematic structural diagram of an embodiment of an SoC simulation apparatus provided in the present application, which may include:
a determination unit 31 for determining a target file name;
an obtaining unit 32, configured to obtain a file list to be simulated;
the determining unit 31 is further configured to determine all files in the file list as files to be replaced if the file list name of the file list is the same as the target file name;
a generating unit 33, configured to generate a function file according to file content of the file to be replaced, where the function file includes an output port with a signal value and does not include logic content in the file to be replaced;
a replacing unit 34, configured to replace, in the file list, the file to be replaced with the function file;
the simulation unit 35 is configured to perform a simulation operation on the file list after the file replacement, so as to output a stable signal corresponding to the signal value when the function file is simulated.
Optionally, the apparatus further comprises: a parsing module 36.
An analysis module 36, configured to perform environment analysis on the file list when the file list name of the file list is different from the target file name;
if the file list contains a file with a file name identical to the target file name, the generating unit 33 is further configured to determine the file as a file to be replaced, and generate the function file according to the file content of the file to be replaced.
Optionally, the apparatus further comprises: a sending module 37.
If the parsing module 36 does not parse the file list to include a file with a file name that is the same as the target file name, the sending module 37 is configured to feed back error reporting information.
Optionally, the generating unit 33 of the apparatus is specifically configured to read the content of the file to be replaced by rows; when the parameter keywords are read, storing the content corresponding to the parameter keywords; when an input keyword is read, storing the content corresponding to the input keyword; when the output keywords are read, storing the content corresponding to the output keywords; and adding the assignment content of the output port in the content corresponding to the parameter keyword, the content corresponding to the input keyword or the content corresponding to the output keyword to generate a function file.
Optionally, the assignment content of the output port may include a plurality of output ports, and each output port sets the same signal value, so that the function file outputs a stable signal corresponding to the signal value in the simulation process.
Optionally, the determining unit 31 of the apparatus is specifically configured to determine the target file name according to a file that does not need to be covered by the simulation process or a target file that has no influence on the simulation result.
Optionally, the apparatus further comprises: an adding unit 38.
An adding unit 38, configured to add the control command for the target file name to a named line of the emulation script.
The SoC simulation apparatus shown in fig. 3 may execute the SoC simulation method shown in the embodiment shown in fig. 1 or fig. 2, and the implementation principle and the technical effect are not described again. The specific manner in which each unit of the SoC simulation apparatus in the above embodiments performs operations has been described in detail in the embodiments related to the method, and will not be elaborated herein.
Fig. 4 is a schematic structural diagram of a computing device provided in this application, and in one possible design, the SoC apparatus in the embodiment shown in fig. 3 may be implemented as a computing device, and in practical application, the computing device may be implemented as the foregoing central node, as shown in fig. 4, the computing device may include a storage component 401, a processing component 402, and a display component 403;
The storage component 401 is configured to store various types of data to support operations at the terminal. The memory components may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks, for storing the above-described function files, and the like.
The display element 403 may be an Electroluminescent (EL) element, a liquid crystal display or a micro-display having a similar structure, or a retina-directly-displayable or similar laser scanning type display for displaying error information.
Of course, a computing device may also necessarily include other components, such as input/output interfaces, communication components, and so forth.
The input/output interface provides an interface between the processing components and peripheral interface modules, which may be output devices, input devices, etc.
The communication component is configured to facilitate wired or wireless communication between the computing device and other devices, and the like.
The computing device may be a physical device or an elastic computing host provided by a cloud computing platform, and the computing device may be a cloud server, and the processing component, the storage component, and the like may be a basic server resource rented or purchased from the cloud computing platform.
An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a computer, the SoC simulation method in the embodiments shown in fig. 1 and fig. 2 may be implemented.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. An SoC simulation method, comprising:
determining a target file name;
acquiring a file list to be simulated;
if the file list name of the file list is the same as the target file name, determining all files in the file list as files to be replaced;
generating a function file according to the file content of the file to be replaced, wherein the function file comprises an output port with a signal value and does not comprise logic content in the file to be replaced;
replacing the file to be replaced with the function file in the file list;
and executing simulation operation on the file list after replacing the file so as to output a stable signal corresponding to the signal value when the function file is simulated.
2. The method of claim 1, further comprising:
when the file list name of the file list is different from the target file name, carrying out environment analysis on the file list;
and if the file list contains the file with the file name identical to the target file name through analysis, determining the file as the file to be replaced.
3. The method of claim 2, further comprising: and if the file list does not contain the file with the file name same as the target file name, feeding back error reporting information.
4. The method according to claim 1 or 2, wherein the generating the function file according to the file content of the file to be replaced comprises:
reading the content of the file to be replaced according to lines;
when the parameter keywords are read, storing the content corresponding to the parameter keywords;
when an input keyword is read, storing the content corresponding to the input keyword;
when the output keywords are read, storing the content corresponding to the output keywords;
and adding the assignment content of the output port in the content corresponding to the parameter keyword, the content corresponding to the input keyword or the content corresponding to the output keyword to generate a function file.
5. The method of claim 4, wherein the assigned contents of the output ports comprise a plurality of output ports, and each output port is set with the same signal value, so that the function file outputs a stable signal corresponding to the signal value in the simulation process.
6. The method of claim 1, wherein determining the target file name comprises:
and determining the name of the target file according to the files which are not required to be covered in the simulation process or the target file which has no influence on the simulation result.
7. The method of claim 6, further comprising, after said determining a target file name:
and adding the control command aiming at the target file name to a named line of the simulation script.
8. An SoC emulation apparatus, comprising:
a determination unit configured to determine a target file name;
the device comprises an acquisition unit, a simulation unit and a control unit, wherein the acquisition unit is used for acquiring a file list to be simulated;
the determining unit is further configured to determine all files in the file list as files to be replaced if the file list name of the file list is the same as the target file name;
a generating unit, configured to generate a function file according to file content of the file to be replaced, where the function file includes an output port with a signal value and does not include logic content in the file to be replaced;
the replacing unit is used for replacing the file to be replaced with the function file in the file list;
and the simulation unit is used for executing simulation operation on the file list after replacing the file so as to output a stable signal corresponding to the signal value when the function file is simulated.
9. A computing device comprising a processing component and a storage component;
the storage component stores one or more computer instructions; the one or more computer instructions are used for being called and executed by the processing component to realize the SoC simulation method of any one of claims 1-7.
10. A computer storage medium storing a computer program which, when executed by a computer, implements the SoC simulation method according to any one of claims 1 to 7.
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