CN117350205A

CN117350205A - Chip verification method and device, electronic equipment and storage medium

Info

Publication number: CN117350205A
Application number: CN202311461698.2A
Authority: CN
Inventors: 张震
Original assignee: Horizon Journey Hangzhou Artificial Intelligence Technology Co ltd
Current assignee: Horizon Journey Hangzhou Artificial Intelligence Technology Co ltd
Priority date: 2023-11-03
Filing date: 2023-11-03
Publication date: 2024-01-05

Abstract

The embodiment of the disclosure discloses a chip verification method, a device, an electronic device and a storage medium, wherein the method comprises the following steps: acquiring a physical unit library of a chip to be verified, wherein the physical unit library comprises behavior models corresponding to all physical units of the chip to be verified; converting the physical unit library into a synthesizable physical unit library; the comprehensive physical unit library comprises a comprehensive model meeting the preset conditions of the target verification platform; the synthesizable model is a model which is consistent with the behavior logic of the behavior model and can be synthesized into a netlist; based on the synthesizable model in the synthesizable physical unit library, verifying the chip to be verified through the target verification platform to obtain a verification result. The embodiment of the disclosure can keep the consistency of the synthesized netlist circuit function of the chip to be verified and the original behavior-level code theory simulation function, so that the verification of the structure of the physical unit of the chip to be verified is not influenced, and the improvement of the sufficiency of chip verification is facilitated.

Description

Chip verification method and device, electronic equipment and storage medium

Technical Field

The disclosure relates to the technical field of chip verification, in particular to a chip verification method, a device, electronic equipment and a storage medium.

Background

In verifying a chip, a model (also called a code) describing a physical unit (i.e., a physical standard unit) of the chip provided by a chip manufacturer is usually a behavior-level model (also called a behavior model), and the behavior model is only applicable to a Simulator verification platform on a server, but not applicable to a simulation accelerator verification platform such as a Simulator. In the related art, when a chip needs to be verified by an analog accelerator verification platform, an underlying standard unit code (i.e., a behavior level code) of the chip needs to be modified, and an uncombinable logic in the underlying standard unit code may cause a netlist (netlist) circuit function after chip synthesis to be inconsistent with a theoretical simulation function of the underlying standard unit code, so that a structure of a physical unit cannot be verified, and thus the chip verification is insufficient.

Disclosure of Invention

In order to solve the technical problems of insufficient chip verification and the like, the embodiment of the disclosure provides a chip verification method, a device, electronic equipment and a storage medium, so that the chip verification is realized on the basis of a synthesizable model which is consistent with behavior logic of a behavior model on the basis of a simulation accelerator verification platform, and the chip verification sufficiency is improved.

In a first aspect of the present disclosure, a method for verifying a chip is provided, including: acquiring a physical unit library of a chip to be verified, wherein the physical unit library comprises behavior models corresponding to physical units of the chip to be verified; converting the physical unit library into a synthesizable physical unit library; the comprehensive physical unit library comprises a comprehensive model meeting the preset conditions of the target verification platform; the synthesizable model is a model which is consistent with the behavior logic of the behavior model and can be synthesized into a netlist; and verifying the chip to be verified through the target verification platform based on the synthesizable model in the synthesizable physical unit library to obtain a verification result.

In a second aspect of the present disclosure, there is provided a verification apparatus for a chip, including: the acquisition module is used for acquiring a physical unit library of the chip to be verified, wherein the physical unit library comprises behavior models corresponding to all physical units of the chip to be verified; the first processing module is used for converting the physical unit library into a synthesizable physical unit library; the comprehensive physical unit library comprises a comprehensive model meeting the preset conditions of the target verification platform; the synthesizable model is a model which is consistent with the behavior logic of the behavior model and can be synthesized into a netlist; and the second processing module is used for verifying the chip to be verified through the target verification platform based on the synthesizable model in the synthesizable physical unit library to obtain a verification result.

In a third aspect of the present disclosure, there is provided a computer-readable storage medium storing a computer program for executing the method of verifying a chip according to any one of the above embodiments of the present disclosure.

In a fourth aspect of the present disclosure, there is provided an electronic device including: a processor; a memory for storing the processor-executable instructions; the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for verifying a chip according to any one of the embodiments of the present disclosure.

In a fifth aspect of the present disclosure, a computer program product is provided, which, when executed by a processor, performs a method of verifying a chip provided by any of the above embodiments of the present disclosure.

Based on the verification method, the device, the electronic equipment and the storage medium of the chip provided by the embodiment of the disclosure, the behavior model of the physical unit of the chip to be verified is converted into a synthesizable model (synthesis model) meeting the conditions of the target verification platform, and further based on the synthesizable model, the chip to be verified is verified through the target verification platform, so that a verification result is obtained. The method and the device realize that the chip to be verified can be verified based on the verification platform such as an emulgator under the condition that the original design code of the chip to be verified is not modified, and because the behavior logic of the synthesizable model and the behavior model is consistent, the consistency of the netlist circuit function and the behavior-level code theoretical simulation function of the chip to be verified after synthesis can be maintained, so that the verification of the structure of the physical unit of the chip to be verified is not influenced, and the improvement of the sufficiency of chip verification is facilitated.

Drawings

Fig. 1 is an exemplary application scenario of a verification method of a chip provided by the present disclosure;

FIG. 2 is a flow chart of a method of verifying a chip provided by an exemplary embodiment of the present disclosure;

FIG. 3 is a flow chart of a method of verifying a chip provided in another exemplary embodiment of the present disclosure;

FIG. 4 is a flow chart of a method of verifying a chip provided in accordance with yet another exemplary embodiment of the present disclosure;

FIG. 5 is a flow chart of a method of verifying a chip provided in accordance with yet another exemplary embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a verification device of a chip according to an exemplary embodiment of the present disclosure;

fig. 7 is a schematic structural view of a verification device of a chip provided in another exemplary embodiment of the present disclosure;

fig. 8 is a block diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Description

For the purpose of illustrating the present disclosure, exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings, it being apparent that the described embodiments are only some, but not all embodiments of the present disclosure, and it is to be understood that the present disclosure is not limited by the exemplary embodiments.

It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.

Summary of the disclosure

In implementing the present disclosure, the inventor has found that, when verifying a chip, a model (also referred to as a code) provided by a chip manufacturer describing a physical unit (i.e., a physical standard unit) of the chip is typically a behavior model, where the behavior model is only applicable to a Simulator verification platform on a server, and is not applicable to a Simulator verification platform such as a Simulator. In the related art, when a chip needs to be verified by an analog accelerator verification platform, an underlying standard unit code (i.e., a behavior level code) of the chip needs to be modified, and an uncombinable logic in the underlying standard unit code may cause a netlist (netlist) circuit function after chip synthesis to be inconsistent with a theoretical simulation function of the underlying standard unit code, so that a structure of a physical unit cannot be verified, and thus the chip verification is insufficient.

Exemplary overview

Fig. 1 is an exemplary application scenario of a verification method of a chip provided by the present disclosure.

As shown in fig. 1, for a chip to be verified, a physical unit library of the chip to be verified may be obtained by using the verification method of the chip of the present disclosure (which may be performed in the verification device of the chip of the present disclosure), where the physical unit library includes behavior models corresponding to each physical unit of the chip to be verified; converting the physical unit library into a synthesizable physical unit library; the comprehensive physical unit library comprises a comprehensive model meeting the preset conditions of the target verification platform; the synthesizable model is a model which is consistent with the behavioral logic of the behavioral model and can be synthesized into a netlist (netlist); based on the synthesizable model in the synthesizable physical unit library, verifying the chip to be verified through the target verification platform to obtain a verification result. The target verification platform may include at least one of an emulators verification platform (which may be abbreviated as EMU platform), a prototype verification platform, and the like. The behavior model of the physical unit is converted into the synthesizable model which is consistent with the behavior logic of the behavior model, so that the synthesization tool can synthesize the hardware description language of the physical unit into a netlist during verification, thereby facilitating verification of the chip to be verified. The verification of the chip to be verified can comprise RTL (Register Transfer Level, register transmission level) function verification and netlist function verification of the chip to be verified, and the chip to be verified can be suitable for simulation accelerator verification platforms such as emulators and prototype verification platforms such as FPGA (Field Programmable Gate Array ) verification platforms, and can avoid the situation that the synthesized netlist circuit function is inconsistent with the theoretical simulation function of the bottom standard unit code and cannot verify the structural function of a physical unit due to modification of the bottom standard unit code of the chip to be verified, thereby being beneficial to improving the sufficiency of chip verification.

Exemplary method

Fig. 2 is a flow chart illustrating a method for verifying a chip according to an exemplary embodiment of the present disclosure. The embodiment can be applied to electronic devices, specifically, electronic devices such as a terminal device, a server, and the like, as shown in fig. 2, and includes the following steps:

step 201, obtaining a physical unit library of a chip to be verified, wherein the physical unit library comprises behavior models corresponding to physical units of the chip to be verified.

The physical unit is a circuit at the bottom layer of the chip to be verified, such as an AND or NOR circuit, a multiple-selection circuit, a register circuit with different reset functions, a power supply control circuit and the like. The behavior model is a behavior-level description of the physical unit, i.e. a hardware description language code segment for describing the functional behavior of the physical unit. Such as a code segment describing the behavior of the output as a function of the input. The physical cell library (which may be referred to as a behavior-level physical cell library) may be independent of the original design code of the chip to be verified, which is a hardware description language code describing the structure and function of the chip to be verified.

The physical unit is a multiple-input single-output unit formed by an and gate and an or gate, and the behavior model of the physical unit may include a description of a Loop Up Table (LUT) that is, outputs corresponding to different inputs respectively.

Step 202, converting a physical unit library into a synthesizable physical unit library; the synthesizable physical unit library comprises synthesizable models meeting preset conditions of the target verification platform.

Wherein the synthesizable model is a model which is logically consistent with the behavior of the behavior model and which can be synthesized into a netlist. The behavior logical agreement may refer to a logical agreement of the input-output behavior of the synthesizable model with the input-output behavior of the behavior model, i.e. for any same input, the output of the synthesizable model agrees with the output of the corresponding behavior model. The inputs of the behavioral level model may include, for example, inputs of 0, 1, X, Z, etc., where 0 and 1 represent logic levels, X represents an unknown state, and Z represents a high resistance state. On the target verification platform, the input of the model does not have an X state (i.e. an unknown state), for example, for the EMU platform, the input of the model does not have an X state, the X state can be converted into any one of 0 and 1, and for any same 0, 1 and Z input, the output of the model can be integrated to be consistent with the output of the corresponding behavior model.

In some alternative embodiments, the preset conditions may be set according to the functional logic and the supporting comprehensive description mode that the target verification platform needs to be involved in the verification process. Synthesizable description means a description that can be identified by a synthesis tool to be synthesized into a netlist. The synthesis tool may be any implementable synthesis tool of the target verification platform.

For example, for redundant logic that is not synthesizable or invalid in the verification process of the target verification platform, the redundant logic can be removed when the redundant logic is converted into a synthesizable model so as to reduce the resource usage in the verification process. For example, for a physical unit with a power port, when the simulator verification platform performs verification, the power port is not involved, and when the physical unit is converted into a synthesizable model, logic related to the power port can be removed. For another example, when the model is converted into the synthesizable model, the time sequence state checking part has no actual function influence on the actual physical circuit, belongs to invalid redundant logic, and can reduce the resource usage of the simulation logic unit in the verification process by eliminating the part of logic.

For example, in the simulator verification platform, the internal structure of the physical unit is not considered, and only the response condition of the output to the input of the physical unit is concerned, so when the synthesizable model is converted, only the input and output behaviors of the synthesizable model can be enabled to be consistent with the behavior logic of the behavior model, and the same function as the behavior model is realized, and the specific implementation structure inside the physical unit is not required to be concerned.

In some alternative embodiments, the target verification platform may be an emulgator verification platform, a prototype verification platform (i.e. FPGA verification platform), or a verification platform of a simulation early verification stage, which is not limited in particular.

And 203, verifying the chip to be verified through a target verification platform based on the synthesizable model in the synthesizable physical unit library to obtain a verification result.

The verifying the chip to be verified may include at least one of verifying an RTL code of the chip to be verified, verifying a netlist of the chip to be verified, and performing prototype verification on the chip to be verified, which is not limited in particular.

In some alternative embodiments, different target verification platforms may implement different verifications of the chip to be verified.

For example, the simulator verification platform may perform hardware simulation on the chip to be verified, and perform system-level verification (may be abbreviated as EMU verification) on functions, performance, power consumption and the like of the chip to be verified. Hardware realism and speed of operation for EMU verification is between EDA (Electronic Design Automation ) verification and FPGA verification. EDA verification can be realized based on a simultaneity verification platform and is used for verifying the consistency of RTL codes of chips to be verified and design schemes. The FPGA verification platform verifies the correctness of functions and time sequences of the chip to be verified by transplanting the RTL code of the chip to be verified into the FPGA, thereby being beneficial to reducing the risk of film streaming, shortening the development period, reducing the cost and reducing the risk of a system by cooperation of software and hardware.

In some alternative embodiments, when verifying the chip to be verified, the physical unit library (which may be referred to as the original physical unit library) of the chip to be verified may be replaced with the synthesizable physical unit library. The behavior-level hardware description code of the chip to be verified is replaced by the synthesizable hardware description code, and then the replaced synthesizable physical unit library of the chip to be verified is configured to a target verification platform, and the verification tool based on the target verification platform verifies the chip to be verified. For example, various verification tools based on an emulgator verification platform verify the chip to be verified. Because the original physical unit library can be independent of the original design code of the chip to be verified, when the target verification platform verifies the chip to be verified, the original design code of the chip to be verified does not need to be modified, but the original physical unit library is replaced by a synthesizable physical unit library which is consistent with the behavior logic of the original physical unit library, so that the integrated netlist circuit function based on the synthesizable physical unit library is consistent with the theoretical simulation function of the original behavior-level code of the chip to be verified, the structural verification of the physical unit of the chip to be verified is facilitated, and the sufficiency of chip verification is improved.

According to the chip verification method provided by the embodiment, the behavior model of the physical unit of the chip to be verified is converted into the synthesizable model meeting the conditions of the target verification platform, and further verification is performed on the chip to be verified through the target verification platform based on the synthesizable model, so that a verification result is obtained. The method and the device realize that the chip to be verified can be verified based on verification platforms such as an emulgator under the condition that the original design codes of the chip to be verified are not modified, and because the behavior logic of the synthesizable model and the behavior model are consistent, the consistence of the netlist circuit function of the chip to be verified after synthesis and the theoretical simulation function of the original behavior-level code can be maintained, so that the verification of the structure of the physical unit of the chip to be verified is not influenced, and the improvement of the sufficiency of chip verification is facilitated.

Fig. 3 is a flowchart illustrating a method for verifying a chip according to another exemplary embodiment of the present disclosure.

In some alternative embodiments, as shown in FIG. 3, converting the physical unit library into a synthesizable physical unit library at step 202 includes:

step 2021, for a behavior model corresponding to any one physical unit in the physical unit library, determining a conversion rule corresponding to the behavior model based on identification information of the behavior model.

The identification information of the behavior model may be a name or other possible representation information of the behavior model. The conversion rule corresponding to the behavior model is a rule for converting the behavior model into a synthesizable model. For example, for a behavior model of a physical unit and (parameter 1, parameter 2, …, parameter n) constituted by an and gate, a name describing the behavior model may be used as identification information of the behavior model.

In some alternative embodiments, corresponding transformation rules may be pre-set for various generic types of behavior models. For example, for the behavior models of physical units of and (), buf (), mux (), lookup tables, etc., corresponding conversion rules may be set. The conversion rules can be specifically set according to different code description rules of a behavior model and a synthesizable model of the physical unit.

In some optional embodiments, according to the physical unit description document of the chip to be verified, the functions implemented by the physical units are determined, the physical units are further classified, the functions of the physical units of each type are analyzed, the same points and different points of the behavior model of the physical units of the same type in different conditions in the synthesizable model are found, and based on the same, the conversion rule corresponding to the behavior model of the physical units of each type and used for being converted into the synthesizable model is determined.

In some optional embodiments, for some general physical units, a synthesizable model corresponding to the behavior model of the physical units may be directly set, and the identification information of the behavior model is stored corresponding to the synthesizable model. The conversion rule corresponding to the behavior model may include a rule for searching for a synthesizable model corresponding to the behavior model according to the identification information of the behavior model.

In some alternative embodiments, the types of the lookup table logic inside the physical unit may be counted, and for each lookup table logic, a unified synthesizable logic conversion rule is set.

In some alternative embodiments, the power signal inside the physical unit is analyzed, and for the logic with the power signal, a corresponding synthesizable logic conversion rule may be set according to the requirement of the target verification platform for the power port.

In some optional embodiments, the behavior model in the physical unit library may be traversed, and for any traversed behavior model of the physical unit, based on the identification information of the behavior model, a conversion rule corresponding to the behavior model is determined, and then, based on the conversion rule corresponding to the behavior model, a subsequent conversion process is performed.

In some alternative embodiments, the conversion rules may include rules for converting the effective logic into synthesizable logic, rules for eliminating redundant logic, and so on, so that the converted synthesizable model can conform to the corresponding preset conditions of the target verification platform.

In some alternative embodiments, the behavior model is a theoretical function that describes the physical unit more fully, and when the behavior model is converted into a synthesizable model, the behavior level description of the overall theory can be converted into a simple synthesizable description that meets the actual verification requirements more specifically for the verification requirements of the target verification platform. For example, some parameters in the behavior model are not used when the target verification platform performs verification, but are only used when the chip is realized, so that the parameters can be simplified to further reduce the resource usage of the verification process. For example, in the behavior model, the synthesizable model may include a plurality of logic units (such as and gate, or gate, not gate, etc.), and the synthesizable model may be implemented without considering how many logic units are specifically implemented, so long as the input/output behavior logic of the synthesizable model can be consistent with the behavior model, thereby simplifying the model and reducing the resource usage in the verification process.

Step 2022, converting the behavior model into a synthesizable model based on the conversion rules corresponding to the behavior model.

After determining the conversion rule corresponding to the behavior model, the behavior model can be converted into a synthesizable model based on the conversion rule corresponding to the behavior model, so that the synthesizable model obtained by conversion can meet the corresponding preset conditions of the target verification platform, and the synthesizable model can be synthesized into a netlist corresponding to the chip to be verified by a synthesis tool, so that the chip to be verified can be verified conveniently.

In the verification method of adapting to the simulation accelerator verification platform by modifying the bottom standard unit code of the chip in the related technology, because the bottom standard unit code of the chip is modified, on one hand, the non-synthesizable logic of the bottom standard unit code can lead to the fact that the integrated netlist circuit function of the chip is inconsistent with the theoretical simulation function of the bottom standard unit code, so that the chip is not sufficiently verified, on the other hand, in the verification process of the simulation accelerator verification platform, in the UPF (UnifiedPowerFormat) verification stage, the UPF design structure needs to be modified, so that the verification related to UPF cannot be kept consistent with the original design. In the later netlist verification stage, an uncombined model (namely a behavior model) is needed to be directly used, and the violation constraint check of the simulator verification platform is modified, so that the resource usage amount of the simulation logic unit in the verification process is easily increased due to the fact that redundant logic possibly exists in the uncombined model. According to the embodiment of the disclosure, the effective logic can be converted into the synthesizable logic through the conversion rule corresponding to the behavior model, and redundant logic can be eliminated, so that on one hand, the consistency of the circuit function of the netlist after chip synthesis and the theoretical simulation function of the original behavior-level code can be maintained, and the subsequent verification of the structure of the chip physical unit is not influenced. On the other hand, in the UPF verification stage, the UPF design structure does not need to be modified, so that the consistency of UPF related verification and original design can be maintained, and verification defects are avoided. In addition, because the synthesizable model is consistent with the behavior logic of the behavior model, in the later netlist verification stage, the synthesizable model can be directly synthesized into a netlist for verification without modifying the Emulator violation constraint check, and because the synthesizable model can reject redundant logic, the resource usage amount of a simulation unit in the verification process is reduced.

In some alternative embodiments, determining the conversion rule corresponding to the behavior model in step 2021 based on the identification information of the behavior model includes:

determining a convertible state corresponding to the behavior model based on the identification information of the behavior model; and determining a conversion rule corresponding to the behavior model based on the identification information in response to the convertible state being the first state.

If the traversed behavior model is a relatively general behavior model, there may already exist corresponding conversion rules, and if the traversed behavior model is a relatively less-used behavior model, there may not be found a corresponding conversion rule, so it may be determined whether the behavior model is convertible (i.e., determining a convertible state of the behavior model) based on identification information of the behavior model. The switchable state may include both a switchable and a non-switchable state. If the corresponding conversion rule is determined to exist, the convertible state of the behavior model is determined to be convertible. If no corresponding conversion rule exists, the convertible state of the behavior model can be determined to be non-convertible. In the case that the transformable state corresponding to the behavior model is determined to be transformable (i.e., the first state), a transformation rule corresponding to the behavior model is determined based on the identification information of the behavior model.

In some alternative embodiments, a switchable identification library or a switchable identification list may be set for a behavior model of an existing conversion rule, and a mapping relationship between switchable identification information and the conversion rule may be established. For each behavior model traversed, matching the identification information of the behavior model with a switchable identification library or a switchable identification list to determine the switchable state of the behavior model. If the transformable state of the behavior model is determined to be the first state, the transformation rule corresponding to the behavior model can be determined based on the mapping relation between the transformable identification information and the transformation rule.

In some alternative embodiments, the transformation rules may be a transformation code function described in any implementable language. Including but not limited to various high-level languages. Thus, the conversion from the behavior model to the synthesizable model can be realized through function call.

In the embodiment, the convertible state of the behavior model is determined first, so that the convertible behavior model can be converted conveniently, and the non-convertible model can be processed in other modes to obtain a final comprehensive physical unit library.

In some alternative embodiments, determining the conversion rule corresponding to the behavior model in step 2021 based on the identification information of the behavior model further includes:

And responding to the switchable state to be the second state, and outputting prompt information corresponding to the behavior model.

Wherein the second state is an unconverted state. For the non-convertible behavior model, corresponding prompt information can be output to prompt the user (such as a conversion rule developer) that the behavior model is non-convertible, and the user performs corresponding processing. For example, the user may provide corresponding conversion rules for the behavior model.

In some optional embodiments, after outputting the prompt information corresponding to the behavior model, the behavior model may be marked, the incomplete conversion of the behavior model is marked, then the next processing of the behavior model is performed, and after traversing each behavior model in the physical unit library, the marked incomplete conversion behavior model is subjected to secondary traversal, or the user triggers the secondary traversal of the incomplete conversion behavior model. For example, the process may be paused after one traversal is completed, and the user may be prompted by a pop-window, such as "whether there are physical units for which a translation is not complete, or whether to traverse again. The user can provide corresponding conversion rules for the behavior models of the physical units which are not converted, and then trigger secondary traversal to enable the device to continue traversing the behavior models which are not converted until conversion of all the behavior models in the physical unit library is completed, and the synthesizable physical unit library is obtained.

In the embodiment, when traversing to the non-convertible behavior model, prompt information can be output so as to prompt a user to perform corresponding processing in time.

In some optional embodiments, after outputting the prompt information corresponding to the behavior model, the method further includes:

acquiring a conversion rule corresponding to the behavior model input by a user; and converting the behavior model into a synthesizable model based on conversion rules corresponding to the behavior model.

The user may input the conversion rule corresponding to the behavior model in any implementable manner, for example, in a file manner. After the conversion rule corresponding to the behavior model input by the user is obtained, the behavior model can be converted into a synthesizable model based on the conversion rule.

In some optional embodiments, after obtaining a conversion rule corresponding to a behavior model input by a user, the apparatus of the present disclosure may store the conversion rule corresponding to identification information of the behavior model, and may add the identification information to a switchable identification library or a switchable identification list, so as to facilitate subsequent determination and conversion of a switchable state.

In some alternative embodiments, the user may also input conversion rules for multiple non-convertible behavior models together. After the device acquires the conversion rules of the behavior models, the conversion rules corresponding to the behavior models are stored. And traversing the behavior models which are not converted in the previous traversal process again, and converting each behavior model which is not converted according to the process to obtain the comprehensive physical unit library.

In this embodiment, for the behavior models that fail to be converted, the user may further provide a corresponding conversion rule to facilitate the continuous conversion of these behavior models that fail to be converted into a synthesizable model, so that an effective determination of a synthesizable physical unit library may be achieved in combination with a small amount of labor cost.

Fig. 4 is a flowchart illustrating a method for verifying a chip according to still another exemplary embodiment of the present disclosure.

In some alternative embodiments, as shown in fig. 4, the converting the physical unit library into the synthesizable physical unit library in step 202 further includes:

in response to completing the conversion of the behavior model in the physical unit library, an initial synthesizable physical unit library is obtained, step 2023.

The synthesizable physical unit library obtained by the conversion can be used as an initial synthesizable physical unit library.

And 2024, performing consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a consistency verification result corresponding to the initial synthesizable physical unit library.

In some alternative embodiments, the consistency verification may include at least one of functional consistency verification (i.e., verification consistency verification), formal consistency verification (i.e., consistency verification). The composition consistency verification is used for verifying the behavior function consistency of the obtained initial comprehensive physical unit library and the original physical unit library. For example, the same random excitation is applied to the synthesizable model and the corresponding behavior model in the initial synthesizable physical unit library, a first output result corresponding to the synthesizable model and a second output result corresponding to the behavior model are obtained, the first output result and the second output result are compared, and the consistency of the two results is verified. Formance consistency verification is used to perform netlist-level consistency verification. The same traversable stimulus can be applied to both models, and the output results of both models can be compared.

In some alternative embodiments, the consistency verification is based on verification of a software simulation tool to ensure accuracy of the conversion of the present disclosure.

In some alternative embodiments, the consistency of the initial synthesizable physical unit library and the original physical unit library can be cross-verified by different verification tools, so that verification of all functions is covered comprehensively, and the condition of insufficient chip verification caused by inaccurate conversion is avoided.

In step 2025, in response to the consistency verification result meeting the consistency condition, the initial synthesizable physical unit library is used as the synthesizable physical unit library corresponding to the physical unit library.

The consistency condition can be set according to actual requirements. For example, if the outputs of both models are identical for each identical stimulus applied to both models, it may be determined that the consistency verification result satisfies the consistency condition. If the consistency verification result meets the consistency condition, the obtained initial synthesizable physical unit library is consistent with the original physical unit library in behavior logic, and the initial synthesizable physical unit library can be used as a synthesizable physical unit library corresponding to the physical unit library for verification of the target verification platform.

In the embodiment, the obtained synthesizable physical unit library is used as the initial synthesizable physical unit library after conversion is completed, the consistency verification is performed on the initial synthesizable physical unit library and the original physical unit library, and the initial synthesizable physical unit library passing the verification can be used for replacing the original non-synthesizable physical unit library to verify the chip to be verified, so that the accuracy and the reliability of the obtained synthesizable physical unit library are ensured, and the reliability and the comprehensive coverage of the verification of the chip to be verified are ensured.

Fig. 5 is a flowchart illustrating a method for verifying a chip according to still another exemplary embodiment of the present disclosure.

In some alternative embodiments, step 2024 performs consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a consistency verification result corresponding to the initial synthesizable physical unit library, including:

step 20241, performing functional consistency verification on the physical unit library and the initial synthesizable physical unit library based on the preconfigured functional consistency verification environment, to obtain a first verification result.

The method comprises the steps of constructing a simulation environment of a physical unit aiming at a chip to be verified, simultaneously configuring an original physical unit library and a generated initial synthesizable physical unit library in the same simulation environment, keeping the same with the simulation environment of the chip to be verified, applying the same random excitation to two models of the two unit libraries to obtain output results corresponding to the two models respectively, comparing the output results of the two models, determining the consistency of the output results, and further determining a first verification result based on the consistency of the output results corresponding to the random excitation respectively.

And 20242, performing form consistency verification on the physical unit library and the initial synthesizable physical unit library based on the preconfigured form consistency verification environment to obtain a second verification result.

The form consistency verification is similar to the form consistency verification, a physical unit form environment of the chip to be verified can be built, the generated initial comprehensive physical unit library and the original physical unit library are configured in the same form environment, the initial comprehensive physical unit library is consistent with the form environment of the chip to be verified, the same traversable excitation is applied to the two models, output results of the two models are compared, and a second verification result is obtained based on the comparison result.

It should be noted that, the step 20241 and the step 20242 do not have a dependency relationship of an execution sequence, and may be executed simultaneously or sequentially, and there is no limitation on the execution sequence.

Step 20243, determining a consistency verification result based on the first verification result and the second verification result.

The combination mode of the first verification result and the second verification result can be set according to actual requirements.

According to the embodiment, the consistency verification results of the two unit libraries are determined by integrating the verification results of the two verification environments, so that cross verification among different verification tools can be realized, and the accuracy and reliability of the consistency verification results are improved.

In some alternative embodiments, determining the consistency verification result based on the first verification result and the second verification result includes:

responding to the first verification result and the second verification result to pass verification, and determining that the consistency verification result meets a consistency condition; and outputting prompt information of inconsistent verification results in response to any one of the first verification result and the second verification result being that verification is failed.

If the first verification result and the second verification result pass through verification, it can be determined that the initial synthesizable physical unit library has consistency with the original physical unit library, and the method can replace the original physical unit library to be used for verifying the chip to be verified on the target verification platform. If any one of the first verification result and the second verification result is not verified, the fact that the initial synthesizable physical unit library is inconsistent with the original physical unit library is indicated, and the verification of the chip to be verified cannot be performed by replacing the original physical unit library. In order to solve the problem, a prompt message of inconsistent verification results can be output, and a user is prompted in time to perform corresponding processing. For example, the user may troubleshoot the cause of the inconsistency based on the hint information and may adjust the initial synthesizable physical cell library or adjust the conversion rules used to generate the synthesizable model. The specific examples are not limited. The output mode of the prompt information and the specific content of the output are not limited. For example, stimulus that produces inconsistent output and inconsistent output, as well as the specific location at which the stimulus is applied, may be output to facilitate a user in quickly locating the inconsistent location.

In the embodiment, corresponding prompt information can be output for the condition that the consistency verification result fails, so that a user can process corresponding conditions in time.

In some alternative embodiments, step 2022 converts the behavioral model to a synthesizable model based on conversion rules corresponding to the behavioral model, including:

detecting the starting position and the ending position of the content to be converted in the behavior model based on the detection rule corresponding to the behavior model; determining the content to be converted in the behavior model based on the starting position and the ending position; and converting the content to be converted into target content meeting the preset conditions of the target verification platform, and obtaining a synthesizable model corresponding to the behavior model.

The detection rule may be based on keywords included in the behavior model and parameter settings of the behavior model. For example, for an and () physical element, a plurality of parameters may be included in the behavior model, and a detection rule is set according to the attribute of the parameter and the requirement of the parameter in a synthesizable model of the adaptive target verification platform, so as to identify the start position and the end position of the content to be converted in the behavior model. The content to be converted may include at least one of content to be replaced, content to be culled, and the like. For the content to be replaced, the content is converted from an uncombinable description mode to a synthesizable description mode. And eliminating the content to be eliminated. Such as redundancy parameters, redundancy logic culling, etc.

In some alternative embodiments, the same behavior model may include a different number of parameters, such as an and () behavior model, may include a different number of inputs and an internally different number of AND logics. The conversion rule corresponding to each behavior model can also comprise a synthesizable model template corresponding to the behavior model and template filling rules corresponding to different parameters, wherein the synthesizable model template can comprise sharable parts under different parameters and parts which need to be filled differently for different parameters. And further, for any traversed behavior model, the synthesizable model template can be filled according to the specific condition of the behavior model, so as to obtain a corresponding synthesizable model.

According to the embodiment, the content to be converted of the behavior model is detected and identified, so that the content to be converted is converted, the corresponding synthesizable model is obtained, and accurate and effective conversion of the synthesizable model is realized.

According to the embodiment of the disclosure, in the process of verifying the chip to be verified based on the target verification platform, a synthesizable model consistent with the design of the chip to be verified can be adopted when the power supply network of the chip to be verified is verified in the RTL stage, and the functions of the chip to be verified can be truly simulated in the later netlist verification stage, including joint debugging of the power supply network and other functions, so that the sufficiency of chip verification can be improved.

The embodiments of the present disclosure may be implemented alone or in any combination without collision, and may specifically be set according to actual needs, which is not limited by the present disclosure.

Any of the chip verification methods provided by the embodiments of the present disclosure may be performed by any suitable device having data processing capabilities, including, but not limited to: terminal equipment, servers, etc. Alternatively, the method for verifying any chip provided in the embodiments of the present disclosure may be executed by a processor, for example, the processor may execute the method for verifying any chip mentioned in the embodiments of the present disclosure by calling a corresponding instruction stored in a memory. And will not be described in detail below.

Exemplary apparatus

Fig. 6 is a schematic structural diagram of a verification device for a chip according to an exemplary embodiment of the present disclosure. The device of this embodiment may be used to implement an embodiment of a verification method of a chip according to the present disclosure, where the device shown in fig. 6 includes: an acquisition module 51, a first processing module 52 and a second processing module 53.

The obtaining module 51 is configured to obtain a physical unit library of the chip to be verified, where the physical unit library includes behavior models corresponding to each physical unit of the chip to be verified.

A first processing module 52, configured to convert the physical unit library into a synthesizable physical unit library; the comprehensive physical unit library comprises a comprehensive model meeting the preset conditions of the target verification platform; the synthesizable model is a model that is logically consistent with the behavior of the behavior model that can be synthesized into a netlist.

The second processing module 53 is configured to verify, by using the target verification platform, the chip to be verified based on the synthesizable model in the synthesizable physical unit library, and obtain a verification result.

Fig. 7 is a schematic structural diagram of a verification device for a chip according to another exemplary embodiment of the present disclosure.

In some alternative embodiments, the first processing module 52 includes: a first processing unit 521 and a second processing unit 522.

The first processing unit 521 is configured to determine, for a behavior model corresponding to any physical unit in the physical unit library, a conversion rule corresponding to the behavior model based on identification information of the behavior model.

The second processing unit 522 is configured to convert the behavior model into a synthesizable model based on a conversion rule corresponding to the behavior model.

In some alternative embodiments, the first processing unit 521 is specifically configured to:

In some alternative embodiments, the first processing unit 521 is further configured to: and responding to the switchable state to be the second state, and outputting prompt information corresponding to the behavior model.

In some alternative embodiments, the first processing module 52 further includes: an obtaining unit 523 is configured to obtain a conversion rule corresponding to the behavior model input by the user. The second processing unit 522 is specifically configured to convert the behavior model into a synthesizable model based on a conversion rule corresponding to the behavior model.

In some alternative embodiments, the first processing module 52 further comprises: a third processing unit 524, a fourth processing unit 525, and a fifth processing unit 526.

And a third processing unit 524, configured to obtain an initial synthesizable physical cell library in response to completing the conversion of the behavior model in the physical cell library.

And a fourth processing unit 525, configured to perform consistency verification on the physical unit library and the initial synthesizable physical unit library, and obtain a consistency verification result corresponding to the initial synthesizable physical unit library.

And a fifth processing unit 526, configured to, in response to the consistency verification result satisfying the consistency condition, use the initial synthesizable physical unit library as a synthesizable physical unit library corresponding to the physical unit library.

In some alternative embodiments, the fourth processing unit 525 is specifically configured to:

and based on a pre-configured function consistency verification environment, performing function consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a first verification result. And based on a preconfigured form consistency verification environment, performing form consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a second verification result. And determining a consistency verification result based on the first verification result and the second verification result.

In some alternative embodiments, the second processing unit 522 is specifically configured to:

The beneficial technical effects corresponding to the exemplary embodiments of the present apparatus may refer to the corresponding beneficial technical effects of the foregoing exemplary method section, and will not be described herein.

ExampleSex electronic device

Fig. 8 is a block diagram of an electronic device provided in an embodiment of the present disclosure, including at least one processor 11 and a memory 12.

The processor 11 may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

Memory 12 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program instructions may be stored on a computer readable storage medium and executed by the processor 11 to implement the methods and/or other desired functions of the various embodiments of the present disclosure above.

In one example, the electronic device 10 may further include: an input device 13 and an output device 14, which are interconnected by a bus system and/or other forms of connection mechanisms (not shown).

The input means 13 may also comprise, for example, a keyboard, a mouse, etc.

The output device 14 may output various information to the outside, which may include, for example, a display, a speaker, a printer, and a communication network and a remote output apparatus connected thereto, etc.

Of course, only some of the components of the electronic device 10 relevant to the present disclosure are shown in fig. 8, with components such as buses, input/output interfaces, etc. omitted for simplicity. In addition, the electronic device 10 may include any other suitable components depending on the particular application.

Exemplary computer program product and computer readable storage Medium

In addition to the methods and apparatus described above, embodiments of the present disclosure may also provide a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform steps in the methods of the various embodiments of the present disclosure described in the "exemplary methods" section above.

The computer program product may write program code for performing the operations of embodiments of the present disclosure in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

Furthermore, embodiments of the present disclosure may also be a computer-readable storage medium, having stored thereon computer program instructions, which when executed by a processor, cause the processor to perform the steps in the methods of the various embodiments of the present disclosure described in the "exemplary methods" section above.

A computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example but not limited to, a system, apparatus, or device including electronic, magnetic, optical, electromagnetic, infrared, or semiconductor, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The basic principles of the present disclosure have been described above in connection with specific embodiments, but the advantages, benefits, effects, etc. mentioned in this disclosure are merely examples and are not to be considered as necessarily possessed by the various embodiments of the present disclosure. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, since the disclosure is not necessarily limited to practice with the specific details described.

Various modifications and alterations to this disclosure may be made by those skilled in the art without departing from the spirit and scope of this application. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A method of chip verification, comprising:

acquiring a physical unit library of a chip to be verified, wherein the physical unit library comprises behavior models corresponding to physical units of the chip to be verified;

converting the physical unit library into a synthesizable physical unit library; the comprehensive physical unit library comprises a comprehensive model meeting the preset conditions of the target verification platform; the synthesizable model is a model which is consistent with the behavior logic of the behavior model and can be synthesized into a netlist;

And verifying the chip to be verified through the target verification platform based on the synthesizable model in the synthesizable physical unit library to obtain a verification result.

2. The method of claim 1, wherein the converting the physical unit library into a synthesizable physical unit library comprises:

determining a conversion rule corresponding to a behavior model corresponding to any physical unit in the physical unit library based on identification information of the behavior model;

and converting the behavior model into a synthesizable model based on conversion rules corresponding to the behavior model.

3. The method of claim 2, wherein the determining the conversion rule corresponding to the behavior model based on the identification information of the behavior model includes:

determining a convertible state corresponding to the behavior model based on the identification information of the behavior model;

and responding to the convertible state as a first state, and determining a conversion rule corresponding to the behavior model based on the identification information.

4. A method according to claim 3, further comprising:

and responding to the convertible state as the second state, and outputting prompt information corresponding to the behavior model.

5. The method according to claim 4, wherein after outputting the prompt information corresponding to the behavior model, further comprising:

acquiring a conversion rule corresponding to the behavior model input by the user;

6. The method of any of claims 2-5, wherein said converting said library of physical units into a synthesizable library of physical units further comprises:

obtaining an initial synthesizable physical cell library in response to completion of the conversion of the behavioral model in the physical cell library;

performing consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a consistency verification result corresponding to the initial synthesizable physical unit library;

and responding to the consistency verification result to meet a consistency condition, and taking the initial synthesizable physical unit library as the synthesizable physical unit library corresponding to the physical unit library.

7. The method of claim 6, wherein the performing consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a consistency verification result corresponding to the initial synthesizable physical unit library comprises:

Based on a pre-configured function consistency verification environment, performing function consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a first verification result;

based on a preconfigured form consistency verification environment, performing form consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a second verification result;

and determining the consistency verification result based on the first verification result and the second verification result.

8. The method of claim 7, wherein the determining the consistency verification result based on the first verification result and the second verification result comprises:

responding to the first verification result and the second verification result to pass verification, and determining that the consistency verification result meets the consistency condition;

and outputting prompt information of inconsistent verification results in response to any one of the first verification result and the second verification result being that verification is failed.

9. The method according to any one of claims 2-5, wherein the converting the behavior model into a synthesizable model based on the conversion rules corresponding to the behavior model comprises:

Detecting the starting position and the ending position of the content to be converted in the behavior model based on the detection rule corresponding to the behavior model;

determining the content to be converted in the behavior model based on the starting position and the ending position;

and converting the content to be converted into target content meeting the preset conditions of the target verification platform, and obtaining the synthesizable model corresponding to the behavior model.

10. A chip verification apparatus, comprising:

the acquisition module is used for acquiring a physical unit library of the chip to be verified, wherein the physical unit library comprises behavior models corresponding to all physical units of the chip to be verified;

the first processing module is used for converting the physical unit library into a synthesizable physical unit library; the comprehensive physical unit library comprises a comprehensive model meeting the preset conditions of the target verification platform; the synthesizable model is a model which is consistent with the behavior logic of the behavior model and can be synthesized into a netlist;

and the second processing module is used for verifying the chip to be verified through the target verification platform based on the synthesizable model in the synthesizable physical unit library to obtain a verification result.

11. A computer readable storage medium storing a computer program for executing the method of verification of a chip as claimed in any one of the preceding claims 1-9.

12. An electronic device, the electronic device comprising:

a processor;

a memory for storing the processor-executable instructions;

the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for verifying a chip according to any one of claims 1-9.