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CN113748500A - 静电卡盘 - Google Patents

静电卡盘 Download PDF

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CN113748500A
CN113748500A CN202080031109.5A CN202080031109A CN113748500A CN 113748500 A CN113748500 A CN 113748500A CN 202080031109 A CN202080031109 A CN 202080031109A CN 113748500 A CN113748500 A CN 113748500A
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ceramic
dielectric layer
insulating layer
electrostatic chuck
ceramic dielectric
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竹林央史
相川贤一郎
久野达也
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NGK Insulators Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/19—Soldering, e.g. brazing, or unsoldering taking account of the properties of the materials to be soldered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
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    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
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Abstract

静电卡盘具备陶瓷基材、陶瓷电介质层、静电电极和陶瓷绝缘层。陶瓷电介质层配置在陶瓷基材上，比陶瓷基材薄。静电电极埋设在陶瓷电介质层与陶瓷基材之间。陶瓷绝缘层配置在陶瓷电介质层上，比陶瓷电介质层薄。陶瓷绝缘层的体积电阻率及耐电压比所述陶瓷电介质层高，陶瓷电介质层的介电常数比陶瓷绝缘层高。

Description

静电卡盘
技术领域
本发明涉及静电卡盘。
背景技术
以往，在半导体晶片的传送、曝光、CVD等成膜工艺、清洗、蚀刻、切割等微细加工中，使用吸附保持晶片的静电卡盘。例如，专利文献1所公开的静电卡盘具有：陶瓷基材、配置在陶瓷基材上的薄的陶瓷电介质层、以及埋设在陶瓷电介质层与陶瓷基材之间的静电电极(参照图4)。陶瓷电介质层的表面为晶片载置面。在该静电卡盘中，陶瓷基材的材质和陶瓷电介质层的材质均为氧化铝烧结体。
现有技术文献
专利文献
专利文献1：日本特开2005-343733号公报
发明内容
发明所要解决的课题
但是，由于陶瓷电介质层的材质为氧化铝烧结体，因此虽然绝缘性能(体积电阻率、耐电压)高，但介电常数没有那么高。因此，有时无法充分得到将晶片吸附于晶片载置面时的静电吸附力。
本发明是为了解决这样的课题而完成的，其主要目的在于提供一种绝缘性能和静电吸附力都高的静电卡盘。
用于解决课题的方案
本发明的静电卡盘具备：
陶瓷基材；
陶瓷电介质层，其配置在所述陶瓷基材上并比所述陶瓷基材薄；
静电电极，其埋设在所述陶瓷电介质层与所述陶瓷基材之间；以及
陶瓷绝缘层，其配置在所述陶瓷电介质层上并比所述陶瓷电介质层薄，
所述陶瓷绝缘层的体积电阻率及耐电压比所述陶瓷电介质层高，
所述陶瓷电介质层的介电常数比所述陶瓷绝缘层高。
在该静电卡盘中，由于陶瓷绝缘层的体积电阻率及耐电压比陶瓷电介质层高，因此绝缘性能由于该陶瓷绝缘层而被保持得高。另一方面，由于陶瓷电介质层的介电常数比陶瓷绝缘层高，因此与介电常数成比例地变高的静电吸附力由于陶瓷电介质层而变高。这样，本发明的静电卡盘的绝缘性能和静电吸附力都高。
在本发明的静电卡盘中，所述陶瓷绝缘层也可以是气溶胶沉积(AD)膜或喷镀膜。特别优选陶瓷绝缘层为AD膜。AD膜在原料粒子彼此的晶界不存在绝缘性低的玻璃相，与使原料粒子烧结而成的膜为同等程度，因此体积电阻率、耐电压变高。
在本发明的静电卡盘中，优选所述陶瓷电介质层的材质为钛酸钡或锆钛酸铅，所述陶瓷绝缘层的材质优选为氧化铝。
在本发明的静电卡盘中，所述陶瓷绝缘层可以以覆盖所述陶瓷电介质层的整个表面的方式设置，且具有支撑晶片的多个凸部。
在本发明的静电卡盘中，所述陶瓷电介质层可以具有支撑晶片的多个凸部，所述陶瓷绝缘层至少设置于所述凸部的顶面。在陶瓷绝缘层中，陶瓷绝缘层也可以覆盖陶瓷电介质层的整个表面而不仅仅覆盖陶瓷电介质层的凸部。
附图说明
图1是本实施方式的静电卡盘的纵剖视图。
图2是另一实施方式的静电卡盘的纵剖视图。
图3是另一实施方式的静电卡盘的纵剖视图。
图4是以往的静电卡盘的纵剖视图。
具体实施方式
以下，参照附图来说明本发明的优选的实施方式。图1是晶片载置台的制造工序图(纵剖视图)。
如图1所示，静电卡盘具备陶瓷基材、陶瓷电介质层、静电电极和陶瓷绝缘层。陶瓷电介质层配置在陶瓷基材上，且比陶瓷基材薄。在本实施方式中，陶瓷电介质层和陶瓷基材是一体烧成的陶瓷烧结体。静电电极埋设在陶瓷电介质层与陶瓷基材之间。陶瓷绝缘层配置在陶瓷电介质层上，且比陶瓷电介质层薄。陶瓷绝缘层的体积电阻率及耐电压比陶瓷电介质层高，陶瓷电介质层的介电常数比陶瓷绝缘层高。
陶瓷绝缘层可以是CVD膜或PVD膜，但从能够比较容易地使膜厚变厚的方面考虑，优选为AD膜或喷镀膜。特别是，AD膜在原料粒子彼此的晶界不存在绝缘性低的玻璃相，与使原料粒子烧结而成的膜为同等程度，因此体积电阻率、耐电压变高。AD膜是由AD法(包括等离子体AD法)形成的膜。AD法由于能够通过冲击固化现象使陶瓷粒子成膜，因此不需要在高温下对陶瓷粒子进行烧结。
陶瓷电介质层的材质优选为钛酸钡或锆钛酸铅，陶瓷绝缘层的材质优选为氧化铝。
在以上说明的本实施方式的静电卡盘中，由于陶瓷绝缘层的体积电阻率及耐电压比陶瓷电介质层高，因此绝缘性能由于该陶瓷绝缘层而被保持得高。另一方面，由于陶瓷电介质层的介电常数比陶瓷绝缘层高，因此与介电常数成比例地变高的静电吸附力由于陶瓷电介质层而变高。
需说明的是，不言而喻，本发明不受上述的实施方式的任何限制，只要属于本发明的技术范围内就可用各种方式来实施。
例如，在上述的实施方式中，陶瓷绝缘层也可以以覆盖陶瓷电介质层的整个表面的方式设置并具有支撑晶片的多个凸部(参照图2)。关于这样的结构，也可以例如以覆盖陶瓷电介质层的整个表面的方式形成AD膜，在将该AD膜的表面精加工成镜面(例如表面粗糙度Ra为0.1μm以下的面)之后，利用AD法(包括等离子体AD法)在该镜面上形成多个凸部。这样一来，由于未形成凸部的部分保持镜面的状态，因此不会成为在半导体工艺中产生微粒的原因。
在上述的实施方式中，也可以是陶瓷电介质层具有支撑晶片的多个凸部，陶瓷绝缘层仅设置在凸部的顶面(参照图3)，但从提高耐电压的观点出发，优选覆盖陶瓷电介质层的整个表面而不仅仅覆盖陶瓷电介质层的凸部。
在上述的实施方式中，也可以在陶瓷基材中埋设RF电极和加热器电极(电阻发热体)中的至少一者。
本申请将2019年6月28日申请的日本专利申请第2019-121488号作为优先权主张的基础，通过引用将其全部内容包含在本说明书中。
产业上的利用可能性
本发明能够用于例如半导体晶片的传送、曝光、CVD等成膜工艺、清洗、蚀刻、切割等微细加工。

Claims (5)

1.一种静电卡盘，具备：
陶瓷基材；
陶瓷电介质层，其配置在所述陶瓷基材上并比所述陶瓷基材薄；
静电电极，其埋设在所述陶瓷电介质层与所述陶瓷基材之间；以及
陶瓷绝缘层，其配置在所述陶瓷电介质层上并比所述陶瓷电介质层薄，
所述陶瓷绝缘层的体积电阻率及耐电压比所述陶瓷电介质层高，
所述陶瓷电介质层的介电常数比所述陶瓷绝缘层高。
2.根据权利要求1所述的静电卡盘，其中，所述陶瓷绝缘层为气溶胶沉积膜或喷镀膜。
3.根据权利要求1或2所述的静电卡盘，其中，所述陶瓷电介质层的材质为钛酸钡或锆钛酸铅，所述陶瓷绝缘层的材质为氧化铝。
4.根据权利要求1至3中任一项所述的静电卡盘，其中，所述陶瓷绝缘层以覆盖所述陶瓷电介质层的整个表面的方式设置，具有支撑晶片的多个凸部。
5.根据权利要求1至3中任一项所述的静电卡盘，其中，所述陶瓷电介质层具有支撑晶片的多个凸部，所述陶瓷绝缘层至少设置在所述凸部的顶面。
CN202080031109.5A 2019-06-28 2020-06-10 静电卡盘 Pending CN113748500A (zh)

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JP2022142421A (ja) * 2021-03-16 2022-09-30 株式会社巴川製紙所 静電チャック装置およびその製造方法
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