CN113745250A - Array substrate, preparation method of array substrate and display panel - Google Patents

Abstract

The embodiments of the present application disclose an array substrate, a method for preparing the array substrate, and a display panel, including a substrate, a touch wire and an active layer, and the touch wire and the active layer are arranged in the same layer. Since the touch traces and the active layer are arranged in the same layer, the active layer and the touch traces can be formed at the same time by one mask process, which can reduce the number of masks required for the preparation of the array substrate, thereby reducing the cost. Effect.

Description

Array substrate, preparation method of array substrate and display panel

technical field

The present application relates to the field of display, and in particular, to an array substrate, a method for preparing the array substrate, and a display panel.

Background technique

At present, the liquid crystal display technology has strong market competitiveness due to the low cost of the liquid crystal display technology. In the liquid crystal display technology, the fringe field switching technology (Fringe Field Switching, FFS) display mode has a larger viewing angle and can integrate a touch module, so it is favored by a large number of panel manufacturers.

However, due to the complexity of the structure of the FFS display structure, eight mask processes are generally required to form it, thereby increasing the fabrication cost of the FFS display structure.

Therefore, how to reduce the number of masks required to prepare the FFS display structure in order to reduce the cost is a difficulty that panel manufacturers need to overcome.

SUMMARY OF THE INVENTION

Embodiments of the present application provide an array substrate, a method for fabricating the array substrate, and a display panel, so as to solve the technical problem of high fabrication cost of an FFS display structure in the prior art.

An embodiment of the present application provides an array substrate, the array substrate includes a thin film transistor region and a pixel electrode region, the pixel electrode region is disposed on one side of the thin film transistor region, and the array substrate includes:

substrate;

touch traces, the touch traces are disposed on the substrate, and the touch traces are located in the pixel electrode region;

an active layer, the active layer is disposed on the substrate, and the active layer is located in the thin film transistor region, the active layer and the touch trace are disposed in the same layer, and the touch The material of the trace is a semiconductor material, and the material of the touch trace is the metallized semiconductor material.

Optionally, in some embodiments of the present application, the array substrate further includes a source and drain, a dielectric layer, a gate insulating layer, and a gate, the source and drain are disposed on the substrate, and the A dielectric layer is disposed on the source and drain electrodes, the active layer is disposed on the dielectric layer, a via hole is disposed on the dielectric layer, and the active layer is connected to the active layer through the via hole. The source and drain are connected, the gate insulating layer is arranged on the active layer, and the gate is arranged on the gate insulating layer.

Optionally, in some embodiments of the present application, the array substrate further includes a common electrode, the common electrode is located in the pixel electrode region, the common electrode, the active layer and the touch traces The same layer is provided, and the material of the common electrode is the metallized semiconductor material.

Optionally, in some embodiments of the present application, the distance between the common electrode and the touch trace is greater than or equal to 6 microns.

Optionally, in some embodiments of the present application, the array substrate further includes a passivation layer and a pixel electrode, the passivation layer is provided on the active layer and covers the gate insulating layer, gate electrode and a common electrode, the passivation layer is provided with a connection hole, and the pixel electrode is connected to the source and drain through the connection hole.

Optionally, in some embodiments of the present application, the metal layer includes a source electrode and a drain electrode, and an orthographic projection of the gate electrode on a plane where the substrate is located is located on a plane where the source electrode is located on the substrate. in the orthographic projection.

Optionally, in some embodiments of the present application, the array substrate further includes a low-impedance layer, the low-impedance layer is located in the pixel electrode region, and the low-impedance layer and the source and drain electrodes are disposed in the same layer, A through hole is provided on the dielectric layer, and the common electrode is connected to the low resistance layer through the through hole.

Correspondingly, an embodiment of the present application further provides a method for preparing an array substrate, the array substrate includes a thin film transistor region and a pixel electrode region, and the pixel electrode region is arranged on one side of the thin film transistor region, and the preparation method include:

providing a substrate, and disposing a semiconductor material on the substrate to form a semiconductor layer;

The semiconductor layer is patterned to form an active layer and touch traces, the active layer is located in the thin film transistor area, the touch traces are located in the pixel electrode area, and the active layer is located in the pixel electrode area. The layer and the touch wire are arranged in the same layer, the active layer is the semiconductor material, and the material of the touch wire is the metallized semiconductor material.

Optionally, in some embodiments of the present application, providing a substrate and forming a semiconductor layer on the substrate includes the following steps:

providing a substrate, and forming source and drain on the substrate;

forming a dielectric layer on the source and drain electrodes, the dielectric layer covering the source and drain electrodes;

A semiconductor layer is formed on the source and drain.

Correspondingly, an embodiment of the present application further provides a display panel, the display panel includes a liquid crystal layer, a color filter substrate and the above-mentioned array substrate, the liquid crystal layer is disposed on the array substrate, and the color filter substrate arranged on the liquid crystal layer; wherein,

The color filter substrate includes a color resist layer, a black matrix and a substrate, the color resist layer and the black matrix are arranged in the same layer, the color resist layer is arranged opposite to the pixel electrode, and the substrate is arranged on the color resist layer. The barrier layer is on the side away from the liquid crystal layer.

The embodiment of the present application adopts an array substrate, a preparation method for preparing the substrate, and a display panel, including a substrate, a touch wiring and an active layer, and the touch wiring and the active layer are arranged in the same layer. Since the touch traces and the active layer are arranged in the same layer, the active layer and the touch traces can be formed at the same time by one mask process, which can reduce the number of masks required to prepare the array substrate, thereby reducing the cost. Effect.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a schematic diagram of a first structure of an array substrate provided by an embodiment of the present application.

FIG. 2 is a schematic diagram of a second structure of an array substrate provided by an embodiment of the present application.

FIG. 3 is a schematic diagram of a third structure of an array substrate provided by an embodiment of the present application.

FIG. 4 is a schematic diagram of a fourth structure of an array substrate provided by an embodiment of the present application.

FIG. 5 is a schematic diagram of a fifth structure of an array substrate provided by an embodiment of the present application.

FIG. 6 is a schematic diagram of a sixth structure of an array substrate provided by an embodiment of the present application.

FIG. 7 is a schematic flowchart of the first embodiment of the method for fabricating the array substrate provided in the embodiment of the present application.

FIG. 8 is a schematic structural diagram of step 201 according to an embodiment of the present application.

FIG. 9 is a schematic structural diagram of step 202 provided in this embodiment of the present application.

FIG. 10 is a schematic sub-flow diagram of the first embodiment of the method for fabricating an array substrate provided by the embodiment of the present application.

FIG. 11 is a schematic structural diagram of step 2011 provided by this embodiment of the present application.

FIG. 12 is a schematic structural diagram of step 2012 provided by this embodiment of the present application.

FIG. 13 is a schematic flowchart of a second embodiment of the method for fabricating an array substrate provided in the embodiment of the present application.

FIG. 14 is a schematic structural diagram of step 401 of the array substrate provided by the embodiment of the present application.

FIG. 15 is a schematic diagram of a first structure of step 402 provided by this embodiment of the present application.

FIG. 16 is a schematic diagram of the second structure of step 402 provided by this embodiment of the present application.

FIG. 17 is a schematic flowchart of a third embodiment of the method for fabricating an array substrate provided in the embodiment of the present application.

FIG. 18 is a schematic structural diagram of step 405 provided by this embodiment of the present application.

FIG. 19 is a schematic structural diagram of a display panel provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "thickness", "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings , is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present application. In the description of the present application, "plurality" means two or more, unless otherwise expressly and specifically defined.

In the description of the present application, it should be understood that the terms "first" and "second" are only used for descriptive purposes, and cannot be interpreted as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined as "first" and "second" etc. may expressly or implicitly include one or more of said features, and therefore should not be construed as limiting the application.

Embodiments of the present application provide an array substrate, a method for fabricating the array substrate, and a display panel. Each of them will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

Please refer to FIG. 1 , which is a schematic diagram of a first structure of an array substrate provided by an embodiment of the present application. As shown in FIG. 1 , the array substrate 10 provided in the embodiment of the present application includes a thin film transistor region 10a and a pixel electrode region 10b, and the pixel electrode region 10b is disposed on one side of the thin film transistor region 10a. The array substrate 10 includes a substrate 101 , touch traces 102 and an active layer 103 . The touch traces 102 are disposed on the substrate 101 . The touch traces 102 are located in the pixel electrode region 10b. The active layer 103 is provided on the substrate 101 . The active layer 103 is located in the thin film transistor region 10a. The active layer 103 and the touch traces 102 are disposed in the same layer, the material of the active layer 103 is a semiconductor material, and the material of the touch traces 102 is a metallized semiconductor material.

It should be noted that the metallized semiconductor material is a semiconductor material that changes from a non-metallic state to a metallic state under high pressure. The material of the touch wire 102 is a metallized semiconductor material, so although the touch wire 102 is formed of a semiconductor material, it can transmit signals.

The material of the active layer 103 is a semiconductor material, and specifically, the material of the active layer 103 is an oxide semiconductor or other types of semiconductors. The material of the active layer 103 is indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), gallium indium oxide (IGO), indium gallium tin oxide (IGTO) , one of indium zinc tin oxide (IZTO) and indium tin oxide (ITO).

The material of the touch traces 102 is an oxide semiconductor. Specifically, the materials of the touch traces 102 are indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), gallium indium oxide (IGO), indium gallium tin oxide (IGZO) one of indium zinc tin oxide (IZTO) and indium tin oxide (ITO).

It should be noted that, since the active layer 103 and the touch traces 102 are disposed in the same layer and can be formed of semiconductor materials, the active layer 103 and the touch traces 102 can be simultaneously formed by a single mask process, so that the The number of photomasks required for preparing the array substrate 10 is reduced, thereby reducing the cost.

Please refer to FIG. 2 , which is a schematic diagram of a second structure of an array substrate provided by an embodiment of the present application. As shown in FIG. 2 , the difference between the array substrate 10 shown in FIG. 2 and the array substrate 10 shown in FIG. 1 is that the array substrate 10 further includes source and drain electrodes 104 , a dielectric layer 105 , a gate insulating layer 106 and a gate electrode 107. The source and drain electrodes 104 are provided on the substrate 101 . The dielectric layer 105 is disposed on the source and drain electrodes 104 . The active layer 103 is disposed on the dielectric layer 105 . Via holes 105 a are provided on the dielectric layer 105 . The active layer 103 is connected to the source and drain electrodes 104 through the holes 105a. The gate insulating layer 106 is provided on the active layer 103 . The gate electrode 107 is provided on the gate insulating layer 106 .

In the prior art, the dielectric layer and the gate insulating layer of the thin film transistor structure are not independent of each other, therefore, the dielectric layer between the gate electrode and the source and drain electrodes is the gate insulating layer. Therefore, in the existing thin film transistor structure, the withstand voltage characteristics and cross-line capacitance between the gate and the source and drain are determined by the material and thickness of the gate insulating layer. The better the withstand voltage characteristics, the lower the cross-line capacitance; the driving voltage between the gate and the source is determined by the thickness of the gate insulating layer. The thicker the gate insulating layer, the higher the driving voltage between the gate and the source. big. In order to improve the gate and source-drain withstand voltage characteristics and reduce the cross-line capacitance, it is necessary to increase the thickness of the gate insulating layer, and increasing the thickness of the gate insulating layer will increase the driving voltage between the gate and the source. Therefore, the existing thin film transistor structure cannot have good gate and source-drain withstand voltage characteristics, low cross-line capacitance, and low gate-source driving voltage at the same time.

It should be noted that, the array substrate 10 provided in the embodiment of the present application adopts a top-gate thin film transistor structure, and the dielectric layer 105 and the gate insulating layer 106 are two independent film layers. Therefore, in the array substrate 10 provided by the embodiment of the present application, the withstand voltage characteristics between the gate 107 and the source and drain 104 and the cross-line capacitance are determined by the material and thickness of the dielectric layer 105 between the gate 107 and the source and drain 104 Decide. The driving voltage between the gate and the source is determined by the thickness of the gate insulating layer 106 . Among them, the array substrate 10 provided by the embodiment of the present application can increase the withstand voltage characteristic and the cross-line capacitance between the gate electrode 107 and the source and drain electrodes 104 by increasing the thickness of the dielectric layer 105. The array substrate 10 provided by the embodiment of the present application The driving voltage between the gate and the source can be reduced by reducing the thickness of the gate insulating layer 106. Therefore, the array substrate 10 provided by the embodiment of the present application can have good gate and source-drain withstand voltage characteristics, low Cross-line capacitance and low gate-to-source drive voltage.

The materials of the source and drain electrodes 104 are molybdenum (Mo), a stack of molybdenum (Mo) and aluminum (Al), a stack of molybdenum (Mo) and copper (Cu), molybdenum-titanium alloy (MoTi) and copper (Cu) ) stack, molybdenum-titanium alloy (MoTi)-copper (Cu)-molybdenum-titanium alloy (MoTi) stack, titanium-aluminum alloy (TiAl) and aluminum (Al) stack, titanium (Ti)-copper (Cu) )-titanium (Ti) stack, molybdenum (Mo)-copper (Cu)-indium zinc oxide (IZO) stack, indium zinc oxide (IZO)-copper (Cu)-indium zinc oxide (IZO) stack layer, molybdenum (Mo)-copper (Cu)-indium tin oxide (ITO) stack, nickel (Ni)-copper (Cu)-nickel (Ni) stack, molybdenum-titanium-nickel alloy (MoTiNi)-copper ( Cu)-molybdenum-titanium-nickel alloy (MoTiNi) lamination, molybdenum-nickel alloy (MoNi)-copper (Cu)-molybdenum-nickel alloy (MoNi) lamination, nickel-chromium alloy (NiCr)-copper (Cu)-nickel-chromium Alloy (NiCr) stack, titanium-nickel alloy (TiNi)-copper (Cu)-titanium-nickel alloy (TiNi) stack, titanium-chromium alloy (TiCr)-copper (Cu)-titanium-chromium alloy (TiCr) stack layer and one of copper niobium alloy (CuNb).

Wherein, in one embodiment, the source and drain electrodes 104 include a source electrode 104a and a drain electrode 104b. The orthographic projection of the gate electrode 107 on the plane of the substrate 101 is located within the orthographic projection of the source electrode 104 a on the plane of the substrate 101 .

It should be noted that, since the orthographic projection of the gate 107 on the plane where the substrate 101 is located is located in the orthographic projection of the source 104a on the plane where the substrate 101 is located, the source 104a can also play a role of shading, so it is not necessary to provide a shading Floor.

The material of the dielectric layer 105 is one of silicon oxide, a stack of silicon oxide and silicon nitride, silicon nitride and silicon oxynitride. The material of the gate insulating layer 106 is one of silicon oxide, a stack of silicon oxide and silicon nitride, silicon nitride and silicon oxynitride.

The material of the gate layer 107 is molybdenum (Mo), a stack of molybdenum (Mo) and aluminum (Al), a stack of molybdenum (Mo) and copper (Cu), molybdenum (Mo)-copper (Cu)- Indium zinc oxide (IZO) stack, indium zinc oxide (IZO)-copper (Cu)-indium zinc oxide (IZO) stack, molybdenum (Mo)-copper (Cu)-indium tin oxide (ITO) stack layer, nickel (Ni)-copper (Cu)-nickel (Ni) stack, molybdenum-titanium-nickel alloy (MoTiNi)-copper (Cu)-molybdenum-titanium-nickel alloy (MoTiNi) stack, nickel-chromium alloy (NiCr) - One of a copper (Cu)-nickel-chromium alloy (NiCr) laminate and a copper-niobium alloy (CuNb).

Please refer to FIGS. 3 and 4 , FIG. 3 is a schematic diagram of a third structure of an array substrate provided by an embodiment of the present application, and FIG. 3 is a schematic diagram of a fourth structure of an array substrate provided by an embodiment of the present application. As shown in FIG. 3 and FIG. 4 , the array substrate 10 provided in this embodiment of the present application further includes a common electrode 108 . The common electrode 108 is located in the pixel electrode region 10b. The common electrode 108 , the active layer 103 and the touch traces 102 are disposed in the same layer.

It should be noted that the metallized semiconductor material is a semiconductor material that changes from a non-metallic state to a metallic state under high pressure. The material of the common electrode 108 is a metallized semiconductor material, so although the common electrode 108 is formed of a semiconductor material, it can play a role of transmitting signals.

The material of the common electrode 108 is an oxide semiconductor. Specifically, the material of the common electrode 108 is indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), gallium indium oxide (IGO), indium gallium tin oxide ( IGTO), one of indium zinc tin oxide (IZTO) and indium tin oxide (ITO).

It should be noted that, since the common electrode 108 , the active layer 103 and the touch traces 102 are arranged in the same layer and can be formed of oxide semiconductors, a mask process can be used to simultaneously form the common electrode 108 and the active layer 103 and touch traces 102 , thereby reducing the number of masks required for preparing the array substrate 10 , thereby reducing costs.

The distance L1 between the common electrode 108 and the touch traces 102 is greater than or equal to 6 microns. Specifically, the distance L1 between the common electrode 108 and the touch trace 102 is 6 microns, 7 microns, 8 microns or 10 microns. It should be noted that since there is a certain interval between the common electrode 108 and the touch trace 102 , the common electrode 108 and the touch trace 102 do not intersect, and the common electrode 108 and the touch trace 102 do not intersect with each other. influences. In addition, when the distance L1 between the common electrodes 108 and the touch traces 102 is less than or equal to 6 μm, the signals transmitted by the common electrodes 108 and the signals transmitted by the touch traces 102 will affect each other, thereby affecting the array substrate 10 display function and touch function.

In one embodiment, the common electrodes 108 and the touch traces 102 are arranged in parallel, wherein the common electrodes 108 and the touch traces 102 are arranged in parallel, so as to more effectively avoid the common electrodes 108 and the touch traces 102 interact with each other.

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of a fifth structure of an array substrate provided by an embodiment of the present application, as shown in FIG. 5 . The difference between the array substrate 10 shown in FIG. 5 and the array substrate 10 shown in FIG. 3 is that the array substrate 10 further includes a low impedance layer 109 . The low-resistance layer 109 is located in the pixel electrode region 10b, and the low-resistance layer 109 and the source and drain electrodes 104 are disposed in the same layer. A through hole 105a is provided on the dielectric layer 105 . The common electrode is connected to the low resistance layer 109 through the through hole 105a.

The material of the low-resistance layer 109 is one or a combination of copper, silver, aluminum, and copper-silver alloys.

It should be noted that since the material of the common electrode 108 is an oxide semiconductor, the impedance of the common electrode 108 is relatively high, which is not conducive to transmitting signals. Therefore, by connecting the common electrode 108 to the low-impedance layer 109 having a relatively low impedance, the efficiency of the signal transmission of the common electrode 108 can be improved.

Please refer to FIG. 6 . FIG. 6 is a schematic diagram of a sixth structure of an array substrate provided by an embodiment of the present application, as shown in FIG. 6 . The difference between the array substrate 10 shown in FIG. 6 and the array substrate 10 shown in FIG. 5 is that the array substrate 10 further includes a passivation layer 110 and a pixel electrode 111 . The passivation layer 110 is disposed on the active layer 103 and covers the gate insulating layer 106 , the gate electrode 107 and the common electrode 108 . The passivation layer 110 is provided with a connection hole 110a. The pixel electrode 111 is connected to the source and drain electrodes 104 through the connection hole 110a.

It should be noted that the common electrode 108 can control the deflection of the liquid crystal by forming a fringe field with the pixel electrode 111 through the passivation layer 110 .

The material of the passivation layer 110 is one of silicon oxide, a stack of silicon oxide and silicon nitride, silicon nitride and aluminum oxide. The material of the pixel electrode 111 is indium zinc oxide (IZO) or indium tin oxide (ITO).

The array substrate provided in the embodiment of the present application includes a substrate, a touch wire and an active layer, and the touch wire and the active layer are arranged in the same layer. Since the touch traces and the active layer are arranged in the same layer, the active layer and the touch traces can be formed at the same time by one mask process, which can reduce the number of masks required to prepare the array substrate, thereby reducing the cost. Effect.

Correspondingly, the embodiments of the present application further provide a method for preparing an array substrate. Please refer to FIGS. 7-9 , and FIG. 7 is a schematic flowchart of a first implementation manner of the method for fabricating an array substrate provided in an embodiment of the present application. As shown in FIG. 7 , the preparation method of the array substrate provided in the embodiment of the present application includes:

Step 201, providing a substrate 301, and disposing a semiconductor layer 302 on the substrate 301;

8 is a schematic structural diagram of step 201 provided by an embodiment of the present application. As shown in FIG. 8 , the array substrate 30 includes a thin film transistor region 30a and a pixel electrode region 30b. The pixel electrode region 30b is disposed on one side of the thin film transistor region 30a.

Step 202, patterning the semiconductor layer 302 to form the active layer 302a and the touch traces 302b. The active layer 302a is located in the thin film transistor region 30a. The touch traces 302b are located in the pixel electrode region 30b. The active layer 302a and the touch wire 302b are disposed in the same layer, and the material of the touch wire 302b is a metallized semiconductor material.

Wherein, FIG. 9 is a schematic structural diagram of step 202 provided by an embodiment of the present application.

It should be noted that the active layer 302a and the touch traces 302b are formed by a single mask process, so that the number of masks required for preparing the array substrate 10 can be reduced, thereby reducing the cost.

See Figures 10-12. FIG. 10 is a schematic sub-flow diagram of the first embodiment of the method for fabricating an array substrate provided by the embodiment of the present application. As shown in Figure 10, step 201 includes:

In step 2011 , a substrate 301 is provided, and source and drain electrodes 303 are formed on the substrate 301 .

It should be noted that the source and drain electrodes 303 are formed through a mask process. Specifically, a metal layer is first formed on the substrate 303 , and then the metal layer is patterned to form the source and drain electrodes 303 .

11 is a schematic structural diagram of step 2011 provided by an embodiment of the present application.

In step 2012 , a dielectric layer 304 is formed on the source and drain electrodes 303 , and the dielectric layer 304 covers the source and drain electrodes 303 .

12 is a schematic structural diagram of step 2012 provided by an embodiment of the present application.

It should be noted that, in the embodiment of the present application, a plurality of through holes are also arranged on the dielectric layer 304 through an etching process, so as to connect the source and drain electrodes 303 and the semiconductor layer 302

Step 2013 , forming a semiconductor layer 302 on the source and drain electrodes 304 .

Please refer to FIG. 13-FIG. 16. FIG. 13 is a schematic flowchart of a second implementation manner of the method for fabricating an array substrate provided by the embodiment of the present application. The preparation method of the array substrate shown in FIG. 13 includes the following steps:

In step 401 , a substrate 301 is provided, and a semiconductor layer 302 is provided on the substrate 301 .

14 is a schematic structural diagram of step 401 of the array substrate provided by the embodiment of the present application.

It should be noted that, before the semiconductor layer 302 is formed on the substrate 301, the source and drain electrodes 303 and the dielectric layer 304 are also formed on the substrate. The source and drain electrodes 303 are formed by an exposure and development process. In addition, when the source and drain electrodes 303 are formed through an exposure and development process, a low-resistance layer 305 is also formed. The low-resistance layer 305 is connected to the common electrode 302c through the hole 304a. The low-impedance layer 305 is used to improve the efficiency of the signal transmission of the common electrode 302c.

Step 402 , patterning the semiconductor layer 302 to form an active layer 302a, a touch trace 302b and a common electrode 302c. The active layer 302a is located in the thin film transistor region 30a. The touch traces 302b are located in the pixel electrode region 30b. The common electrode 302c is located in the pixel electrode region 30b. The active layer 302a, the touch traces 302b and the common electrodes 302c are disposed in the same layer, and the materials of the touch traces 302b and the common electrodes 302c are all metallized semiconductor materials.

15 is a schematic diagram of the first structure of step 402 provided in this embodiment of the present application. FIG. 16 is a schematic diagram of the second structure of step 402 provided by this embodiment of the present application.

It should be noted that the active layer 302a, the touch traces 302b and the common electrode 302c are formed by one mask process, which can reduce the number of masks required for preparing the array substrate 30, thereby reducing the cost.

The distance L2 between the touch traces 302b and the common electrode 302c is greater than or equal to 6 microns. Specifically, the distance L2 between the touch traces 302b and the common electrode 302c is 6 microns, 7 microns, 8 microns or 10 microns. It should be noted that since there is a certain interval between the touch traces 302b and the common electrodes 302c, the touch traces 302b and the common electrodes 302c do not intersect, and the touch traces 302b and the common electrodes 302c do not affect each other. In addition, when the distance L1 between the common electrode 302c and the touch trace 302b is less than or equal to 6 microns, the signal transmitted by the common electrode 302c and the signal transmitted by the touch trace 302b will affect each other, thereby affecting the array substrate 30 display function and touch function.

The active layer 302a is connected to the source and drain electrodes 303 through the connection hole 304b.

Please refer to FIGS. 17-18 , and FIG. 17 is a schematic flowchart of a third embodiment of the method for fabricating an array substrate provided by the embodiment of the present application. The difference between the preparation method of the array substrate shown in FIG. 17 and the preparation method of the array substrate shown in FIG. 13 is that after step 402, the method further includes:

403. Form a gate insulating layer 306 and a gate electrode 307 on the active layer 302a.

It should be noted that the gate insulating layer 306 and the gate electrode 307 are formed by the same mask. First, the gate electrode 307 is formed by an exposure and development process, and then the gate electrode 307 is used as a self-aligned pattern, and the gate insulating layer 306 is formed by an exposure and development process.

404 , forming a passivation layer 308 on the gate layer 307 , the passivation layer 308 covering the active layer 302 a , the touch traces 302 b , the common electrode 302 c , the gate insulating layer 306 and the gate layer 307 .

405 , forming a pixel electrode 309 on the passivation layer 308 .

18 is a schematic structural diagram of step 405 provided by an embodiment of the present application.

The pixel electrode 309 is connected to the source and drain electrodes 303 through the through hole 308a.

It should be noted that, both the passivation layer 308 and the pixel electrode 309 are formed by a simultaneous exposure and development process.

In addition, the above-mentioned embodiments have already described the array substrate in detail, therefore, the embodiments of the present application do not describe the array substrate in detail.

In the manufacturing method of the array substrate provided in the embodiment of the present application, the array substrate includes a substrate, a touch wire and an active layer, and the touch wire and the active layer are arranged in the same layer. Since the touch traces and the active layer are arranged in the same layer, the active layer and the touch traces can be formed at the same time by one mask process, which can reduce the number of masks required to prepare the array substrate, thereby reducing the cost. Effect.

Correspondingly, an embodiment of the present application further provides a display panel. Please refer to FIG. 19 , which is a schematic structural diagram of a display panel provided by an embodiment of the present application. As shown in FIG. 19 , the display panel 100 includes the liquid crystal layer 40 , the color filter substrate 50 and the array substrate 10 as described above. The liquid crystal layer 40 is disposed on the array substrate 10 . The color filter substrate 50 is disposed on the liquid crystal layer 40 . The color filter substrate 50 includes a color resist layer 501 , a black matrix 502 and a substrate 503 . The color resist layer 501 and the black matrix 502 are arranged in the same layer. The color resist layer 501 is disposed opposite to the pixel electrode 111 . The substrate 503 is disposed on the side of the color resist layer 501 away from the liquid crystal layer 40 .

In addition, the above embodiments have already described the array substrate 10 in detail, therefore, the embodiments of the present application do not describe the array substrate in detail.

The display panel provided in the embodiment of the present application includes a substrate, a touch wire and an active layer, and the touch wire and the active layer are arranged in the same layer. Since the touch traces and the active layer are arranged in the same layer, the active layer and the touch traces can be formed at the same time by one mask process, which can reduce the number of masks required to prepare the array substrate, thereby reducing the cost. Effect.

An array substrate, a method for fabricating an array substrate, and a display panel provided by the embodiments of the present application have been described above in detail. The principles and implementations of the present application are described with specific examples in this article. The descriptions of the above embodiments are only It is used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there will be changes in the specific embodiments and application scope. In summary, this specification The content should not be construed as a limitation on this application.

Claims (10)

1. An array substrate, characterized in that the array substrate comprises a thin film transistor region and a pixel electrode region, the pixel electrode region is disposed on one side of the thin film transistor region, and the array substrate comprises: substrate; touch traces, the touch traces are disposed on the substrate, and the touch traces are located in the pixel electrode region; an active layer, the active layer is disposed on the substrate, and the active layer is located in the thin film transistor region, the active layer and the touch traces are disposed in the same layer, the active layer The layers are semiconductor materials, and the touch traces are metallized semiconductor materials. 2 . The array substrate according to claim 1 , wherein the array substrate further comprises a source and drain, a dielectric layer, a gate insulating layer and a gate, and the source and drain are disposed on the substrate. 3 . , the dielectric layer is disposed on the source and drain electrodes, the active layer is disposed on the dielectric layer, a via hole is disposed on the dielectric layer, and the active layer passes through the A hole is connected with the source and drain, the gate insulating layer is arranged on the active layer, and the gate is arranged on the gate insulating layer. 3 . The array substrate according to claim 2 , wherein the source and drain electrodes comprise a source electrode and a drain electrode, and an orthographic projection of the gate electrode on a plane where the substrate is located is located between the source electrode and the drain electrode. 4 . In the orthographic projection of the plane on which the substrate lies. 4 . The array substrate according to claim 2 , wherein the array substrate further comprises a common electrode, the common electrode is located in the pixel electrode region, the common electrode, the active layer and the contact The control wiring is arranged in the same layer, and the material of the common electrode is the metallized semiconductor material. 5 . The array substrate of claim 4 , wherein the distance between the common electrode and the touch trace is greater than or equal to 6 μm. 6 . 6 . The array substrate according to claim 5 , wherein the array substrate further comprises a low-impedance layer, the low-impedance layer is located in the pixel electrode region, and the low-impedance layer is the same as the source and drain. 7 . The dielectric layer is provided with a through hole, and the common electrode is connected to the low-resistance layer through the through hole. 7 . The array substrate according to claim 4 , wherein the array substrate further comprises a passivation layer and a pixel electrode, the passivation layer is provided on the active layer and covers the gate insulation. 8 . layer, gate and common electrode, the passivation layer is provided with a connection hole, and the pixel electrode is connected to the source and drain through the connection hole. 8. A preparation method of an array substrate, wherein the array substrate comprises a thin film transistor region and a pixel electrode region, the pixel electrode region is disposed on one side of the thin film transistor region, and the preparation method comprises: providing a substrate, and disposing a semiconductor material on the substrate to form a semiconductor layer; The semiconductor layer is patterned to form an active layer and touch traces, the active layer is located in the thin film transistor area, the touch traces are located in the pixel electrode area, and the active layer is located in the pixel electrode area. The layer and the touch wire are arranged in the same layer, the active layer is the semiconductor material, and the material of the touch wire is the metallized semiconductor material. 9. The preparation method according to claim 8, wherein the providing a substrate and forming a semiconductor layer on the substrate comprises the following steps: providing a substrate, and forming source and drain on the substrate; forming a dielectric layer on the source and drain electrodes, the dielectric layer covering the source and drain electrodes; A semiconductor layer is formed on the source and drain. 10. A display panel, characterized in that the display panel comprises a liquid crystal layer, a color filter substrate and the array substrate according to claims 1-7, the liquid crystal layer is disposed on the array substrate, and the color filter substrate is disposed on the array substrate. The film substrate is arranged on the liquid crystal layer; wherein, The color filter substrate includes a color resist layer, a black matrix and a substrate, the color resist layer and the black matrix are arranged in the same layer, the color resist layer is arranged opposite to the pixel electrode, and the substrate is arranged on the color resist layer. The barrier layer is on the side away from the liquid crystal layer.

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