CN113722255B - Signal quality processing method, device and system - Google Patents
Signal quality processing method, device and system Download PDFInfo
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- CN113722255B CN113722255B CN202111023117.8A CN202111023117A CN113722255B CN 113722255 B CN113722255 B CN 113722255B CN 202111023117 A CN202111023117 A CN 202111023117A CN 113722255 B CN113722255 B CN 113722255B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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Abstract
The invention provides a signal quality processing method, a device and a system, wherein the method comprises the following steps: monitoring the signal quality of PCIE signals between the processor and the interconnection external card; if the signal quality meets the first preset condition, the parameter value of the signal repeater is adjusted to enable the signal quality of the PCIE signal between the processor and the interconnection external card to meet the second preset condition, so that the problem that the server in the related art needs to rely on the parameters which are debugged in advance in the development stage to ensure the signal reliability when the server applies the Retimer/driver technology can be solved.
Description
Technical Field
The present invention relates to the field of image processing, and in particular, to a signal quality processing method, apparatus and system.
Background
The high-speed serial computer expansion bus standard (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, abbreviated as PCIE) bus is a common bus for server boards. With the development of PCIE standard, from PCIE1.0 to current PCIE5.0, the bus rate is faster and faster. Bus speeds are increasing and signal integrity is the greatest design challenge. For example, for a common FR4 board, the PCIE3.0 rate is 8Gbps, the wiring length is about 20 inches, the PCIE4.0 rate reaches 16Gbps, and the wiring length can only reach about 12 inches. The actual wiring link is far beyond 12 inches, so that the technology of the Retimer/Redriver is generated for relay compensation and recovery of signals. So that the high-speed signal integrity of the processor to the device end is ensured.
The Retimer/Redriver technique is used, which comprises the following two modes:
Mode one: and placing the R/R in a Riser card, and interconnecting the main board (PCIERoot Complex of the CPU) with terminal equipment (End Point) through the Riser card. Before the equipment leaves the factory, parameters of a repeater/driver are preset according to the types of the limited End Point equipment in advance, so that signals of the main board reaching the terminal equipment are optimal.
Mode two: and placing the Retimer/driver in a main board, and directly interconnecting the main board (PCIE Root Complex of a CPU) with terminal equipment (End Point) through a standard PCIE slot. Before the equipment leaves the factory, parameters of a repeater/driver are preset according to the types of the limited End Point equipment in advance, so that signals of the main board reaching the terminal equipment are optimal.
In the two modes, the End Point device is used as an external card for access, and cards with different forms can exist. The parameters of the re/driver are difficult to cover all differences. Even the risk of signal integrity is incurred when a server purchased by a customer needs to upgrade a terminal device card. In addition, the quality of the high-speed bus is not monitored in the operation of the server, and when the communication between the server and the external card is abnormal, the signal quality of the server is a black box for operation and maintenance personnel, and the operation and maintenance on site are difficult to carry out.
When the server applies the Retimer/driver technology, the server needs to rely on parameters which are debugged in advance in the development stage to ensure the reliability of signals. And the End Point device is accessed as an external card, and different forms exist. The parameters of the re/driver are difficult to cover all differences. Even the risk of signal integrity is incurred when the server needs to upgrade the terminal equipment card.
Aiming at the problem that the server in the related art needs to rely on parameters which are debugged in advance in the development stage to ensure the reliability of signals when the server applies the Retimer/Redriver technology, no solution is proposed yet.
Disclosure of Invention
The embodiment of the invention provides a signal quality processing method, a device and a system, which at least solve the problem that a server in the related art needs to rely on parameters which are debugged in advance in a development stage to ensure the reliability of signals when the server applies a repeater/driver technology.
According to an embodiment of the present invention, there is provided a signal quality processing method including:
Monitoring the signal quality of PCIE signals between the processor and the interconnection external card;
And if the signal quality meets the first preset condition, adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition.
Optionally, monitoring the signal quality of the PCIE signal between the processor and the interconnect-external card includes:
Monitoring signal error packet or eye pattern quality of a receiving end of the processor;
Monitoring the quality of a signal error packet or an eye pattern of a receiving end of the interconnection external card;
and determining the signal quality of the PCIE signal according to the signal error packet or the eye pattern quality.
Optionally, determining the signal quality of the PCIE signal according to the signal error packet or the eye diagram quality includes:
Judging whether the number of the signal error packets is larger than or equal to a preset number or whether the eye pattern quality is smaller than a preset threshold value;
if the judgment result is yes, determining that the signal quality meets the first preset condition;
And under the condition that the judgment result is negative, determining that the signal quality does not meet the first preset condition.
Optionally, adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnect add-on card meets a second preset condition includes:
Adjusting the parameter value of the signal repeater through a control bus, so that the signal quality of PCIE signals sent to the processor by the interconnection external card meets a second preset condition;
and adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the interconnection external card by the processor meets a second preset condition.
Optionally, after adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnect-external card meets a second preset condition, the method further includes:
And sending the monitored signal error packet or the eye diagram quality to a client, wherein the signal error packet or the eye diagram quality is used for indicating that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition under the condition that the client determines that the signal quality of the PCIE signal between the processor and the interconnection external card does not meet the second preset condition, and remotely adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition.
According to still another embodiment of the present invention, there is also provided a signal quality processing apparatus including:
the monitoring module is used for monitoring the signal quality of PCIE signals between the processor and the interconnection external card;
and the adjusting module is used for adjusting the parameter value of the signal repeater if the signal quality meets a first preset condition, so that the signal quality of the PCIE signal between the processor and the interconnection external card meets a second preset condition.
Optionally, the monitoring module includes:
the first monitoring submodule is used for monitoring the quality of signal error packets or eye patterns of the receiving end of the processor;
The second monitoring submodule is used for monitoring the quality of signal error packets or eye patterns of the receiving end of the interconnection external card;
And the determining submodule is used for determining the signal quality of the PCIE signal according to the signal error packet or the eye diagram quality.
Optionally, the determining submodule includes:
the judging unit is used for judging whether the number of the signal error packets is larger than or equal to a preset number or whether the eye diagram quality is smaller than a preset threshold value;
a first determining unit, configured to determine that the signal quality meets the first preset condition if the determination result is yes;
And the second determining unit is used for determining that the signal quality does not meet the first preset condition under the condition that the judging result is negative.
Optionally, the adjusting module includes:
the first adjusting sub-module is used for adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the processor by the interconnection external card meets a second preset condition;
And the second adjusting sub-module is used for adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the interconnection external card by the processor meets a second preset condition.
Optionally, the apparatus further comprises:
And the sending module is used for sending the monitored signal error packet or the eye diagram quality to a client, wherein the signal error packet or the eye diagram quality is used for indicating that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition under the condition that the client determines that the signal quality of the PCIE signal between the processor and the interconnection external card does not meet the second preset condition, and remotely adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition.
According to another embodiment of the present invention, there is also provided a signal quality processing system including: a server device, wherein the server device comprises: the baseboard management controller (Baseboard Management Controller, abbreviated as BMC), the processor, the signal repeater and the interconnection external card are respectively connected with the processor and the interconnection external card through a monitoring bus, the BMC is connected with the signal repeater through a control bus, the processor, the signal repeater and the interconnection external card are interconnected through a high-speed bus,
The BMC is used for monitoring the signal quality of PCIE signals between the processor and the interconnection external card; and if the signal quality meets a first preset condition, adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnection external card meets a second preset condition.
Optionally, the BMC is further configured to monitor a quality of a signal error packet or an eye pattern of the receiving end of the processor, monitor a quality of a signal error packet or an eye pattern of the receiving end of the interconnect add-on card, and determine a signal quality of the PCIE signal according to the signal error packet or the eye pattern quality.
Optionally, the BMC is further configured to determine whether the number of signal error packets is greater than or equal to a preset number, or whether the eye diagram quality is less than a preset threshold; if the judgment result is yes, determining that the signal quality meets the first preset condition; and under the condition that the judgment result is negative, determining that the signal quality does not meet the first preset condition.
Optionally, the BMC is further configured to adjust, through a control bus, a parameter value of the signal repeater, so that signal quality of a PCIE signal sent by the interconnect external card to the processor meets a second preset condition; and adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the interconnection external card by the processor meets a second preset condition.
Optionally, the system further comprises: the client is connected with the BMC through a monitoring bus, wherein,
The BMC is further configured to send the monitored signal error packet or the eye pattern quality to a client;
And the client is used for remotely adjusting the parameter value of the signal repeater under the condition that the signal quality of the PCIE signal between the processor and the interconnection external card does not meet the second preset condition according to the signal error packet or the eye pattern quality, so that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition.
According to a further embodiment of the invention, there is also provided a computer-readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.
According to a further embodiment of the invention, there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
By the invention, the signal quality of PCIE signals between the processor and the interconnection external card is monitored; if the signal quality meets the first preset condition, the parameter value of the signal repeater is adjusted to enable the signal quality of the PCIE signal between the processor and the interconnection external card to meet the second preset condition, the problem that the server in the related art needs to rely on the parameters which are debugged in advance in the development stage to ensure the signal reliability when the server applies the Retimer/driver technology can be solved, the quality of the PCIE high-speed signal is monitored in real time, and when abnormality is found, the parameter tuning of the signal repeater can be actively performed, so that the link achieves or recovers the optimal communication state.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
Fig. 1 is a block diagram of a hardware structure of a mobile terminal of a signal quality processing method according to an embodiment of the present invention;
Fig. 2 is a flow chart of a signal quality processing method according to an embodiment of the present invention;
fig. 3 is a schematic diagram of PCIE signal quality monitoring on a server according to the present embodiment;
fig. 4 is a schematic diagram of a server for PCIE signal quality monitoring according to the preferred embodiment;
FIG. 5 is a schematic diagram of EQ value settings according to an embodiment of the invention;
FIG. 6 is a schematic diagram of an eye diagram in accordance with an embodiment of the invention;
FIG. 7 is a schematic diagram II of an eye diagram according to an embodiment of the invention;
Fig. 8 is a block diagram of a signal quality processing apparatus according to an embodiment of the present invention.
Detailed Description
The application will be described in detail hereinafter with reference to the drawings in conjunction with embodiments. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
Example 1
The method according to the first embodiment of the present application may be implemented in a mobile terminal, a computer terminal or a similar computing device. Taking a mobile terminal as an example, fig. 1 is a block diagram of a hardware structure of the mobile terminal according to the signal quality processing method of the embodiment of the present application, as shown in fig. 1, the mobile terminal may include one or more (only one is shown in fig. 1) processors 102 (the processors 102 may include, but are not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, and optionally, the mobile terminal may further include a transmission device 106 for a communication function and an input/output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative and not limiting of the structure of the mobile terminal described above. For example, the mobile terminal may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1.
The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a signal quality processing method in an embodiment of the present invention, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and control of telnet, that is, implementing the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as a NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used to communicate with the internet wirelessly.
In this embodiment, a signal quality processing method operating on the mobile terminal or the network architecture is provided, and fig. 2 is a flowchart of a signal quality processing method according to an embodiment of the present invention, as shown in fig. 2, where the flowchart includes the following steps:
step S202, monitoring the signal quality of PCIE signals between a processor and an interconnection external card;
in step S2024, if the signal quality meets the first preset condition, the parameter value of the signal repeater is adjusted so that the signal quality of the PCIE signal between the processor and the interconnect card meets the second preset condition.
In this embodiment, the step S204 may specifically include: adjusting the parameter value of the signal repeater through a control bus, so that the signal quality of PCIE signals sent to the processor by the interconnection external card meets a second preset condition; and adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the interconnection external card by the processor meets a second preset condition.
Through the steps S202 to S204, the problem that the server in the related art needs to rely on parameters debugged in advance in the development stage to ensure the reliability of the signal when applying the repeater/driver technology can be solved, and when abnormality is found, the quality of the PCIE high-speed signal is monitored in real time, and parameter tuning can be actively performed on the signal repeater, so that the link reaches or recovers the optimal communication state.
In this embodiment, the step S202 may specifically include:
S2021, monitoring the quality of signal error packets or eye patterns of a receiving end of the processor;
s2022, monitoring the quality of signal error packets or eye patterns of the receiving end of the interconnection external card;
s2023, determining the signal quality of the PCIE signal according to the signal error packet or the eye diagram quality, and further judging whether the number of the signal error packets is greater than or equal to a preset number or whether the eye diagram quality is smaller than a preset threshold; if the judgment result is yes, determining that the signal quality meets the first preset condition; and under the condition that the judgment result is negative, determining that the signal quality does not meet the first preset condition.
In an optional embodiment, after the step S204, the monitored signal error packet or the eye diagram quality is sent to a client, where the signal error packet or the eye diagram quality is used to indicate that, when it is determined by the client that the signal quality of the PCIE signal between the processor and the interconnect-external card does not meet the second preset condition, the parameter value of the signal repeater is remotely adjusted, so that the signal quality of the PCIE signal between the processor and the interconnect-external card meets the second preset condition.
Example 2
According to another embodiment of the present invention, there is further provided a signal quality processing system, and fig. 3 is a schematic diagram for PCIE signal quality monitoring on a server according to the present embodiment, as shown in fig. 3, including: a server device 30, wherein the server device 30 comprises: the BMC302 is respectively connected with the processor 304 and the interconnection external card 308 through monitoring buses, the BMC302 is connected with the signal repeater 306 through control buses, the processor 304, the signal repeater 306 and the interconnection external card 308 are interconnected through high-speed buses,
The BMC302 is configured to monitor signal quality of PCIE signals between the processor 304 and the interconnect add-on card 308; if the signal quality meets the first preset condition, the parameter value of the signal repeater 306 is adjusted so that the signal quality of the PCIE signal between the processor 304 and the interconnect-external card meets the second preset condition.
Optionally, the BMC302 is further configured to monitor a quality of a signal error packet or an eye diagram of a receiving end of the processor 304, monitor a quality of a signal error packet or an eye diagram of a receiving end of the interconnect add-on card 308, and determine a signal quality of the PCIE signal according to the signal error packet or the eye diagram quality.
Optionally, the BMC302 is further configured to determine whether the number of signal error packets is greater than or equal to a preset number, or whether the eye quality is less than a preset threshold; if the judgment result is yes, determining that the signal quality meets the first preset condition; and under the condition that the judgment result is negative, determining that the signal quality does not meet the first preset condition.
Optionally, the BMC302 is further configured to adjust, through a control bus, a parameter value of the signal repeater 306, so that a signal quality of a PCIE signal sent by the interconnect-external card to the processor 304 meets a second preset condition; the parameter values of the signal repeater 306 are adjusted through the control bus, so that the signal quality of the PCIE signal sent by the processor 304 to the interconnect add-on card 308 meets a second preset condition.
Fig. 4 is a schematic diagram of a server for PCIE signal quality monitoring according to the preferred embodiment, as shown in fig. 4, the system further includes: a client 40, the client 40 being connected to the BMC302 via a monitoring bus, wherein,
The BMC302 is further configured to send the monitored signal error packet or the eye pattern quality to the client 40;
The client 40 is configured to, when determining that the signal quality of the PCIE signal between the processor 304 and the interconnect add-on card does not meet the second preset condition according to the signal error packet or the eye pattern quality, remotely adjust a parameter value of the signal repeater 306 so that the signal quality of the PCIE signal between the processor 304 and the interconnect add-on card meets the second preset condition.
For PCIE high-speed signal quality on the server, the signal quality of the processor 304 and the interconnection external card 308 is monitored in real time through the BMC302, including error packet statistics and eye pattern monitoring, and parameters of the repeater/driver are actively adjusted, so that a communication link between the processor 304 and the interconnection external card 308 is optimal. And meanwhile, error packet statistics and eye diagrams are reported to the client 40, so that the server operation and maintenance are facilitated. In the embodiment of the present invention, the processor 304, the signal repeater 306, the interconnection card 308, and the BMC302 are internal unit modules of the server device 30. The client 40 is interconnected to the server BMC302 via a network for remote monitoring and control of the server. The server and signal repeater 306 (re/r) are interconnected by a high-speed bus PCIE, and the re/r enhances or recovers the high-speed signals and then interconnects with the interconnect add-on card 308.
BMC302 is interconnected with processor 304 via a monitor bus for monitoring signal error packets and eye quality at the PCIE receive end (RX end) of the processor. When the signal error packet exceeds a preset early warning value or the quality of the eye diagram is detected to be poor, the BMC302 actively adjusts the parameter value of the signal repeater 306 (repeater/driver) through the control bus, so as to adjust the signal sent to the processor 304 by the interconnection external card to an optimal state, that is, the signal error packet is reduced to the early warning value or no signal error packet, or the quality of the eye diagram is adjusted to be optimal.
The BMC302 is interconnected with the interconnect add-on card 308 through a monitor bus, and is configured to monitor signal error packets and eye pattern quality of a PCIE receiving end (RX end) of the add-on card. When the signal error packet exceeds a preset early warning value or the quality of the eye diagram is detected to be poor, the BMC302 actively adjusts the parameter value of the signal repeater 306 (repeater/driver) through the control bus, so as to adjust the signal sent by the processor 304 to the external card to an optimal state, that is, the signal error packet is reduced to the early warning value or no signal error packet, or the quality of the eye diagram is adjusted to be optimal.
BMC302 may communicate the monitored signal error packets and eye diagrams of processor 304 and interconnect add-in card 308 to client 40. The computer lab fortune dimension personnel can monitor current communication signal reliability in real time, can observe the eye pattern quality simultaneously. The operator may also remotely adjust parameters of signal repeater 306 (repeater/driver) to optimize the operation of server apparatus 30.
The present embodiment will be described by way of example.
FIG. 5 is a schematic diagram of EQ value setting according to an embodiment of the present invention, as shown in FIG. 5, a manufacturer's Retimer, a first column (EQA 1/EQB 1) and a second column (EQA 0/EQB 0) are configurable parameter values, which can be dynamically set by BMC. The fifth, sixth and seventh columns are EQ values corresponding to different types of frequencies. The last column is the board type (FR 4), signal trace length and width (which can be considered as empirical values) suggested by the chip manufacturer, and it can be seen that these actual trace empirical values correspond to the settings of EQ.
Corresponding to the above, the interconnect card is different, and the corresponding signal trace length, width, and board type may be different, which may be considered as variables. The corresponding reasonable EQ settings are different for different interconnect add-in cards according to the following table. And this setting may be set by the BMC.
The BMC can set the EQ value, which BMC must not go according to what the EQ value is set to, directly by the last column of signal length, width and sheet type in the table above. In the present case, an indirect approach is provided. The signal quality of the processor and the receiving end of the interconnection external card is monitored in real time. High speed signal quality is typically measured in terms of an eye diagram index. The BMC can judge the quality of the signal by acquiring a signal eye diagram in the processor or the interconnection external card and quantitatively evaluating the eye diagram, so as to dynamically adjust the parameter value of the re-timer according to the quality of the signal. A good signal eye is never obtained.
Fig. 6 is a schematic diagram of an eye diagram of a BMC, as shown in fig. 6, when the BMC looks at an eye diagram of a received signal from the inside of a processor or an interconnect card, and in the eye diagram, the "eyes" are open, and all signal indexes meet the requirements. Fig. 7 is a schematic diagram of a second eye diagram according to an embodiment of the present invention, as shown in fig. 7, the "eyes" in the worse eye diagram are smaller, and the signal indexes are barely satisfactory. An example of dynamically adjusting parameters by the BMC in an actual certain project to further improve the quality of the eye pattern is as follows:
default parameters: eye quality is very poor;
Adjusting parameter 1: eye patterns have been formed, but the signal reflection is large, forming "multiple eyelid";
adjusting parameter 2: the eye quality is very good.
In the embodiment, the quality of the PCIE high-speed signal can be monitored in real time by the management unit BMC of the server, and error packets of the PCIE high-speed link are counted in real time. When abnormality is found, parameter tuning can be actively performed on the signal repeater, so that the link reaches or recovers the optimal communication state. The suitability of the server to the external interface card is further enhanced. The method solves the problem of suitability or consistency brought by different external cards to the server. Meanwhile, the BMC can report the monitoring results of the signal eye diagrams of the processor and the external card to the client, so that operation and maintenance personnel can conveniently operate and maintain the high-speed signal reliability of the server.
Example 3
According to still another embodiment of the present invention, there is also provided a signal quality processing apparatus, fig. 8 is a block diagram of the signal quality processing apparatus according to an embodiment of the present invention, as shown in fig. 8, including:
the monitoring module 82 is configured to monitor signal quality of PCIE signals between the processor and the interconnect-external card;
and the adjusting module 84 is configured to adjust the parameter value of the signal repeater if the signal quality meets a first preset condition, so that the signal quality of the PCIE signal between the processor and the interconnect card meets a second preset condition.
Optionally, the monitoring module 82 includes:
the first monitoring submodule is used for monitoring the quality of signal error packets or eye patterns of the receiving end of the processor;
The second monitoring submodule is used for monitoring the quality of signal error packets or eye patterns of the receiving end of the interconnection external card;
And the determining submodule is used for determining the signal quality of the PCIE signal according to the signal error packet or the eye diagram quality.
Optionally, the determining submodule includes:
the judging unit is used for judging whether the number of the signal error packets is larger than or equal to a preset number or whether the eye diagram quality is smaller than a preset threshold value;
a first determining unit, configured to determine that the signal quality meets the first preset condition if the determination result is yes;
And the second determining unit is used for determining that the signal quality does not meet the first preset condition under the condition that the judging result is negative.
Optionally, the adjustment module 84 includes:
the first adjusting sub-module is used for adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the processor by the interconnection external card meets a second preset condition;
And the second adjusting sub-module is used for adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the interconnection external card by the processor meets a second preset condition.
Optionally, the apparatus further comprises:
And the sending module is used for sending the monitored signal error packet or the eye diagram quality to a client, wherein the signal error packet or the eye diagram quality is used for indicating that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition under the condition that the client determines that the signal quality of the PCIE signal between the processor and the interconnection external card does not meet the second preset condition, and remotely adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition.
It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; or the above modules may be located in different processors in any combination.
Example 4
Embodiments of the present invention also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.
Alternatively, in the present embodiment, the above-described storage medium may be configured to store a computer program for performing the steps of:
s1, monitoring the signal quality of PCIE signals between a processor and an interconnection external card;
And S2, if the signal quality meets a first preset condition, adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnection external card meets a second preset condition.
Alternatively, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
Example 5
An embodiment of the invention also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Alternatively, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s1, monitoring the signal quality of PCIE signals between a processor and an interconnection external card;
And S2, if the signal quality meets a first preset condition, adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnection external card meets a second preset condition.
Alternatively, specific examples in this embodiment may refer to examples described in the foregoing embodiments and optional implementations, and this embodiment is not described herein.
It will be appreciated by those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may alternatively be implemented in program code executable by computing devices, so that they may be stored in a memory device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps within them may be fabricated into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A signal quality processing method, comprising:
Monitoring signal quality of a high-speed serial computer expansion bus standard PCIE signal between a processor and an interconnection external card;
If the signal quality meets a first preset condition, adjusting a parameter value of a signal repeater so that the signal quality of PCIE signals between the processor and the interconnection external card meets a second preset condition;
the adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnect add-on card meets a second preset condition includes:
Adjusting the parameter value of the signal repeater through a control bus, so that the signal quality of PCIE signals sent to the processor by the interconnection external card meets a second preset condition;
and adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the interconnection external card by the processor meets a second preset condition.
2. The method of claim 1, wherein monitoring the signal quality of PCIE signals between the processor and the interconnect add-on card comprises:
Monitoring signal error packet or eye pattern quality of a receiving end of the processor;
Monitoring the quality of a signal error packet or an eye pattern of a receiving end of the interconnection external card;
and determining the signal quality of the PCIE signal according to the signal error packet or the eye pattern quality.
3. The method of claim 2, wherein determining the signal quality of the PCIE signal based on the signal error packet or the eye diagram quality comprises:
Judging whether the number of the signal error packets is larger than or equal to a preset number or whether the eye pattern quality is smaller than a preset threshold value;
if the judgment result is yes, determining that the signal quality meets the first preset condition;
And under the condition that the judgment result is negative, determining that the signal quality does not meet the first preset condition.
4. A method according to any one of claims 1 to 3, wherein after adjusting the parameter values of the signal repeater such that the signal quality of the PCIE signal between the processor and the interconnect-external card meets a second preset condition, the method further comprises:
And sending the monitored signal error packet or the eye diagram quality to a client, wherein the signal error packet or the eye diagram quality is used for indicating that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition under the condition that the client determines that the signal quality of the PCIE signal between the processor and the interconnection external card does not meet the second preset condition, and remotely adjusting the parameter value of the signal repeater so that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition.
5. A signal quality processing apparatus, comprising:
the monitoring module is used for monitoring the signal quality of the high-speed serial computer expansion bus standard PCIE signal between the processor and the interconnection external card;
the adjusting module is used for adjusting the parameter value of the signal repeater if the signal quality meets a first preset condition, so that the signal quality of the PCIE signal between the processor and the interconnection external card meets a second preset condition;
wherein, the adjustment module includes:
the first adjusting sub-module is used for adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the processor by the interconnection external card meets a second preset condition;
And the second adjusting sub-module is used for adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the interconnection external card by the processor meets a second preset condition.
6. A signal quality processing system, comprising: a server device, wherein the server device comprises: the BMC is respectively connected with the processor and the interconnection external card through a monitoring bus, the BMC is connected with the signal relay through a control bus, the processor, the signal relay and the interconnection external card are interconnected through a high-speed bus,
The BMC is used for monitoring the signal quality of a high-speed serial computer expansion bus standard PCIE signal between the processor and the interconnection external card; if the signal quality meets a first preset condition, adjusting the parameter value of the signal repeater so that the signal quality of PCIE signals between the processor and the interconnection external card meets a second preset condition;
The BMC is further configured to adjust a parameter value of the signal repeater through a control bus, so that signal quality of a PCIE signal sent to the processor by the interconnection external card meets a second preset condition; and adjusting the parameter value of the signal repeater through the control bus so that the signal quality of the PCIE signal sent to the interconnection external card by the processor meets a second preset condition.
7. The system of claim 6, wherein the system further comprises a controller configured to control the controller,
And the BMC is also used for monitoring the quality of the signal error packet or the eye diagram of the receiving end of the processor, monitoring the quality of the signal error packet or the eye diagram of the receiving end of the interconnection external card, and determining the signal quality of the PCIE signal according to the signal error packet or the eye diagram quality.
8. The system of claim 7, wherein the system further comprises a controller configured to control the controller,
The BMC is further configured to determine whether the number of signal error packets is greater than or equal to a preset number, or whether the eye diagram quality is less than a preset threshold; if the judgment result is yes, determining that the signal quality meets the first preset condition; and under the condition that the judgment result is negative, determining that the signal quality does not meet the first preset condition.
9. The system according to any one of claims 6 to 8, further comprising: the client is connected with the BMC through a monitoring bus, wherein,
The BMC is further configured to send the monitored signal error packet or the eye pattern quality to the client;
And the client is used for remotely adjusting the parameter value of the signal repeater under the condition that the signal quality of the PCIE signal between the processor and the interconnection external card does not meet the second preset condition according to the signal error packet or the eye pattern quality, so that the signal quality of the PCIE signal between the processor and the interconnection external card meets the second preset condition.
10. A computer-readable storage medium, characterized in that the storage medium has stored therein a computer program, wherein the computer program is arranged to execute the method of any of the claims 1 to 4 when run.
11. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 1 to 4.
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107329774A (en) * | 2017-05-24 | 2017-11-07 | 华为技术有限公司 | The method and apparatus for determining Redriver chip parameters |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6901456B1 (en) * | 1999-06-18 | 2005-05-31 | Lsi Logic Corporation | Method and system for SCSI host bus interconnection |
| CN103152259B (en) * | 2013-02-20 | 2014-06-11 | 浪潮电子信息产业股份有限公司 | Design method of repeater chip |
| CN106155950B (en) * | 2015-03-23 | 2019-07-05 | 中兴通讯股份有限公司 | Parameter processing method and device |
| CN106021151A (en) * | 2016-05-09 | 2016-10-12 | 浪潮电子信息产业股份有限公司 | Signal enhancing board as well as signal enhancing method and system |
| CN106598903B (en) * | 2016-11-29 | 2020-01-14 | 浙江宇视科技有限公司 | Method and device for adjusting parameters of driver chip |
| JP6673270B2 (en) * | 2017-03-15 | 2020-03-25 | 日本電気株式会社 | Repeater device, repeater chip, card device, signal transmission device, repeater-related parameter setting method, and repeater-related parameter setting program |
| CN107357991A (en) * | 2017-07-12 | 2017-11-17 | 郑州云海信息技术有限公司 | A kind of redriver chip parameters configuration structure and method |
| CN107885923A (en) * | 2017-10-31 | 2018-04-06 | 郑州云海信息技术有限公司 | A kind of method for improving signal quality based on redriver parameter adaptives |
| CN109818886B (en) * | 2018-12-07 | 2020-12-08 | 华为技术有限公司 | A method and device for configuring equalization parameters |
| CN110377547B (en) * | 2019-06-28 | 2021-03-12 | 苏州浪潮智能科技有限公司 | Method and device for realizing driver parameter self-adaption in PCIE4.0 link |
| CN111159067B (en) * | 2019-12-26 | 2021-06-22 | 海光信息技术股份有限公司 | Parameter optimization method, device, module, processor and computer storage medium |
| CN112034947B (en) * | 2020-09-02 | 2022-07-08 | 苏州浪潮智能科技有限公司 | Backplane Design System and Parameter Tuning Method for Enhancing Server Hard Disk Compatibility |
| CN113206683A (en) * | 2021-04-27 | 2021-08-03 | 群联电子股份有限公司 | Circuit parameter adjusting system, method and host system |
-
2021
- 2021-09-01 CN CN202111023117.8A patent/CN113722255B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107329774A (en) * | 2017-05-24 | 2017-11-07 | 华为技术有限公司 | The method and apparatus for determining Redriver chip parameters |
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