CN113206683A - Circuit parameter adjusting system, method and host system - Google Patents
Circuit parameter adjusting system, method and host system Download PDFInfo
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- CN113206683A CN113206683A CN202110460460.2A CN202110460460A CN113206683A CN 113206683 A CN113206683 A CN 113206683A CN 202110460460 A CN202110460460 A CN 202110460460A CN 113206683 A CN113206683 A CN 113206683A
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- H04B3/36—Repeater circuits
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Abstract
The invention provides a circuit parameter adjusting system, a circuit parameter adjusting method and a host system. The circuit parameter adjustment system comprises a processing circuit, a relay circuit and a memory storage device. The processing circuit is configured to transmit an instruction to the memory storage device through the relay circuit to instruct the memory storage device to provide signal quality information. The processing circuit is also to receive the signal quality information from the memory storage and adjust a circuit parameter of the relay circuit according to the signal quality information. Therefore, the efficiency of adjusting the circuit parameters used for the relay circuit can be improved.
Description
Technical Field
The present invention relates to a circuit parameter adjusting technique, and more particularly, to a circuit parameter adjusting system, a method and a host system.
Background
A signal repeater (re-driver) is generally used to extend the transmission distance of the signal. However, under different usage environments and/or different configuration conditions, the circuit parameters preset by the signal repeater may cause poor modulation efficiency of the signal repeater on the signal.
Disclosure of Invention
The invention provides a circuit parameter adjusting system, a circuit parameter adjusting method and a host system, which can improve the adjusting efficiency of circuit parameters used by a relay circuit.
An exemplary embodiment of the present invention provides a circuit parameter adjustment system, which includes a processing circuit, a relay circuit and a memory storage device. The relay circuit is connected to the processing circuit. The memory storage device is connected to the relay circuit. The processing circuit is used for transmitting instructions to the memory storage device through the relay circuit. The instructions are to instruct the memory storage device to provide signal quality information. The processing circuit is also to receive the signal quality information from the memory storage. The processing circuit is further configured to adjust a circuit parameter of the relay circuit according to the signal quality information.
In an exemplary embodiment of the invention, the relay circuit is configured to modulate a signal transmitted between the processing circuit and the memory storage device to extend a transmission distance of the signal.
In an exemplary embodiment of the invention, the relay circuit includes a transmitting end circuit, and the adjusted circuit parameter is at least one setting parameter of the transmitting end circuit.
An exemplary embodiment of the present invention further provides a circuit parameter adjusting method, which includes: transmitting, by a relay circuit, an instruction to a memory storage device, wherein the instruction is to instruct the memory storage device to provide signal quality information; receiving the signal quality information from the memory storage; and adjusting a circuit parameter of the relay circuit according to the signal quality information.
In an exemplary embodiment of the invention, the circuit parameter adjusting method further includes: modulating, by the relay circuit, a signal passing between the processing circuit and the memory storage device to extend a transmission distance of the signal.
In an exemplary embodiment of the invention, the signal quality information reflects a signal quality of a test signal received by the memory storage device through the relay circuit.
In an exemplary embodiment of the present invention, the signal quality information reflects at least one of a signal recovery state, a signal eye width state, a signal eye height state, and a signal edge state of the test signal received by the memory storage device through the relay circuit.
In an exemplary embodiment of the invention, the adjusted circuit parameter is used to improve the operation performance of the relay circuit.
In an exemplary embodiment of the invention, the processing circuit and the relay circuit are disposed on the same motherboard.
In an exemplary embodiment of the invention, the relay circuit includes a transmitting-end circuit, and the step of adjusting the circuit parameter of the relay circuit according to the signal quality information includes: and adjusting at least one set parameter of the sending end circuit according to the signal quality information.
In an exemplary embodiment of the present invention, the memory storage device includes a receiving end circuit. The receiving-side circuit of the memory storage device is connected to the transmitting-side circuit of the relay circuit. At least one setting parameter of the receiving end circuit of the memory storage device is set by the memory storage device.
In an exemplary embodiment of the invention, the memory storage device is removably mounted on the main board.
In an exemplary embodiment of the invention, the memory storage device comprises an external storage device.
An exemplary embodiment of the present invention further provides a host system connected to the memory storage device through the relay circuit. The host system includes a processing circuit. The processing circuit is used for running a control program to: performing initialization setting on the relay circuit; executing a handshake procedure with the memory storage device through the initialized relay circuit; transmitting, by the relay circuitry, a developer instruction to the memory storage device to instruct the memory storage device to provide signal quality information; and adjusting a circuit parameter of the relay circuit according to the signal quality information.
In an exemplary embodiment of the present invention, the memory storage device includes a receiving end circuit connected to the relay circuit. In the handshake procedure, the memory storage device automatically adjusts at least one setting parameter of the receiving end circuit.
Based on the above, the processing circuit may transmit a specific instruction to the memory storage device through the relay circuit to instruct the memory storage device to provide the signal quality information. Processing circuitry may then receive the signal quality information from the memory storage and adjust circuit parameters of the relay circuitry in accordance with the signal quality information. Therefore, the efficiency of adjusting the circuit parameters used by the relay circuit can be improved.
Drawings
FIG. 1 is a schematic diagram of a circuit parameter adjustment system according to an exemplary embodiment of the present invention;
fig. 2-5 are schematic diagrams illustrating adjusting circuit parameters of a relay circuit according to an exemplary embodiment of the invention;
FIG. 6 is a schematic diagram of an eye diagram of a signal shown in accordance with an exemplary embodiment of the present invention;
FIG. 7 is a schematic diagram of a memory storage device according to an exemplary embodiment of the invention;
fig. 8 is a flowchart illustrating a circuit parameter adjustment method according to an exemplary embodiment of the invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1 is a schematic diagram of a circuit parameter adjustment system according to an exemplary embodiment of the invention. Referring to fig. 1, a system (also referred to as a circuit parameter adjusting system) 10 includes a processing circuit 11, a relay circuit (re-driving circuit)12, and a memory storage device 13. The processing circuit 11 may access the memory storage 13 through the relay circuit 12. For example, the processing circuit 11 may include a Central Processing Unit (CPU), or other Programmable general purpose or special purpose microprocessor, Digital Signal Processor (DSP), Programmable controller, Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), or other similar Device or combination of devices.
The relay circuit 12 is connected to the processing circuit 11 and the memory storage device 13. For example, the relay circuit 12 may be disposed on a signal transfer path between the processing circuit 11 and the memory storage device 13. The relay circuit 12 may be used to modulate signals passing between the processing circuit 11 and the memory storage device 13 to extend the transmission distance of the signals. For example, the relay circuit 12 may include a signal repeater (Re-driver).
The memory storage 13 is used to store data in a nonvolatile manner. For example, the memory storage device 13 may include an external storage device such as a usb disk, a memory card, a Solid State Drive (SSD), or a wireless memory storage device. Alternatively, the memory storage device 13 may include an embedded storage device such as an embedded multimedia Card (eMMC) or an embedded Multi-Chip Package (eMCP) storage device.
In an exemplary embodiment, the processing circuit 11 and the relay circuit 12 are disposed on the motherboard 14 and communicate with each other via the motherboard 14. In an exemplary embodiment, the processing circuit 11, the relay circuit 12 and the memory storage device 13 are all disposed on the motherboard 14 and communicate with each other through the motherboard 14.
In an exemplary embodiment, the memory storage device 13 may be embedded on the motherboard 14 by an embedded mounting method. In an exemplary embodiment, the memory storage device 13 may also be removably mounted on the motherboard 14 (i.e., electrically connected to the motherboard 14) via a Peripheral Component Interconnect (PCI Express) slot, a Serial Advanced Technology Attachment (SATA) slot, a Universal Serial Bus (USB) slot, or a similar Bus slot.
In an exemplary embodiment, the processing circuit 11 may transmit at least one instruction to the memory storage device 13 through the relay circuit 12. For example, the instructions may include predefined developer instructions or the like. The instructions may be used to instruct the memory storage 13 to provide signal quality information.
In an example embodiment, the signal quality information may be generated by the memory storage device 13. The signal quality information may reflect the signal quality of the test signal received by memory storage device 13 through relay circuit 12. The test signal may be generated by the processing circuit 11 and modulated by the relay circuit 12 before being transmitted to the transmission memory storage device 13. The memory storage 13 may generate the signal quality information from the received test signal.
In an example embodiment, in response to the instructions, memory storage 13 may provide the signal quality information to processing circuitry 11. Processing circuit 11 may then adjust circuit parameters of relay circuit 12 based on the signal quality information. The adjusted circuit parameters can be used to improve the operation performance of the relay circuit 12. For example, the adjusted circuit parameters may improve the signal quality of the signals transmitted between the processing circuit 11 and the memory storage device 13 through the relay circuit 12, thereby improving the performance of the relay circuit 12.
Fig. 2 to 5 are schematic diagrams illustrating adjusting circuit parameters of a relay circuit according to an exemplary embodiment of the invention. Referring to fig. 2, in an exemplary embodiment, the processing circuit 11 includes a control program 21, the relay circuit 12 includes a modulation circuit 22, and the memory storage device 13 includes a signal receiving circuit 23.
The processing circuit 11 may run the control program 21 to generate the test signal ts (i). i can be any positive integer. Test signal ts (i) may be transmitted to memory storage device 13 through relay circuit 12. The test signal ts (i) may be first transmitted to the relay circuit 12. When receiving the test signal ts (i), the modulation circuit 22 may automatically modulate the test signal ts (i) according to one or more circuit parameters. For example, the modulation may include changing various electrical characteristics of the test signal ts (i) such as voltage, waveform, or frequency. The test signal ts (i) modulated by the modulation circuit 22 can be transmitted to the memory storage device 13.
The signal receiving circuit 23 may receive the test signal ts (i) through the relay circuit 12. When receiving the test signal ts (i), the signal receiving circuit 23 may perform preprocessing such as signal restoration on the test signal ts (i) and analyze the test signal ts (i). The signal receiving circuit 23 may generate signal quality information (e.g., signal quality information sq (i) of fig. 4) related to the test signal ts (i) according to the analysis result of the test signal ts (i). The signal quality information associated with test signal ts (i) may reflect the signal quality of received test signal ts (i). The signal receiving circuit 23 may temporarily store the signal quality information in the memory storage device 13.
Referring to fig. 3, continuing with the example embodiment of fig. 2, after sending the test signal ts (i), the processing circuit 11 may run the control program 21 to generate the developer instruction vc (i). Developer instruction vc (i) corresponds to test signal ts (i). Processing circuitry 11 may communicate developer instructions vc (i) to memory storage 13 via relay circuitry 12. The developer instruction vc (i) may be used to instruct the memory storage device 13 to provide signal quality information related to the test signal ts (i).
Referring to fig. 4, following the example embodiment of fig. 3, after receiving the developer command vc (i), the memory storage device 13 may read the previously stored signal quality information sq (i) related to the test signal ts (i) in response to the developer command vc (i). Further, in response to the developer instruction vc (i), the memory storage 13 may transmit the signal quality information sq (i) to the processing circuit 11 through the relay circuit 12.
Referring to fig. 5, continuing with the example embodiment of fig. 4, after receiving the signal quality information sq (i), the processing circuit 11 may obtain the signal quality of the test signal ts (i) transmitted to the memory storage device 13 through the modulation circuit 22 according to the signal quality information sq (i). According to the signal quality information sq (i), the processing circuit 11 may operate the control program 21 to send a parameter adjustment instruction adj (i) to the relay circuit 12. The relay circuit 12 may adjust one or more circuit parameters of the modulation circuit 22 according to the parameter adjustment command adj (i).
In an exemplary embodiment, the processing circuit 11 may evaluate whether the current circuit parameters used by the modulation circuit 22 are appropriate (e.g., whether a relatively better signal transmission quality is achieved) according to the signal quality information sq (i). If not suitable (e.g., a relatively good signal transmission quality is not achieved), the processing circuit 11 may run the control program 21 to send the parameter adjustment command adj (i) to the relay circuit 12 to continuously adjust one or more circuit parameters of the modulation circuit 22. Otherwise, if appropriate (e.g., a relatively better signal transmission quality is achieved), the processing circuit 11 may not send the parameter adjustment command adj (i).
It should be noted that the operations mentioned in the exemplary embodiments of fig. 2 to 5 may be repeated multiple times to continuously adjust the circuit parameters used by the modulation circuit 22 according to the modulation result (or the signal quality information sq (i)) of the test signal ts (i) by the modulation circuit 22. For example, when i is equal to 1, the test signal TS (1) may be modulated by the modulation circuit 22 and transmitted to the memory storage device 13. Processing circuit 11 may then request signal quality information SQ (1) from memory storage 13 using developer instruction VC (1). Signal quality information SQ (1) may reflect the signal quality of test signal TS (1) received by memory storage device 13. According to the signal quality information SQ (1) provided by the memory storage device 13, the processing circuit 11 can adjust a specific circuit parameter of the modulation circuit 22 through the parameter adjustment instruction adj (i). Then, when i is 2, 3 or other values, the operations mentioned in the exemplary embodiments of fig. 2 to 5 may be repeated until the parameter adjustment operation of the modulation circuit 22 is completed.
In an example embodiment, the relay circuit 12 includes a receiving end circuit (also referred to as a first receiving end circuit) and a transmitting end circuit (also referred to as a first transmitting end circuit), and the memory storage device 13 also includes a receiving end circuit (also referred to as a second receiving end circuit) and a transmitting end circuit (also referred to as a second transmitting end circuit). The receiving end circuit (i.e., the first receiving end circuit) of the relay circuit 12 and the receiving end circuit (i.e., the second receiving end circuit) of the memory storage device 13 belong to the RX circuit and receive signals from the outside. A transmission-side circuit (i.e., a first transmission-side circuit) in the relay circuit 12 and a transmission-side circuit (i.e., a second transmission-side circuit) in the memory storage device 13 both belong to the TX circuit and transmit signals.
In an exemplary embodiment, a transmitting end circuit (i.e., a first transmitting end circuit) in the relay circuit 12 is connected to a receiving end circuit (i.e., a second receiving end circuit) in the memory storage device 13. In an exemplary embodiment, the sending end circuit (i.e., the first sending end circuit) of the relay circuit 12 may send the test signal ts (i) to the receiving end circuit (i.e., the second receiving end circuit) of the memory storage device 13. In an exemplary embodiment, the modulation circuit 22 may be disposed in the first transmitting end circuit. In an exemplary embodiment, the signal receiving circuit 23 may be disposed in the second receiving end circuit.
In an exemplary embodiment, during the transmission of the test signal ts (i), the relay circuit 12 may receive the test signal ts (i) from the processing circuit 11 through the first receiving end circuit and modulate the test signal ts (i) through the modulation circuit 22 in the first sending end circuit. The modulated test signal ts (i) may be transmitted to the memory storage device 13 through the first sending-end circuit. The memory storage device 13 may receive the test signal ts (i) through the signal receiving circuit 23 in the second receiving end circuit and generate the signal quality information sq (i) corresponding to the test signal ts (i). The signal quality information sq (i) may be transferred to the relay circuit 12 through the second sending-end circuit and transferred to the processing circuit 11 through the relay circuit 12. Then, the processing circuit 11 may send a parameter adjustment instruction adj (i) to the relay circuit 12 according to the signal quality information sq (i), so as to adjust at least one setting parameter of the first sending end circuit through the parameter adjustment instruction adj (i). For example, the setting parameters adjusted in the relay circuit 12 may include setting parameters of a signal amplifier in the first transmitter circuit (or the modulation circuit 22) and other parameters that can change various electrical characteristics such as voltage, waveform, or frequency of the signal output by the first transmitter circuit. In addition, at least one setting parameter of the transmitting-side circuit (i.e., the second transmitting-side circuit) and/or the receiving-side circuit (i.e., the second receiving-side circuit) in the memory storage device 13 is set and/or adjusted by the memory storage device 13 itself. For example, the setting parameters adjusted in the memory storage device 13 may include setting parameters of an equalizer circuit in the second receiving circuit (or the signal receiving circuit 23).
In an exemplary embodiment, after electrically connecting the relay circuit 12 and the memory storage device 13 to the motherboard 14, the processing circuit 11 may run the control program 21 to perform an initialization setting on the relay circuit 12. For example, in this initialization setting, the control program 21 may instruct the relay circuit 12 to perform an initialization configuration to set at least some parameters of the relay circuit 12 to initial values. After the initialization setting is completed, the processing circuit 11 may run the control program 21 to execute a handshake procedure (also referred to as a handshake operation) with the memory storage device 13 through the initialized relay circuit 12. In this handshake procedure, the processing circuit 11 may exchange information, e.g. electrical information related to voltage and/or frequency, with the memory storage 13 via the relay circuit 12. In addition, in the handshake procedure, the memory storage device 13 may automatically adjust at least one setting parameter of a receiving end circuit (i.e., a second receiving end circuit) (e.g., the signal receiving circuit 23) in the memory storage device 13 according to the information from the relay circuit 12. After completing the handshake procedure, the processing circuit 11 may execute the control program 21 to perform at least some of the operations mentioned in the example embodiments of fig. 2 to 5. In addition, in an example embodiment, at least some of the operations mentioned in the example embodiment of fig. 2 (e.g., transmitting the test signal ts (i) and analyzing the signal quality of the test signal ts (i)) may also be performed in the handshake procedure.
In an exemplary embodiment, the signal receiving circuit 23 may evaluate the signal recovery state, the signal eye width state, the signal eye height state and/or the signal edge state of the test signal ts (i) according to the received test signal ts (i). For example, the signal receiving circuit 23 may include various detection circuits such as an eye width detector and/or an eye height detector for evaluating signal quality. Then, the signal receiving circuit 23 may store signal quality information sq (i) about the test signal ts (i) according to the evaluation result. Thus, the stored signal quality information sq (i) may reflect at least one of a signal recovery state, a signal eye width state, a signal eye height state, and a signal edge state of the received test signal ts (i).
Fig. 6 is a schematic diagram of an eye diagram of a signal according to an exemplary embodiment of the invention. Referring to fig. 6, continuing with the example embodiment of fig. 2, in an example embodiment, the signal receiving circuit 23 may depict an eye diagram 61 of the received test signal ts (i). At least part of the information in the eye diagram 61 may reflect the signal quality of the received test signal ts (i).
In an exemplary embodiment, the signal receiving circuit 23 may generate the signal quality information sq (i) according to the parameters D (1) -D (5) in the eye diagram 61 or other useful information. For example, the parameter D (1) may reflect the signal eye width status of the received test signal ts (i). For example, parameter D (2) may reflect the eye high state of the received test signal ts (i). For example, the parameters D (3) to D (5) may reflect the signal edge status of the received test signal ts (i). In addition, in an exemplary embodiment, the signal receiving circuit 23 may also evaluate the signal recovery status of the received test signal ts (i) according to the number of times of signal recovery or signal reconstruction performed on the received test signal ts (i).
FIG. 7 is a diagram illustrating a memory storage device according to an exemplary embodiment of the invention. Referring to fig. 7, the memory storage device 13 includes a connection interface unit 701, a memory control circuit unit 702, and a rewritable nonvolatile memory module 703.
The connection interface unit 701 is used to connect the memory storage device 13 to the processing circuit 11, the relay circuit 12, and/or the main board 14 of fig. 1. The memory storage device 13 may communicate with the processing circuit 11, the relay circuit 12, and/or the main board 14 through the connection interface unit 701. For example, the connection interface unit 701 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, PCI Express standard, USB standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated drive Electronics Interface (IDE) standard, or other suitable standard. The connection interface unit 701 may be packaged with the memory control circuit unit 702 in one chip, or the connection interface unit 701 may be disposed outside a chip including the memory control circuit unit 702.
The memory control circuit unit 702 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 703 according to commands of a host system.
The rewritable nonvolatile memory module 703 is connected to the memory control circuit unit 702 and is used for storing data written by the processing circuit 11. For example, the rewritable nonvolatile memory module 703 may be a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two-Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
In an example embodiment, the memory control circuit unit 702 is also referred to as a flash memory controller. In an example embodiment, the rewritable nonvolatile memory module 703 is also called a flash memory module. In an exemplary embodiment, at least a portion of the electronic circuits (including the processing circuit 11) on the motherboard 14 of fig. 1 may also be referred to as a host system.
Fig. 8 is a flowchart illustrating a circuit parameter adjustment method according to an exemplary embodiment of the invention. Referring to fig. 8, in step S801, at least one instruction is transmitted to a memory storage device through a relay circuit, wherein the instruction is used to instruct the memory storage device to provide signal quality information. In step S802, the signal quality information is received from the memory storage. In step S803, one or more circuit parameters of the relay circuit are adjusted according to the signal quality information.
However, the steps in fig. 8 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 8 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 8 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In summary, in a use scenario where a processing circuit (e.g., a CPU) is connected to a memory storage device through a relay circuit, the processing circuit may use specific instructions (e.g., developer instructions) to read signal quality information from the memory storage device. The processing circuit may then evaluate, based on the signal quality information, whether the circuit parameters currently used by the relay circuit need to be updated and may dynamically adjust the circuit parameters. In an exemplary embodiment, no external testing instrument is required to test the signal output by the relay circuit. By cooperation between the processing circuit and the memory storage device, the circuit parameters used by the relay circuit can be appropriately adjusted, thereby improving the efficiency of adjustment of the circuit parameters used by the relay circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (22)
1. A circuit parameter adjustment system, comprising:
a processing circuit;
a relay circuit connected to the processing circuit; and
a memory storage device connected to the relay circuit,
wherein the processing circuitry is to transmit instructions to the memory storage device through the relay circuitry, the instructions to instruct the memory storage device to provide signal quality information,
the processing circuit is further to receive the signal quality information from the memory storage, and
the processing circuit is further configured to adjust a circuit parameter of the relay circuit according to the signal quality information.
2. The circuit parameter adjustment system of claim 1, wherein the relay circuit is configured to modulate a signal passing between the processing circuit and the memory storage device to extend a transmission distance of the signal.
3. The circuit parameter adjustment system of claim 1, wherein the signal quality information reflects a signal quality of a test signal received by the memory storage device through the relay circuit.
4. The circuit parameter adjustment system of claim 3, wherein the signal quality information reflects at least one of a signal recovery state, a signal eye width state, a signal eye height state, and a signal edge state of the test signal received by the memory storage device through the relay circuit.
5. The circuit parameter adjustment system of claim 1, wherein the adjusted circuit parameter is used to improve the performance of the relay circuit.
6. The circuit parameter adjustment system of claim 1, wherein the processing circuit and the relay circuit are disposed on a same motherboard.
7. The circuit parameter adjustment system of claim 1, wherein the relay circuit comprises a transmitting end circuit, and the adjusted circuit parameter is at least one setting parameter of the transmitting end circuit.
8. The circuit parameter adjustment system according to claim 7, wherein the memory storage device includes a receiving-side circuit, the receiving-side circuit of the memory storage device is connected to the transmitting-side circuit of the relay circuit, and at least one setting parameter of the receiving-side circuit of the memory storage device is set by the memory storage device.
9. The circuit parameter adjustment system of claim 6, wherein the memory storage device is pluggable mounted on the motherboard.
10. The circuit parameter adjustment system of claim 1, wherein the memory storage device comprises an external storage device.
11. A method for adjusting circuit parameters, comprising:
transmitting, by a relay circuit, an instruction to a memory storage device, wherein the instruction is to instruct the memory storage device to provide signal quality information;
receiving the signal quality information from the memory storage; and
and adjusting the circuit parameters of the relay circuit according to the signal quality information.
12. The circuit parameter adjustment method of claim 11, further comprising:
modulating, by the relay circuit, a signal passing between the processing circuit and the memory storage device to extend a transmission distance of the signal.
13. The circuit parameter adjustment method of claim 11, wherein the signal quality information reflects a signal quality of a test signal received by the memory storage device through the relay circuit.
14. The circuit parameter adjustment method of claim 13, wherein the signal quality information reflects at least one of a signal recovery state, a signal eye width state, a signal eye height state, and a signal edge state of the test signal received by the memory storage device through the relay circuit.
15. The method as claimed in claim 11, wherein the adjusted circuit parameter is used to improve the performance of the relay circuit.
16. The circuit parameter adjustment method according to claim 12, wherein the processing circuit and the relay circuit are disposed on the same motherboard.
17. The circuit parameter adjustment method according to claim 11, wherein the relay circuit includes a transmitting-end circuit, and the step of adjusting the circuit parameter of the relay circuit according to the signal quality information includes:
and adjusting at least one set parameter of the sending end circuit according to the signal quality information.
18. The circuit parameter adjustment method according to claim 17, wherein the memory storage device includes a receiving end circuit, the receiving end circuit of the memory storage device is connected to the transmitting end circuit of the relay circuit, and at least one setting parameter of the receiving end circuit of the memory storage device is set by the memory storage device.
19. The circuit parameter adjustment method of claim 16, wherein the memory storage device is pluggable onto the motherboard.
20. The circuit parameter adjustment method of claim 11, wherein the memory storage device comprises an external storage device.
21. A host system connected to a memory storage device through a relay circuit, wherein the host system comprises:
a processing circuit to run a control program to:
performing initialization setting on the relay circuit;
executing a handshake procedure with the memory storage device through the initialized relay circuit; transmitting, by the relay circuitry, a developer instruction to the memory storage device to instruct the memory storage device to provide signal quality information; and
and adjusting the circuit parameters of the relay circuit according to the signal quality information.
22. The host system of claim 21, wherein the memory storage device comprises a receive side circuit coupled to the relay circuit, and
in the handshake procedure, the memory storage device automatically adjusts at least one setting parameter of the receiving end circuit.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113722255A (en) * | 2021-09-01 | 2021-11-30 | 浙江大华技术股份有限公司 | Signal quality processing method, device and system |
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| CN102930901A (en) * | 2011-08-08 | 2013-02-13 | 安凯(广州)微电子技术有限公司 | Controller used for memory and method for using controller |
| CN106527977A (en) * | 2016-10-17 | 2017-03-22 | 锐捷网络股份有限公司 | A parameter configuring method and a storage apparatus |
| CN110299914A (en) * | 2018-03-21 | 2019-10-01 | 群联电子股份有限公司 | Phase-locked loop circuit bearing calibration, memorizer memory devices and connecting interface circuit |
| CN112397119A (en) * | 2019-08-14 | 2021-02-23 | 美光科技公司 | Apparatus and method for setting operating parameters of memory based on location |
| CN112069023A (en) * | 2020-08-23 | 2020-12-11 | 苏州浪潮智能科技有限公司 | A storage link monitoring system and method |
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| CN113722255A (en) * | 2021-09-01 | 2021-11-30 | 浙江大华技术股份有限公司 | Signal quality processing method, device and system |
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