CN113612449A - An operational amplifier circuit - Google Patents
An operational amplifier circuit Download PDFInfo
- Publication number
- CN113612449A CN113612449A CN202111004370.9A CN202111004370A CN113612449A CN 113612449 A CN113612449 A CN 113612449A CN 202111004370 A CN202111004370 A CN 202111004370A CN 113612449 A CN113612449 A CN 113612449A
- Authority
- CN
- China
- Prior art keywords
- circuit
- tube
- nmos
- switchable
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 claims abstract description 39
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 39
- 238000003491 array Methods 0.000 claims description 36
- 238000005070 sampling Methods 0.000 claims description 24
- 239000003990 capacitor Substances 0.000 claims description 19
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000000087 stabilizing effect Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000009897 systematic effect Effects 0.000 description 2
- RWPYOAUYOSFJQV-UHFFFAOYSA-N (1-methylpiperidin-4-yl) acetate Chemical compound CN1CCC(OC(C)=O)CC1 RWPYOAUYOSFJQV-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
- H03F1/48—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
- H03F1/483—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers with field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45012—Indexing scheme relating to differential amplifiers the addition of two signals being made in a switched capacitor circuit for producing the common mode signal
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
本发明公开了一种运算放大器电路，包括两个差分信号输入端、两个差分信号输出端、偏置电路、全差分运算放大器主电路和共模反馈电路，全差分运算放大器主电路包括作为第一级的第一差分放大电路和作为第二级的前向放大补偿与推挽驱动电路，前向放大补偿与推挽驱动电路包括两组参与前向放大补偿和推挽驱动的可切换开关管阵列。本发明的运算放大器电路可以实现较大的带宽，且功耗较低。
The invention discloses an operational amplifier circuit, comprising two differential signal input ends, two differential signal output ends, a bias circuit, a main circuit of a fully differential operational amplifier and a common mode feedback circuit. The first differential amplifier circuit of the first stage and the forward amplification compensation and push-pull driving circuit as the second stage, the forward amplification compensation and push-pull driving circuit includes two groups of switchable switches involved in the forward amplification compensation and push-pull driving. array. The operational amplifier circuit of the present invention can achieve larger bandwidth and lower power consumption.
Description
[ technical field ]
The present invention relates to integrated circuits, and more particularly, to an operational amplifier circuit.
[ background art ]
The operational amplifier is an electronic integrated circuit containing a multistage amplifying circuit, and the invention with the application number of CN201310123747.1 discloses an operational amplifier circuit with adjustable bandwidth, which comprises a bias circuit, a fully differential operational amplifier main circuit and a common mode feedback circuit, wherein: the bias circuit is used for providing stable bias current irrelevant to temperature and process for the main circuit of the fully differential operational amplifier and the common-mode feedback circuit; the fully differential operational amplifier main circuit is a two-stage amplified full-swing output structure and is used for providing gain and required bandwidth under the action of bias current and outputting a common-mode level to a common-mode feedback circuit; and the common-mode feedback circuit is used for stabilizing the common-mode level output by the main circuit of the fully differential operational amplifier to a constant voltage. The operational amplifier circuit with the adjustable bandwidth is required to obtain larger bandwidth. It is necessary to trade by increasing power consumption.
[ summary of the invention ]
The invention aims to provide an operational amplifier circuit with larger bandwidth and lower power consumption.
In order to solve the technical problems, the technical scheme adopted by the invention is that the operational amplifier circuit comprises two differential signal input ends, two differential signal output ends, a bias circuit, a fully differential operational amplifier main circuit and a common mode feedback circuit, wherein the fully differential operational amplifier main circuit comprises a first differential amplification circuit serving as a first stage and a forward amplification compensation and push-pull driving circuit serving as a second stage, and the forward amplification compensation and push-pull driving circuit comprises two groups of switchable switching tube arrays participating in forward amplification compensation and push-pull driving.
In the operational amplifier circuit, the first differential amplification circuit comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the forward amplification compensation and push-pull driving circuit comprises a fifth PMOS transistor, a sixth PMOS transistor and the two switchable switch transistor arrays; the drain electrode of the first NMOS tube is connected with the positive electrode of the power supply through a third PMOS tube, and the drain electrode of the second NMOS tube is connected with the positive electrode of the power supply through a fourth PMOS tube; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and then connected with the biasing circuit, the grid electrode of the first NMOS tube is connected with the first differential signal input end, and the grid electrode of the second NMOS tube is connected with the second differential signal input end; each group of switchable switch tube arrays comprises a plurality of switchable NMOS tubes connected in parallel, the grid electrode of the fifth PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the sixth PMOS tube is connected with the drain electrode of the second NMOS tube; and the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with the positive electrode of the power supply, and the drain electrode of the fifth PMOS tube is connected with the first differential signal output end. The NMOS tubes of the first group of switchable switching tube arrays are grounded; the drain electrode of the sixth PMOS tube is connected with the second differential signal output end and is grounded through the NMOS tube of the second group of switchable switching tube arrays; the grid electrodes of the NMOS tubes connected in parallel with the first group of switchable switch tube arrays are connected with the grid electrode of the second NMOS tube through a first alternating current coupling capacitor, and the grid electrodes of the NMOS tubes connected in parallel with the second group of switchable switch tube arrays are connected with the grid electrode of the first NMOS tube through a second alternating current coupling capacitor.
In the operational amplifier circuit, the common mode feedback circuit includes the second differential amplifying circuit and the common mode sampling circuit; the second differential amplification circuit comprises a fifth NMOS tube, a sixth NMOS tube, two groups of switchable parallel PMOS tubes and a common mode sampling circuit, wherein the drain electrode of the fifth NMOS tube is connected with the anode of the power supply through the first group of switchable parallel PMOS tubes, and the drain electrode of the sixth NMOS tube is connected with the anode of the power supply through the second group of switchable parallel PMOS tubes; the source electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube and then connected with the bias circuit, the grid electrode of the fifth NMOS tube is connected with the output end of the common mode sampling circuit, and the grid electrode of the sixth NMOS tube is connected with the reference voltage signal input end; the common mode sampling circuit comprises two sampling resistors which are connected in series, and the connection point of the two sampling resistors is the output end of the common mode sampling circuit; two ends of the common mode sampling circuit are respectively connected with the first differential signal output end and the second differential signal output end.
In the operational amplifier circuit, the common mode feedback circuit includes a common mode feedback compensation circuit, and the common mode feedback compensation circuit includes a first RC delay compensation circuit and a second RC delay compensation circuit; the source electrode of the first group of the switchable parallel PMOS tubes and the source electrode of the second group of the switchable parallel PMOS tubes are connected with the positive electrode of the power supply, the drain electrode and the grid electrode of the first group of the switchable parallel PMOS tubes are connected with the drain electrode of the fifth NMOS tube, and the drain electrode and the grid electrode of the second group of the switchable parallel PMOS tubes are connected with the drain electrode of the sixth NMOS tube; the grid electrodes of the first group of switchable parallel PMOS tubes are connected with the positive electrode of the power supply through a second RC lag compensation circuit and are connected with the grid electrode of a third PMOS tube and the grid electrode of a fourth PMOS tube; the grid electrode of the fifth NMOS tube is grounded through the first RC hysteresis compensation circuit.
In the operational amplifier circuit, the forward amplification compensation and push-pull driving circuit comprises two miller compensation capacitors, the first miller compensation capacitor is connected between the gate and the drain of the fifth PMOS transistor, and the second miller compensation capacitor is connected between the gate and the drain of the sixth PMOS transistor.
In the operational amplifier circuit, the bias circuit comprises a reference current source, a first NMOS transistor of the bias circuit, a second NMOS transistor of the bias circuit, and a switchable switch transistor array of the bias circuit, wherein the switchable switch transistor array of the bias circuit comprises a plurality of switchable parallel-connected NMOS transistors; the input end of the reference current source is connected with the positive electrode of the power supply, the output end of the reference current source is connected with the drain electrode of the first NMOS tube of the bias circuit, the drain electrode of the first NMOS tube of the bias circuit is connected with the grid electrode, and the source electrode of the first NMOS tube of the bias circuit is grounded; the grid electrode of the second NMOS tube of the bias circuit is connected with the grid electrode of the first NMOS tube of the bias circuit, the source electrode of the second NMOS tube of the bias circuit is grounded, and the drain electrode of the second NMOS tube of the bias circuit is connected with the source electrode of the first NMOS tube of the first differential amplification circuit and the source electrode of the second NMOS tube; the grid electrode of the NMOS tube of the switchable switch tube array of the bias circuit is connected with the grid electrode of the first NMOS tube of the bias circuit, the source electrode of the NMOS tube of the switchable switch tube array of the bias circuit is grounded, and the drain electrode of the switchable switch tube array of the bias circuit is connected with the source electrode of the fifth NMOS tube of the second differential amplification circuit and the source electrode of the sixth NMOS tube.
In the operational amplifier circuit, the grid electrodes of the NMOS tubes connected in parallel with the first group of switchable switching tube arrays are connected with the grid electrode of the first NMOS tube of the biasing circuit through the first biasing resistor, and the grid electrodes of the NMOS tubes connected in parallel with the second group of switchable switching tube arrays are connected with the grid electrode of the first NMOS tube of the biasing circuit through the second biasing resistor; the drain electrodes of the NMOS tubes connected in parallel with the first group of switchable switching tube arrays are connected with the drain electrode of the fifth PMOS tube, and the source electrodes of the NMOS tubes connected in parallel with the first group of switchable switching tube arrays are grounded; the drain electrodes of the NMOS tubes connected in parallel in the second group of switchable switch tube arrays are connected with the drain electrode of the sixth PMOS tube, and the source electrodes of the NMOS tubes connected in parallel in the second group of switchable switch tube arrays are grounded.
The operational amplifier circuit adjusts the number of the NMOS tubes which are connected in parallel in the two groups of switchable switch tube arrays of the forward amplification compensation and push-pull driving circuit according to the requirements of bandwidth and current consumption.
The operational amplifier circuit adjusts the number of the PMOS tubes connected in parallel in two groups of switchable parallel PMOS tubes and/or the number of the NMOS tubes connected in parallel in the switchable switch tube array of the bias circuit according to the requirements of bandwidth and power consumption of the common mode feedback loop.
The operational amplifier circuit of the invention can realize larger bandwidth and lower power consumption,
[ description of the drawings ]
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic block diagram of an operational amplifier circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of an operational amplifier circuit according to an embodiment of the present invention.
FIG. 3 is a diagram of an NMOS switch array according to an embodiment of the invention.
FIG. 4 is a schematic diagram of a PMOS switch array according to an embodiment of the invention.
[ detailed description of the invention ]
The structure and principle of the operational amplifier circuit of the embodiment of the invention are shown in fig. 1 to 4, and the operational amplifier circuit comprises a power supply positive electrode input end VDD and a differential signal input end VIP、VINTwo differential signal output ends V0P、V0NThe circuit comprises a bias circuit, a fully differential operational amplifier main circuit and a common mode feedback circuit.
The bias circuit is used for providing stable bias current independent of temperature and process for the main circuit of the fully differential operational amplifier and the common-mode feedback circuit. The main circuit of the fully differential operational amplifier adopts a two-stage amplified full-swing output structure, is used for providing gain and required bandwidth under the action of bias current, and outputs a common mode level to a common mode feedback circuit. The common-mode feedback circuit is used for stabilizing the common-mode level output by the main circuit of the fully differential operational amplifier to a constant voltage.
As shown in fig. 1, the fully differential operational amplifier main circuit includes a first differential amplification circuit as a first stage and a forward amplification compensation and push-pull drive circuit as a second stage.
As shown in fig. 2, the first differential amplifier circuit includes a first NMOS transistor MN1A second NMOS transistor MN2And the third PMOS transistor MP3And the fourth PMOS transistor MP4The forward amplification compensation and push-pull driving circuit comprises a fifth PMOS tube MP5Sixth PMOS pipe MP6The device comprises two groups of switchable switch tube arrays and two Miller compensation capacitors. First NMOS transistor MN1The drain electrode of the transistor passes through a third PMOS tube MP3The drain electrode of the second NMOS transistor MN2 is connected with the positive electrode VDD of the power supply through a fourth PMOS transistor MP 4. First NMOS transistor MN1Source electrode of and the second NMOS transistor MN2The source electrode of the NMOS transistor is connected with a back bias circuit, and a first NMOS transistor MN1The grid of the first differential signal input end V is connected with the first differential signal input end VIPSecond NMOS transistor MN2The grid of the first differential signal input terminal is connected with the second differential signal input terminal VIN. Each group of switchable switch tube array MN3And MN4Each comprising a plurality of switchable, parallel-connected NMOS transistors.
Fifth PMOS transistor MP5The grid electrode of the NMOS transistor is connected with the first NMOS transistor MN1The sixth PMOS transistor MP6Grid of the NMOS transistor is connected with a second NMOS transistor MN2Of the substrate. Fifth PMOS transistor MP5Source electrode and sixth PMOS transistor MP6The source electrodes of the first and second electrode are respectively connected with a power supply anode VDD and a first Miller compensation capacitor CM1Is connected to a fifth PMOS transistor MP5Between the gate and the drain of the first transistor, a second Miller compensation capacitor CM2Is connected to a sixth PMOS tube MP6Between the gate and the drain. Fifth PMOS transistor MP5Drain electrode of the first differential signal output end V is connected with the first differential signal output end VOP. And through the first group of switchable switching tube arrays MN3The NMOS tube of (1) is grounded. Sixth PMOS transistor MP6Drain electrode of the first differential signal output terminal is connected with the second differential signal output terminal VONAnd through a second group of switchable switching tube arrays MN4The NMOS tube of (1) is grounded. I.e. a first set of switchable switching tube arrays MN3The drain electrode of the NMOS tube connected in parallel is connected with the fifth PMOS tube MP5The first group of switchable switching tube arrays MN3The source electrode of the NMOS tube connected in parallel is grounded. Second group of switchable switch tube array MN4The drain electrode of the NMOS tube connected in parallel is connected with a sixth PMOS tube MP6A second group of switchable switching tube arrays MN4The source electrode of the NMOS tube connected in parallel is grounded. First group of switchable switch tube array MN3The grid of the NMOS tubes connected in parallel passes through a first alternating current coupling capacitor CF1Is connected with a second NMOS tube MN2A second group of switchable switching tube arrays MN4Of parallel-connected NMOS tubesThe grid electrode passes through a second alternating current coupling capacitor CF2Is connected with a first NMOS tube MN1A gate electrode of (1).
The common-mode feedback circuit comprises a second differential amplifying circuit and a common-mode sampling circuit. The second differential amplifying circuit comprises a fifth NMOS tube MN5And a sixth NMOS transistor MN6Two groups of switchable parallel PMOS (P-channel metal oxide semiconductor) tubes MP1、MP2And a common mode sampling circuit, a fifth NMOS transistor MN5The drain electrode of the PMOS transistor is connected with a first group of switchable parallel PMOS tubes MP1The drain electrode of the sixth NMOS transistor MN6 is connected with the anode VDD of the power supply through a second group of switchable parallel PMOS transistors MP2Connected with the positive electrode VDD of the power supply. The source of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6The source electrode of the NMOS transistor is connected with a back-end bias circuit, and a fifth NMOS transistor MN5The grid of the NMOS transistor is connected with the output end of the common-mode sampling circuit, and a sixth NMOS transistor MN6Is connected with a reference voltage signal VREFTo the input terminal of (1).
The common mode sampling circuit comprises two sampling resistors R connected in seriesS1And RS2Two sampling resistors RS1And RS2The connection point of the common mode sampling circuit and the fifth NMOS tube MN5Is connected to the gate of (a). Two ends of the common mode sampling circuit are respectively connected with a first differential signal output end VOPAnd a second differential signal output terminal VON。
The common mode feedback circuit also comprises a common mode feedback compensation circuit which comprises a resistor RC1And a capacitor CC1A first RC hysteresis compensation circuit composed of series connection and a resistor RC2And a capacitor CC2A second RC lag compensation circuit formed in series. First group of switchable parallel PMOS (P-channel Metal oxide semiconductor) tubes MP1And a second group of switchable parallel PMOS transistors MP2The source electrodes of the PMOS transistors are respectively connected with the positive electrode VDD of the power supply, and the first group of switchable parallel PMOS tubes MP1The drain electrode and the grid electrode of the transistor are connected and then connected with a fifth NMOS transistor MN5A second group of switchable parallel PMOS transistors MP2The drain electrode and the grid electrode are connected and then connected with a sixth NMOS tube MN6Of the substrate. First group of switchable parallel PMOS (P-channel Metal oxide semiconductor) tubes MP1The grid of the PMOS transistor is connected with a positive electrode VDD of a power supply through a second RC lag compensation circuit and is connected with a third PMOS transistor MP3Grid and fourth PMOS tube MP4A gate electrode of (1). Fifth NMOS transistor MN5Is grounded through a first RC hysteresis compensation circuit.
The bias circuit comprises a reference current source IBThe first NMOS transistor M of the bias circuitCM0And a second NMOS transistor M of the bias circuitCM2And a bias circuit switchable switching tube array MCM1Reference current source IBThe first NMOS transistor M of the bias circuitCM0And a second NMOS transistor M of the bias circuitCM2And a bias circuit switchable switching tube array MCM1The current mirror structure is used for providing bias current for the main circuit of the fully differential operational amplifier and the common mode feedback circuit.
Switchable switch tube array M of bias circuitCM1Comprises a plurality of switchable NMOS tubes connected in parallel. Reference current source IBThe input end of the biasing circuit is connected with a power supply anode VDD, and the output end of the biasing circuit is connected with a first NMOS tube M of the biasing circuitCM0The drain electrode of the bias circuit is the first NMOS tube MCM0The drain electrode of the bias circuit is connected with the grid electrode, and a first NMOS tube M of the bias circuitCM0Is grounded. Second NMOS transistor M of bias circuitCM2The grid electrode of the transistor is connected with a first NMOS transistor M of a bias circuitCM0The grid of the bias circuit and the second NMOS tube MCM2The source electrode of the first differential amplifier circuit is grounded, and the drain electrode of the first differential amplifier circuit is connected with the first NMOS tube MN1Source electrode of and second NMOS transistor MN2Of the substrate. Switchable switch tube array M of bias circuitCM1The grid of the middle NMOS tube is connected with a first NMOS tube M of the bias circuitCM0Grid electrode and bias circuit switchable switch tube array MCM1The source electrode of the middle NMOS tube is grounded, and the drain electrode of the middle NMOS tube is connected with a fifth NMOS tube M of the second differential amplification circuitN5Source electrode of (1) and sixth NMOS transistor MN6Of the substrate.
First group of switchable switch tube array MN3The grid of the NMOS tubes connected in parallel is also connected with a first bias resistor RF1A first NMOS transistor M of a bias circuit is connectedCM0A second group of switchable switching tube arrays MN4The grid of the NMOS tubes connected in parallel is also connected with a second bias resistor RF2A first NMOS transistor M of a bias circuit is connectedCM0A gate electrode of (1).
The operational amplifier circuit of the embodiment of the inventionThe first differential amplifying circuit of the main circuit of the fully differential operational amplifier comprises an NMOS tube MN1,MN2,MCM2And PMOS transistor MP3,MP4. Differential input signal VIP,VINIs connected to MN1,MN2Through M of the gate electrodeN1,MN2At M, is amplifiedN1,MN2Is ofON1And VOP1And obtaining a first-stage amplified signal of differential input. PMOS tube MP3,MP4Is an active load that provides high impedance so that the first stage of the operational amplifier has high gain.
The forward amplification compensation and push-pull driving circuit as the second stage comprises an NMOS tube MN3,MN4PMOS transistor MP5,MP6And a compensation capacitor CM1,CM2. NMOS tube MN3,MN4The circuit has two functions of (1) forward amplification compensation and (2) push-pull type driving stage. Will MN3,MN4Through CF1And CF2Connected into positive feedback, i.e. MN3Gate through C ofF1AC coupling to VINDrain connected to VOPA forward amplification compensation path is provided. MN4Gate through C ofF2AC coupling to VIPDrain connected to VONAnd another forward amplification compensation path is provided to achieve the effect of broadband compensation. Furthermore MN3,MN4The static currents of the two NMOS tubes are determined by a bias circuit, but the dynamic currents of the two NMOS tubes are changed along with the magnitude of an input signal, and the larger the input signal is, the larger the dynamic current is, and the characteristics of a push-pull type driving stage are achieved. PMOS tube MP5,MP6Is connected with the grid input at VON1,VOP1Drain connected to VOPAnd VONFor the second stage of amplification, and in addition, a PMOS transistor MP5,MP6The dynamic current of (2) also changes with the magnitude of the input signal, and has the characteristics of a push-pull driving stage. Because M isN3And MN4Has two functions simultaneously, and C is added to increase the design flexibility of frequency compensationM1And CM2And finely adjusting the phase margin to ensure that various process angles can meet the requirement of the phase margin.
Common mode feedback circuitComprises an NMOS tube MN5,MN6,MCM1And PMOS transistor MP1,MP2-a differential amplifier structure formed of a resistor RS1,RS2Detecting the output common mode level, and stabilizing the output common mode level to a stabilized voltage V by negative feedbackREF. V in common mode feedback loopcmfbAnd VfBoth nodes are added with RC series compensation (R)C1,CC1And RC2,CC2) The purpose of zero point compensation is achieved, and the phase margin of the common mode feedback loop is assisted.
The operational amplifier circuit of the embodiment of the invention can adjust M according to different bandwidthsN3And MN4The number of the middle MOS transistors connected in parallel, the structure of the NMOS switching array according to the embodiment of the present invention is shown in fig. 3, and the structure of the PMOS switching array is shown in fig. 4, which can increase or decrease the current consumption under different bandwidth requirements. The power consumption of the common mode feedback loop is adjusted according to different bandwidths, so that the bias circuit can switch the switch tube array MCM1The architecture of fig. 3 may also be used. And in order to reduce systematic offset (systematic offset), two groups of switchable parallel PMOS (P-channel metal oxide semiconductor) tubes M of the common mode feedback circuitP1、MP2The architecture of fig. 4 may be employed to switch the number of parallel MOS transistors. The number of the parallel MOS tubes can be adjusted before leaving a factory and also adjusted in use.
The dynamic current of the push-pull output stage adopted by the above embodiment of the present invention varies with the magnitude of the input signal, and the larger the input signal is, the larger the dynamic current is, and vice versa, so that the smaller static current can be used to bias the push-pull output stage. And the push-pull output stage is analyzed by small signals, and the equivalent transconductance is g under the same static currentmn+gmpTransconductance g equivalent to the output stage of a conventional operational amplifiermn(or is g)mp) Compared with the prior art, the amplification can be increased by 1.5-2 times.
The frequency compensation method of the above embodiment of the present invention is considered as a broadband target, and the method considers selecting forward-forward (feed-forward) amplification compensation or cross-feedback miller compensation as in the background art.
The above embodiments of the present invention combine the two functions of forward amplification compensation and push-pull driving stageIn the switchable switch tube array, extra current is not needed to perform forward amplification compensation, so that electricity can be saved. In addition, the advantage of forward amplification compensation is that the transconductance of the forward amplification stage is properly designed, so that the traditional Miller compensation capacitor can be removed, and the bandwidth can be easily deduced. And then, the push-pull type driving stage is matched for use, so that a larger load can be driven by using lower static current, and the purpose of saving electricity is achieved. In the above embodiment of the present invention, two RC series circuits (R) are used to process the phase margin of the common mode feedback loop after the bandwidth of the main circuit is pushed outC1,CC1And RC2,CC2) The compensation achieves the effect of zero point compensation, and the power consumption of the common mode feedback loop can be saved.
Claims (9)
1. An operational amplifier circuit comprises two differential signal input ends, two differential signal output ends, a bias circuit, a fully differential operational amplifier main circuit and a common mode feedback circuit, and is characterized in that the fully differential operational amplifier main circuit comprises a first differential amplification circuit serving as a first stage and a forward amplification compensation and push-pull driving circuit serving as a second stage, and the forward amplification compensation and push-pull driving circuit comprises two groups of switchable switch tube arrays participating in forward amplification compensation and push-pull driving.
2. The operational amplifier circuit as claimed in claim 1, wherein the first differential amplifier circuit comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, and the forward amplification compensation and push-pull driving circuit comprises a fifth PMOS transistor, a sixth PMOS transistor, and the two switchable switch transistor arrays; the drain electrode of the first NMOS tube is connected with the positive electrode of the power supply through a third PMOS tube, and the drain electrode of the second NMOS tube is connected with the positive electrode of the power supply through a fourth PMOS tube; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and then connected with the biasing circuit, the grid electrode of the first NMOS tube is connected with the first differential signal input end, and the grid electrode of the second NMOS tube is connected with the second differential signal input end; each group of switchable switch tube arrays comprises a plurality of switchable NMOS tubes connected in parallel, the grid electrode of the fifth PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the sixth PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with the positive electrode of the power supply, and the drain electrode of the fifth PMOS tube is connected with the first differential signal output end and is grounded through the NMOS tubes of the first group of switchable switching tube arrays; the drain electrode of the sixth PMOS tube is connected with the second differential signal output end and is grounded through the NMOS tube of the second group of switchable switching tube arrays; the grid electrodes of the NMOS tubes connected in parallel with the first group of switchable switch tube arrays are connected with the grid electrode of the second NMOS tube through a first alternating current coupling capacitor, and the grid electrodes of the NMOS tubes connected in parallel with the second group of switchable switch tube arrays are connected with the grid electrode of the first NMOS tube through a second alternating current coupling capacitor.
3. The operational amplifier circuit of claim 2, wherein the common mode feedback circuit comprises a second differential amplifying circuit and a common mode sampling circuit; the second differential amplification circuit comprises a fifth NMOS tube, a sixth NMOS tube, two groups of switchable parallel PMOS tubes and a common mode sampling circuit, wherein the drain electrode of the fifth NMOS tube is connected with the anode of the power supply through the first group of switchable parallel PMOS tubes, and the drain electrode of the sixth NMOS tube is connected with the anode of the power supply through the second group of switchable parallel PMOS tubes; the source electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube and then connected with the bias circuit, the grid electrode of the fifth NMOS tube is connected with the output end of the common mode sampling circuit, and the grid electrode of the sixth NMOS tube is connected with the reference voltage signal input end; the common mode sampling circuit comprises two sampling resistors which are connected in series, and the connection point of the two sampling resistors is the output end of the common mode sampling circuit; two ends of the common mode sampling circuit are respectively connected with the first differential signal output end and the second differential signal output end.
4. The operational amplifier circuit of claim 3, wherein the common mode feedback circuit comprises a common mode feedback compensation circuit comprising a first RC hysteretic compensation circuit and a second RC hysteretic compensation circuit; the source electrode of the first group of the switchable parallel PMOS tubes and the source electrode of the second group of the switchable parallel PMOS tubes are connected with the positive electrode of the power supply, the drain electrode and the grid electrode of the first group of the switchable parallel PMOS tubes are connected with the drain electrode of the fifth NMOS tube, and the drain electrode and the grid electrode of the second group of the switchable parallel PMOS tubes are connected with the drain electrode of the sixth NMOS tube; the grid electrodes of the first group of switchable parallel PMOS tubes are connected with the positive electrode of the power supply through a second RC lag compensation circuit and are connected with the grid electrode of a third PMOS tube and the grid electrode of a fourth PMOS tube; the grid electrode of the fifth NMOS tube is grounded through the first RC hysteresis compensation circuit.
5. The operational amplifier circuit as claimed in claim 2, wherein the forward amplification compensation and push-pull driving circuit comprises two miller compensation capacitors, the first miller compensation capacitor is connected between the gate and the drain of the fifth PMOS transistor, and the second miller compensation capacitor is connected between the gate and the drain of the sixth PMOS transistor.
6. The operational amplifier circuit as claimed in claim 3, wherein the bias circuit comprises a reference current source, a first NMOS transistor of the bias circuit, a second NMOS transistor of the bias circuit, and a switchable switch transistor array of the bias circuit, the switchable switch transistor array of the bias circuit comprises a plurality of switchable parallel NMOS transistors; the input end of the reference current source is connected with the positive electrode of the power supply, the output end of the reference current source is connected with the drain electrode of the first NMOS tube of the bias circuit, the drain electrode of the first NMOS tube of the bias circuit is connected with the grid electrode, and the source electrode of the first NMOS tube of the bias circuit is grounded; the grid electrode of the second NMOS tube of the bias circuit is connected with the grid electrode of the first NMOS tube of the bias circuit, the source electrode of the second NMOS tube of the bias circuit is grounded, and the drain electrode of the second NMOS tube of the bias circuit is connected with the source electrode of the first NMOS tube of the first differential amplification circuit and the source electrode of the second NMOS tube; the grid electrode of the NMOS tube of the switchable switch tube array of the bias circuit is connected with the grid electrode of the first NMOS tube of the bias circuit, the source electrode of the NMOS tube of the switchable switch tube array of the bias circuit is grounded, and the drain electrode of the switchable switch tube array of the bias circuit is connected with the source electrode of the fifth NMOS tube of the second differential amplification circuit and the source electrode of the sixth NMOS tube.
7. The operational amplifier circuit as claimed in claim 6, wherein the gates of the NMOS transistors connected in parallel to the first group of switchable switching transistor arrays are connected to the gate of the first NMOS transistor of the bias circuit through a first bias resistor, and the gates of the NMOS transistors connected in parallel to the second group of switchable switching transistor arrays are connected to the gate of the first NMOS transistor of the bias circuit through a second bias resistor; the drain electrodes of the NMOS tubes connected in parallel with the first group of switchable switching tube arrays are connected with the drain electrode of the fifth PMOS tube, and the source electrodes of the NMOS tubes connected in parallel with the first group of switchable switching tube arrays are grounded; the drain electrodes of the NMOS tubes connected in parallel in the second group of switchable switch tube arrays are connected with the drain electrode of the sixth PMOS tube, and the source electrodes of the NMOS tubes connected in parallel in the second group of switchable switch tube arrays are grounded.
8. The operational amplifier circuit as claimed in claim 2, wherein the number of the parallel NMOS transistors in the two sets of switchable switch transistor arrays of the forward amplification compensation and push-pull driving circuit is adjusted according to the requirements of bandwidth and current consumption.
9. The operational amplifier circuit as claimed in claim 6, wherein the number of parallel PMOS transistors in the two sets of switchable parallel PMOS transistors and/or the number of parallel NMOS transistors in the bias circuit switchable switch transistor array is adjusted according to the requirements of the bandwidth and the power consumption of the common mode feedback loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111004370.9A CN113612449B (en) | 2021-08-30 | 2021-08-30 | An operational amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111004370.9A CN113612449B (en) | 2021-08-30 | 2021-08-30 | An operational amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113612449A true CN113612449A (en) | 2021-11-05 |
| CN113612449B CN113612449B (en) | 2025-03-14 |
Family
ID=78309709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111004370.9A Active CN113612449B (en) | 2021-08-30 | 2021-08-30 | An operational amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113612449B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115622579A (en) * | 2022-11-08 | 2023-01-17 | 杭州地芯科技有限公司 | Open-loop compensation circuit based on phase inverter operational amplifier, receiver and radio frequency transceiver |
| CN118249759A (en) * | 2024-05-29 | 2024-06-25 | 成都玖锦科技有限公司 | Broadband programmable gain amplifier |
| US12081175B2 (en) | 2022-05-18 | 2024-09-03 | Hangzhou Geo-Chip Technology Co., Ltd. | Operational amplifier and electronic system |
| CN118646372A (en) * | 2024-08-14 | 2024-09-13 | 深圳市微源半导体股份有限公司 | Operational amplifier circuit, chip and electronic device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60100807A (en) * | 1983-11-08 | 1985-06-04 | Nec Corp | Operational amplifier |
| TW200719584A (en) * | 2005-11-02 | 2007-05-16 | Marvell World Trade Ltd | High-bandwidth high-gain amplifier |
| CN101917169A (en) * | 2010-08-05 | 2010-12-15 | 复旦大学 | High Bandwidth Low Power Frequency Compensated Three-Stage Operational Amplifier |
| CN103219961A (en) * | 2013-04-10 | 2013-07-24 | 中国科学院微电子研究所 | Bandwidth-adjustable operational amplifier circuit |
| CN215420202U (en) * | 2021-08-30 | 2022-01-04 | 北京北斗华大科技有限公司 | An operational amplifier circuit |
-
2021
- 2021-08-30 CN CN202111004370.9A patent/CN113612449B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60100807A (en) * | 1983-11-08 | 1985-06-04 | Nec Corp | Operational amplifier |
| TW200719584A (en) * | 2005-11-02 | 2007-05-16 | Marvell World Trade Ltd | High-bandwidth high-gain amplifier |
| CN101917169A (en) * | 2010-08-05 | 2010-12-15 | 复旦大学 | High Bandwidth Low Power Frequency Compensated Three-Stage Operational Amplifier |
| CN103219961A (en) * | 2013-04-10 | 2013-07-24 | 中国科学院微电子研究所 | Bandwidth-adjustable operational amplifier circuit |
| CN215420202U (en) * | 2021-08-30 | 2022-01-04 | 北京北斗华大科技有限公司 | An operational amplifier circuit |
Non-Patent Citations (1)
| Title |
|---|
| 邹晓磊: ""基于通道复用技术的心电信号采集模拟前端电路设计"", 《中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑》, 15 February 2021 (2021-02-15) * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12081175B2 (en) | 2022-05-18 | 2024-09-03 | Hangzhou Geo-Chip Technology Co., Ltd. | Operational amplifier and electronic system |
| CN115622579A (en) * | 2022-11-08 | 2023-01-17 | 杭州地芯科技有限公司 | Open-loop compensation circuit based on phase inverter operational amplifier, receiver and radio frequency transceiver |
| CN115622579B (en) * | 2022-11-08 | 2024-06-11 | 杭州地芯科技有限公司 | Open loop compensation circuit based on inverter operational amplifier, receiver and radio frequency transceiver |
| CN118249759A (en) * | 2024-05-29 | 2024-06-25 | 成都玖锦科技有限公司 | Broadband programmable gain amplifier |
| CN118646372A (en) * | 2024-08-14 | 2024-09-13 | 深圳市微源半导体股份有限公司 | Operational amplifier circuit, chip and electronic device |
| CN118646372B (en) * | 2024-08-14 | 2024-11-08 | 深圳市微源半导体股份有限公司 | Operational amplifier circuit, chip and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113612449B (en) | 2025-03-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113612449B (en) | An operational amplifier circuit | |
| JP4068227B2 (en) | Low voltage CMOS operational amplifier circuit and sample and hold circuit having the same | |
| CN101951236B (en) | Digital variable gain amplifier | |
| US6577184B2 (en) | Switched-capacitor, common-mode feedback circuit for a differential amplifier without tail current | |
| EP1863171A1 (en) | Operational amplifier of class AB | |
| CN109951161B (en) | A Complementary Digital Variable Gain Amplifier | |
| US6150884A (en) | Multistage amplifier circuit with improved nested transconductance capacitance compensation | |
| CN113726298A (en) | Fully-differential two-stage operational amplifier circuit | |
| JPH07307624A (en) | Low voltage high speed CMOS operational amplifier | |
| CN107078700B (en) | Amplifier circuit and amplifier arrangement | |
| CN201846315U (en) | Digital variable gain amplifier | |
| CN116470857A (en) | Low-mismatch Class-AB output stage bias circuit | |
| CN215420202U (en) | An operational amplifier circuit | |
| Carrillo et al. | 1-V rail-to-rail bulk-driven CMOS OTA with enhanced gain and gain-bandwidth product | |
| CN110224700A (en) | A kind of high speed complementation type dual power supply operational amplifier | |
| CN112511110B (en) | High-linearity programmable gain amplifier | |
| Kai et al. | A 168 dB high gain folded cascode operational amplifier for Delta-Sigma ADC | |
| CN111697936A (en) | Low-power-consumption complementary digital variable gain amplifier | |
| Hussain et al. | A 45nm ultra-low power operational amplifier with high gain and high CMRR | |
| US7315210B2 (en) | Differential operational amplifier | |
| Vij et al. | An operational amplifier with recycling folded Cascode topology and adaptive biaisng | |
| CN115149910B (en) | Capacitance multiplication frequency compensation circuit for three-stage operational amplifier | |
| TWI806543B (en) | Amplifier and method for controlling common mode voltage of the same | |
| CN115167595B (en) | Low-power consumption high-power supply ripple rejection ratio voltage buffer | |
| JP2004180268A (en) | Amplifier circuit and liquid crystal display device using this |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |