CN113539793A - Surface treatment process before feeding of power chip - Google Patents
Surface treatment process before feeding of power chip Download PDFInfo
- Publication number
- CN113539793A CN113539793A CN202110801519.XA CN202110801519A CN113539793A CN 113539793 A CN113539793 A CN 113539793A CN 202110801519 A CN202110801519 A CN 202110801519A CN 113539793 A CN113539793 A CN 113539793A
- Authority
- CN
- China
- Prior art keywords
- silicon wafer
- parts
- power chip
- before feeding
- surface treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H10F71/121—The active layers comprising only Group IV materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Weting (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
The invention discloses a surface treatment process before feeding of a power chip, which comprises the following steps: A. firstly, cleaning the surface of a silicon wafer to remove impurities and oil stains, and then airing; B. putting the dried silicon wafer into an alkaline corrosive liquid to corrode the silicon wafer to form a surface gold tower; C. b, washing the silicon wafer corroded by the alkaline solution in the step B by deionized water and airing; D. and then the dried silicon wafer is put into an acidic corrosive liquid to carry out correction treatment on the surface of the silicon wafer after the alkaline corrosion, and impurities generated after the alkaline corrosion are further reacted and corrected, so that the structure of the gold-seed tower is more uniform.
Description
Technical Field
The invention relates to the technical field of silicon wafer surface treatment, in particular to a surface treatment process before feeding of a power chip.
Background
The thickness of the silicon wafer is also a factor affecting productivity because it relates to the number of silicon wafers produced per block. Ultra-thin silicon wafers present additional challenges to wire saw technology because their production process is much more difficult. In addition to the mechanical fragility of the silicon wafer, fine cracks and bowing can negatively impact product yield if the wire saw process is not precisely controlled. Ultra-thin silicon wafer wire saw systems must be capable of precise control of process linearity, cutting wire speeds and pressures, and cutting coolants. Regardless of the thickness of the silicon wafer, the crystalline silicon photovoltaic cell manufacturers have made extremely high requirements on the quality of the silicon wafer. The wafer does not have surface damage (microcracks, wire saw marks), topographical defects (bowing, roughness, thickness variation) are minimized, and the need for additional back end processing such as polishing is minimized.
The silicon wafer needs to be pretreated on the surface before processing, and the existing processing method is complex in operation and cannot improve the contact force of the silicon wafer surface, so that improvement is needed.
Disclosure of Invention
The invention aims to provide a surface treatment process before feeding of a power chip, so as to solve the problems in the background technology.
In order to achieve the purpose, the invention provides the following technical scheme: a surface treatment process before feeding of a power chip comprises the following steps:
A. firstly, cleaning the surface of a silicon wafer to remove impurities and oil stains, and then airing;
B. putting the dried silicon wafer into an alkaline corrosive liquid to corrode the silicon wafer to form a surface gold tower;
C. b, washing the silicon wafer corroded by the alkaline solution in the step B by deionized water and airing;
D. and then, the dried silicon wafer is placed into an acidic corrosive liquid to carry out correction treatment on the surface of the silicon wafer subjected to alkali corrosion, and impurities generated after the alkali corrosion are further subjected to reaction correction, so that the structure of the gold-seed tower is more uniform.
Preferably, the alkaline solution corrosive liquid in the step B comprises 5-8 parts by mass of sodium chlorate, 2-6 parts by mass of sodium hydroxide and 30-40 parts by mass of water.
Preferably, the acidic etching solution in the step D comprises, by mass, 1-3 parts of hydrofluoric acid, 2-6 parts of silicon dioxide etching solution, 4-8 parts of glycerol and 40-50 parts of water.
Preferably, the height of the neutron tower in the step B is 10mm-30 mm.
Preferably, the temperature of the alkaline solution corrosion solution in the step B is 60-70 ℃, and the corrosion time is 50-60 s.
Preferably, the deionized water washing time in the step C is 60min-80 min.
Compared with the prior art, the invention has the beneficial effects that: the operation method is simple, and the surface of the processed silicon wafer can be more easily subjected to diffusion doping and surface electrode contact; according to the invention, the alkaline corrosion solution is adopted for corrosion, and then the acidic corrosion solution is adopted for corrosion, so that the structure of the surface of the silicon wafer is more uniform, and the surface contact force is improved.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
the invention provides the following technical scheme: a surface treatment process before feeding of a power chip comprises the following steps:
A. firstly, cleaning the surface of a silicon wafer to remove impurities and oil stains, and then airing;
B. putting the dried silicon wafer into an alkaline corrosive liquid to corrode the silicon wafer to form a surface gold tower;
C. b, washing the silicon wafer corroded by the alkaline solution in the step B by deionized water and airing;
D. and then, the dried silicon wafer is placed into an acidic corrosive liquid to carry out correction treatment on the surface of the silicon wafer subjected to alkali corrosion, and impurities generated after the alkali corrosion are further subjected to reaction correction, so that the structure of the gold-seed tower is more uniform.
In this embodiment, the components of the alkaline corrosion solution in step B include, by mass, 5 parts of sodium chlorate, 2 parts of sodium hydroxide, and 30 parts of water.
In this embodiment, the acidic etching solution in step D includes, by mass, 1 part of the hydrofluoric acid, 2 parts of the silicon dioxide etching solution, 4 parts of glycerol, and 40 parts of water.
In this example, the height of the seed tower in step B was 10 mm.
In this embodiment, the temperature of the alkaline etching solution in step B is 60 ℃ and the etching time is 50 s.
In this embodiment, the deionized water rinsing time in step C is 60 min.
Example two:
a surface treatment process before feeding of a power chip comprises the following steps:
A. firstly, cleaning the surface of a silicon wafer to remove impurities and oil stains, and then airing;
B. putting the dried silicon wafer into an alkaline corrosive liquid to corrode the silicon wafer to form a surface gold tower;
C. b, washing the silicon wafer corroded by the alkaline solution in the step B by deionized water and airing;
D. and then, the dried silicon wafer is placed into an acidic corrosive liquid to carry out correction treatment on the surface of the silicon wafer subjected to alkali corrosion, and impurities generated after the alkali corrosion are further subjected to reaction correction, so that the structure of the gold-seed tower is more uniform.
In this embodiment, the components of the alkaline corrosion solution in step B include, by mass, 8 parts of sodium chlorate, 6 parts of sodium hydroxide, and 40 parts of water.
In this embodiment, the acidic etching solution in step D includes, by mass, 3 parts of the hydrofluoric acid, 6 parts of the silicon dioxide etching solution, 8 parts of glycerol, and 50 parts of water.
In this example, the height of the seed tower in step B was 30 mm.
In this embodiment, the temperature of the alkaline etching solution in step B is 70 ℃ and the etching time is 60 s.
In this embodiment, the deionized water rinsing time in step C is 80 min.
Example three:
a surface treatment process before feeding of a power chip comprises the following steps:
A. firstly, cleaning the surface of a silicon wafer to remove impurities and oil stains, and then airing;
B. putting the dried silicon wafer into an alkaline corrosive liquid to corrode the silicon wafer to form a surface gold tower;
C. b, washing the silicon wafer corroded by the alkaline solution in the step B by deionized water and airing;
D. and then, the dried silicon wafer is placed into an acidic corrosive liquid to carry out correction treatment on the surface of the silicon wafer subjected to alkali corrosion, and impurities generated after the alkali corrosion are further subjected to reaction correction, so that the structure of the gold-seed tower is more uniform.
In this embodiment, the components of the alkaline corrosion solution in step B include, by mass, 6 parts of sodium chlorate, 3 parts of sodium hydroxide, and 32 parts of water.
In this embodiment, the acidic etching solution in step D includes, by mass, 1 part of the hydrofluoric acid, 3 parts of the silicon dioxide etching solution, 4 parts of glycerol, and 42 parts of water.
In this example, the height of the seed tower in step B was 15 mm.
In this embodiment, the temperature of the alkaline etching solution in step B is 62 ℃, and the etching time is 52 s.
In this embodiment, the deionized water rinsing time in step C is 65 min.
Example four:
a surface treatment process before feeding of a power chip comprises the following steps:
A. firstly, cleaning the surface of a silicon wafer to remove impurities and oil stains, and then airing;
B. putting the dried silicon wafer into an alkaline corrosive liquid to corrode the silicon wafer to form a surface gold tower;
C. b, washing the silicon wafer corroded by the alkaline solution in the step B by deionized water and airing;
D. and then, the dried silicon wafer is placed into an acidic corrosive liquid to carry out correction treatment on the surface of the silicon wafer subjected to alkali corrosion, and impurities generated after the alkali corrosion are further subjected to reaction correction, so that the structure of the gold-seed tower is more uniform.
In this embodiment, the components of the alkaline corrosion solution in step B include, by mass, 7 parts of sodium chlorate, 5 parts of sodium hydroxide, and 38 parts of water.
In this embodiment, the acidic etching solution in step D includes, by mass, 2 parts of the hydrofluoric acid, 5 parts of the silicon dioxide etching solution, 7 parts of glycerol, and 48 parts of water.
In this example, the height of the seed tower in step B was 25 mm.
In this embodiment, the temperature of the alkaline etching solution in step B is 68 ℃, and the etching time is 58 s.
In this embodiment, the deionized water rinsing time in step C is 78 min.
Example five:
a surface treatment process before feeding of a power chip comprises the following steps:
A. firstly, cleaning the surface of a silicon wafer to remove impurities and oil stains, and then airing;
B. putting the dried silicon wafer into an alkaline corrosive liquid to corrode the silicon wafer to form a surface gold tower;
C. b, washing the silicon wafer corroded by the alkaline solution in the step B by deionized water and airing;
D. and then, the dried silicon wafer is placed into an acidic corrosive liquid to carry out correction treatment on the surface of the silicon wafer subjected to alkali corrosion, and impurities generated after the alkali corrosion are further subjected to reaction correction, so that the structure of the gold-seed tower is more uniform.
In this embodiment, the components of the alkaline corrosion solution in step B include, by mass, 6 parts of sodium chlorate, 4 parts of sodium hydroxide, and 35 parts of water.
In this embodiment, the acidic etching solution in step D includes, by mass, 2 parts of the hydrofluoric acid, 4 parts of the silicon dioxide etching solution, 6 parts of glycerol, and 45 parts of water.
In this example, the height of the seed tower in step B was 20 mm.
In this embodiment, the temperature of the alkaline etching solution in step B is 65 ℃ and the etching time is 55 s.
In this embodiment, the deionized water rinsing time in step C is 70 min.
The operation method is simple, and the surface of the processed silicon wafer can be more easily subjected to diffusion doping and surface electrode contact; according to the invention, the alkaline corrosion solution is adopted for corrosion, and then the acidic corrosion solution is adopted for corrosion, so that the structure of the surface of the silicon wafer is more uniform, and the surface contact force is improved.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. A surface treatment process before feeding of a power chip is characterized by comprising the following steps: the method comprises the following steps:
A. firstly, cleaning the surface of a silicon wafer to remove impurities and oil stains, and then airing;
B. putting the dried silicon wafer into an alkaline corrosive liquid to corrode the silicon wafer to form a surface gold tower;
C. b, washing the silicon wafer corroded by the alkaline solution in the step B by deionized water and airing;
D. and then, the dried silicon wafer is placed into an acidic corrosive liquid to carry out correction treatment on the surface of the silicon wafer subjected to alkali corrosion, and impurities generated after the alkali corrosion are further subjected to reaction correction, so that the structure of the gold-seed tower is more uniform.
2. The process of claim 1, wherein the surface treatment process before feeding of the power chip comprises the following steps: and the components of the alkaline solution corrosive liquid in the step B comprise 5-8 parts of sodium chlorate, 2-6 parts of sodium hydroxide and 30-40 parts of water by weight.
3. The process of claim 1, wherein the surface treatment process before feeding of the power chip comprises the following steps: and the acidic corrosive liquid in the step D comprises 1-3 parts by mass of hydrofluoric acid, 2-6 parts by mass of silicon dioxide etching liquid, 4-8 parts by mass of glycerol and 40-50 parts by mass of water.
4. The process of claim 1, wherein the surface treatment process before feeding of the power chip comprises the following steps: and the height of the neutron tower in the step B is 10mm-30 mm.
5. The process of claim 1, wherein the surface treatment process before feeding of the power chip comprises the following steps: and in the step B, the temperature of the alkaline solution corrosion solution is 60-70 ℃, and the corrosion time is 50-60 s.
6. The process of claim 1, wherein the surface treatment process before feeding of the power chip comprises the following steps: and the deionized water washing time in the step C is 60-80 min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110801519.XA CN113539793A (en) | 2021-07-15 | 2021-07-15 | Surface treatment process before feeding of power chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110801519.XA CN113539793A (en) | 2021-07-15 | 2021-07-15 | Surface treatment process before feeding of power chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113539793A true CN113539793A (en) | 2021-10-22 |
Family
ID=78128121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110801519.XA Pending CN113539793A (en) | 2021-07-15 | 2021-07-15 | Surface treatment process before feeding of power chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113539793A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010007240A1 (en) * | 1999-07-14 | 2001-07-12 | Seh America, Inc. | High efficiency silicon wafer optimized for advanced semiconductor devices |
| US20030171075A1 (en) * | 2000-06-29 | 2003-09-11 | Takashi Nihonmatsu | Method for processing semiconductor wafer and semiconductor wafer |
| CN101634046A (en) * | 2009-07-24 | 2010-01-27 | 江苏林洋新能源有限公司 | Method for preparing single crystal silicon velvet surface |
| CN103924305A (en) * | 2013-01-14 | 2014-07-16 | 东莞市长安东阳光铝业研发有限公司 | Making method of quasi-monocrystalline silicon wafer suede |
| CN107170846A (en) * | 2017-06-02 | 2017-09-15 | 嘉兴尚能光伏材料科技有限公司 | The surface matte preparation method of monocrystaline silicon solar cell |
| CN112951716A (en) * | 2021-03-22 | 2021-06-11 | 上海中欣晶圆半导体科技有限公司 | Method for improving flatness and roughness through mixed corrosion |
-
2021
- 2021-07-15 CN CN202110801519.XA patent/CN113539793A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010007240A1 (en) * | 1999-07-14 | 2001-07-12 | Seh America, Inc. | High efficiency silicon wafer optimized for advanced semiconductor devices |
| US20030171075A1 (en) * | 2000-06-29 | 2003-09-11 | Takashi Nihonmatsu | Method for processing semiconductor wafer and semiconductor wafer |
| CN101634046A (en) * | 2009-07-24 | 2010-01-27 | 江苏林洋新能源有限公司 | Method for preparing single crystal silicon velvet surface |
| CN103924305A (en) * | 2013-01-14 | 2014-07-16 | 东莞市长安东阳光铝业研发有限公司 | Making method of quasi-monocrystalline silicon wafer suede |
| CN107170846A (en) * | 2017-06-02 | 2017-09-15 | 嘉兴尚能光伏材料科技有限公司 | The surface matte preparation method of monocrystaline silicon solar cell |
| CN112951716A (en) * | 2021-03-22 | 2021-06-11 | 上海中欣晶圆半导体科技有限公司 | Method for improving flatness and roughness through mixed corrosion |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103441182B (en) | The matte processing method of solar cell and solar cell | |
| CN101409312B (en) | Method for fine-hair maring using monocrystalline silicon slice | |
| CN102751377A (en) | Wet surface processing technique used for manufacturing high efficiency crystalline silicon solar cells | |
| CN104253033A (en) | Semiconductor wafer back technology and forming method of power device | |
| CN105118898A (en) | Silicon chip surface passivation method and manufacturing method of N type double-face cell based thereon | |
| CN113707535B (en) | Etching method of indium phosphide wafer | |
| CN113430652A (en) | Cleaning and saturation method of quartz boat for diffusion of crystalline silicon solar cell | |
| CN104218122A (en) | Texturing method for decreasing polycrystalline silicon reflectivity during diamond wire cutting | |
| CN114335247A (en) | Double-texturing cleaning process and device for heterojunction battery | |
| CN103924305B (en) | A kind of preparation method of pseudo single crystal silicon chip suede | |
| CN111105995B (en) | A method for cleaning and texturing monocrystalline silicon wafers | |
| CN102214726B (en) | Method for treating flocking on surface of solar silicon slice | |
| CN114318549A (en) | Monocrystalline silicon texturing additive for weak rough polishing process and use method | |
| CN109755102B (en) | Silicon wafer laser and alkali liquor combined texturing process | |
| CN113539793A (en) | Surface treatment process before feeding of power chip | |
| CN113161447B (en) | A phosphorus hydrogen annealing pretreatment method for casting single crystal or polycrystalline silicon wafers | |
| CN114420793A (en) | A kind of preparation process of crystalline silicon battery slicing | |
| CN103531667A (en) | Unqualified solar cell slice processing method | |
| KR101642045B1 (en) | Wafer for use in solar cells, manufacturing method of wafer for use in solar cells, solar cell manufacturing method and solar cell module manufacturing method | |
| CN113990981B (en) | Single crystal suede smooth and round treatment process | |
| CN113990984B (en) | A cleaning method for PERC crystalline silicon battery | |
| CN115763637A (en) | Preparation method of solar cell texture | |
| CN109352430B (en) | Processing method for reducing bending degree of germanium grinding sheet | |
| CN112876090A (en) | Chemical thinning method for ultrathin glass | |
| CN118197970B (en) | Monitoring method for etching of front-side coiling and plating polycrystalline silicon of TOPCO battery |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20211022 |