CN113489594A

CN113489594A - PCIE real-time network card based on FPGA module

Info

Publication number: CN113489594A
Application number: CN202110623596.0A
Authority: CN
Inventors: 王峰
Original assignee: Beijing Avic Shuangxing Technology Co ltd
Current assignee: Beijing Avic Shuangxing Technology Co ltd
Priority date: 2021-06-04
Filing date: 2021-06-04
Publication date: 2021-10-08
Anticipated expiration: 2041-06-04
Also published as: CN113489594B

Abstract

The present invention provides a PCI E real-time network card based on an FPGA module, comprising: a ZYNQ module, including an FPGA chip; at least one PHY chip connected to the ZYNQ module, the PHY chip communicates with the ZYNQ through MI I and/or RMI I interfaces The module performs data interaction, and the PHY chip is connected to an external interface; the PCI E bus is connected to the ZYNQ module for transferring the received data to the ZYNQ module for processing. The ZYNQ module includes an FPGA chip with an ARM core; the FPGA chip is connected to the host memory through the PCI E bus, and the FPGA chip and the host memory perform data interaction through the PCI E bus. Based on the FPGA chip with ARM core for processing, the PCI E bus communication rate of the PCI E real-time network card breaks through the bottleneck, improves the communication rate, and has the advantage of high transmission rate.

Description

PCIE real-time network card based on FPGA module

Technical Field

The invention relates to a real-time network card technology, in particular to a PCIE real-time network card based on an FPGA module.

Background

With the rapid development of computer network technology, in order to meet the requirements of various application environments and application layers, many different types of real-time network cards, such as USB real-time network cards, PCI real-time network cards, PCIX real-time network cards, PCIE real-time network cards, etc., appear, and the most popular type of real-time network card in the market is the gigabit PCIE real-time network card.

A common technical solution of the gigabit PCIE real-time network card is to select an ethernet controller chip of the real-time network card, for example, a chip such as RTL81390D commonly found in the market, and design a circuit around the main control chip. The PCIE real-time network card designed by the scheme completely meets the standard of IEEE 802.3 on a physical layer and a data link layer, and after the PCIE real-time network card is connected with a computer, the PCIE real-time network card serves as a physical connection line between the computer and a network cable.

Although the real-time network card designed according to the common technical scheme meets the basic application of the Ethernet in terms of functions, the transmission rate of the real-time network card is low.

Disclosure of Invention

The embodiment of the invention provides a PCIE real-time network card based on an FPGA module, which is processed based on an FPGA chip with an ARM core, so that the PCIE bus communication rate of the PCIE real-time network card breaks through the bottleneck, the communication rate is improved, and the transmission rate is high.

In a first aspect of the embodiments of the present invention, a PCIE real-time network card based on an FPGA module is provided, including:

the ZYNQ module comprises an FPGA chip;

the PHY chip is connected with the ZYNQ module, performs data interaction with the ZYNQ module through an MII interface and/or an RMII interface, and is connected with an external interface;

and the PCIE bus is connected with the ZYNQ module and used for transmitting the received data to the ZYNQ module for processing.

Optionally, in a possible implementation manner of the first aspect, the ZYNQ module includes an FPGA chip with an ARM core;

the FPGA chip is connected with a host memory through the PCIE bus, and the FPGA chip and the host memory perform data interaction through the PCIE bus.

Optionally, in a possible implementation manner of the first aspect, the FPGA chip is connected to a clock circuit.

Optionally, in a possible implementation manner of the first aspect, the apparatus further includes double-rate synchronous dynamic random access memories respectively connected to the ZYNQ modules, and configured to perform data interaction with the ZYNQ modules.

Optionally, in a possible implementation manner of the first aspect, the apparatus further includes one or more of a pci ex2 interface, a gigabit ethernet interface, a UART serial interface, an SD card interface, and a JTAG interface, which are respectively connected to the FPGA chip, and are used for performing data interaction.

Optionally, in a possible implementation manner of the first aspect, the synchronous dynamic random access memory includes two;

and an address line and a control line of the synchronous dynamic random access memory are respectively connected with the ZYNQ module.

Optionally, in a possible implementation manner of the first aspect, one of the sdram and the ZYNQ module is in a data transmission connection mode with data being 16 bits high;

and the other synchronous dynamic random access memory and the ZYNQ module adopt a data transmission connection mode of 16 low bits of data.

Optionally, in a possible implementation manner of the first aspect, the ZYNQ module is connected to an QSPI FLASH chip, and the QSPI FLASH chip is configured to boot the ZYNQ module and boot a mirror image.

Optionally, in a possible implementation manner of the first aspect, the ZYNQ module is connected to an eMMC FLASH chip, and the eMMC FLASH chip is configured to store any one or more of an application program, a system file, and a data file.

Optionally, in a possible implementation manner of the first aspect, the clock circuit is configured to provide an active clock, and provide clock pulses to the ARM core and the FPGA chip respectively;

and the ARM core and the FPGA chip respectively work based on the received active clock.

The PCIE real-time network card based on the FPGA module provided by the invention is processed based on the FPGA chip with the ARM core, so that the PCIE bus communication speed of the PCIE real-time network card breaks through the bottleneck, the communication speed is improved, and the PCIE real-time network card has the advantage of high transmission speed.

The technical scheme of the invention fully utilizes the ARM core provided by the hardware part to build a real-time operating system, and utilizes the logic control capability of the ARM and the real-time characteristic of the operating system to realize the network transceiving of big data, the real-time network communication and the extremely high bandwidth utilization rate.

The technical scheme of the invention ensures that the performance of the PCIE is fully used in the network receiving and transmitting of the big data. According to a common technical scheme, a PCIE bus of a real-time network card is limited by a network communication protocol and a bandwidth of a network can only exert a transceiving capability of 1 Gb/s. The technical scheme of the invention uses the ARM core with the real-time operating system, and PCIE is managed by the ARM core, so that the performance of PCIE2.0 x4 in the technical scheme is fully utilized, and the peak rate of 20Gb/s can be theoretically reached.

Drawings

Fig. 1 is a schematic structural diagram of a PCIE real-time network card based on an FPGA module;

fig. 2 is a schematic diagram of a connection structure of the FPGA and the host via the PCIE bus;

FIG. 3 is a schematic diagram of a general scheme of a real-time network card implemented based on ZYNQ;

fig. 4 is a schematic structural diagram of a first embodiment of a real-time network card board;

fig. 5 is a schematic structural diagram of a second embodiment of a real-time network card board;

fig. 6 is a schematic diagram of a first embodiment of a hardware structure of a PCIE real-time network card based on an FPGA module;

fig. 7 is a schematic diagram of a second embodiment of a PCIE real-time network card hardware structure based on an FPGA module;

FIG. 8 is a schematic structural diagram of a ZYNQ module and/or a ZYNQ chip;

FIG. 9 is a schematic diagram of naming rules of a ZYNQ module and/or a ZYNQ chip;

FIG. 10A is a diagram illustrating the detailed configuration of a DDR \ DDR3 DRAM;

FIG. 10B is a diagram illustrating a hardware connection of a DDR \ DDR3 DRAM;

FIG. 10C is a schematic diagram of a DDR \ DDR3 DRAM;

FIG. 10D is a schematic diagram of pin assignment for DDR \ DDR3 DRAM.

FIG. 11A is a schematic view of a specific configuration of QSPI FLASH;

FIG. 11B is a diagram illustrating the hardware connection of QSPI FLASH;

FIG. 11C is a schematic view of QSPI FLASH;

FIG. 11D is a pin assignment diagram of QSPI FLASH;

fig. 12A is a schematic diagram of a specific configuration of an eMMC FLASH;

fig. 12B is a schematic diagram of a hardware connection mode of the eMMC FLASH;

fig. 12C is a schematic diagram of eMMC FLASH;

fig. 12D is a pin assignment diagram of the eMMC FLASH;

FIG. 13A is a schematic diagram of a PS system clock source;

FIG. 13B is a schematic diagram of pin assignment of a PS system clock source;

FIG. 13C is a schematic diagram of a PL system clock source;

FIG. 13D is a pin allocation diagram of a PL system clock source;

FIG. 14A is a diagram illustrating a hardware connection of a USB-UART;

FIG. 14B is a schematic diagram of a USB-UART to serial port;

FIG. 14C is a schematic diagram of pin allocation for USB-UART to serial port;

FIG. 15 is a schematic diagram of JTAG;

FIG. 16 is a diagram illustrating default information of a GPHY chip;

FIG. 17A is a schematic diagram of a hardware connection mode of a 1-way Ethernet PHY chip at a ZYNQ PS end;

FIG. 17B is a schematic diagram of a 1-way Ethernet PHY chip at ZYNQ PS end;

fig. 17C is a diagram illustrating PS-side gigabit ethernet pin assignment;

FIG. 17D shows a hardware connection of a 1-way Ethernet PHY chip at the ZYNQ PL terminal;

FIG. 17E is a schematic diagram of a 1-way Ethernet PHY chip at ZYNQ PL end;

FIG. 17F is a diagram of PL terminal gigabit Ethernet pin assignment;

FIG. 18A is a diagram illustrating a hardware connection of a PCIe interface;

FIG. 18B is a schematic diagram of a PCIe interface;

fig. 18C is a schematic diagram of PCIE interface FPGA pin allocation;

FIG. 19A is a schematic diagram of the hardware connection between Zynq7000PS and SD card connectors;

FIG. 19B is a schematic diagram of an SD card slot;

FIG. 19C is a schematic diagram of SD card slot pin assignment;

FIG. 20 is a schematic diagram of the RT-NET power supply principle;

fig. 21 is a size structure diagram of a PCIE real-time network card.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.

It should be understood that, in various embodiments of the present invention, the sequence numbers of the processes do not mean the execution sequence, and the execution sequence of the processes should be determined by the functions and the internal logic of the processes, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

It should be understood that in the present application, "comprising" and "having" and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that, in the present invention, "a plurality" means two or more. "and/or" is merely an association describing an associated object, meaning that three relationships may exist, for example, and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "comprises A, B and C" and "comprises A, B, C" means that all three of A, B, C comprise, "comprises A, B or C" means that one of A, B, C comprises, "comprises A, B and/or C" means that any 1 or any 2 or 3 of A, B, C comprises.

It should be understood that in the present invention, "B corresponding to a", "a corresponds to B", or "B corresponds to a" means that B is associated with a, and B can be determined from a. Determining B from a does not mean determining B from a alone, but may be determined from a and/or other information. And the matching of A and B means that the similarity of A and B is greater than or equal to a preset threshold value.

As used herein, "if" may be interpreted as "at … …" or "when … …" or "in response to a determination" or "in response to a detection", depending on the context.

The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

The present invention provides a meaning of a word

ZYNQ: an extensible processing chip;

PCIE: a high speed serial computer expansion bus standard;

RMII: simplifying a media independent interface;

PHY: the physical layer is the lowest layer of the OSI and generally refers to a chip for interfacing with external signals;

PS system: a Processing System (Processing System) which is a Processing part of the SOC of the ARM;

PL System: programmable Logic (progamble Logic) which is the processing part of the FPGA;

DDR: synchronous dynamic random access memory.

The invention provides a PCIE real-time network card based on an FPGA module, which comprises an application layer, a link layer and a physical layer which are connected in sequence as shown in a schematic structural diagram of figure 1, and comprises the following components:

in a link layer, the ZYNQ module comprises an FPGA chip;

at least one PHY chip connected with the ZYNQ module is arranged on the physical layer, the PHY chip performs data interaction with the ZYNQ module through an MII interface and/or an RMII interface, and the PHY chip is connected with an external interface;

and a PCIE bus is arranged on the application layer, is connected with the ZYNQ module and is used for transmitting the received data to the ZYNQ module for processing.

The PHY chip interacts with the ZYNQ module through an MII/RMII interface to realize the functions of link control and communication. An mii (medium Independent interface), which is a media Independent interface, is responsible for communication connection between the PHY and the network controller. According to the scheme, the communication connection between the PHY and the network controller is realized by adopting the RMII (reduced Medium Independent interface), and the problem that the MII consumes more IO pin resources is solved.

The functions implemented by the data link layer include: and the data frames transmitted from the physical layer and the master station core layer are packed or unpacked, the receiving and transmitting sequence of the data frames is controlled, and the frame errors occurring in the transmission process are detected and recovered.

The PCIE bus is a novel serial point-to-point I/O bus system, uses full duplex and point-to-point technology, obviously reduces the number of buses, and adopts a differential transmission mode to greatly reduce the interference between the buses, and the speed can reach 5.0 Gb/s. The real-time network card of the bus can be more suitable for the requirements of networks with higher speed and higher bandwidth, so PCIE is selected to realize the main control function and is responsible for realizing the bus communication management and controlling system software, and the functions of finishing the protocol analysis of RT-NET, parameter configuration and maintenance, process data interaction, system diagnosis, human-computer interaction interface and the like are realized. As shown in fig. 2, the FPGA is connected to the host memory through the PCIE bus to implement data interaction between the two. Where HOST in fig. 2 is the master.

The PHY chip is used for completing data encoding, decoding and transceiving of the physical layer. The application of ethernet PHY chips in RT-NET needs to meet some requirements: the link loss response time of the chip is small by supporting 1000Mbit/s full duplex link.

The ZYNQ module comprises an FPGA chip with an ARM core; the FPGA chip is connected with a host memory through the PCIE bus, and the FPGA chip and the host memory perform data interaction through the PCIE bus. The FPGA chip with the ARM core can also be a ZYNQ chip. The ZYNQ module mainly realizes the control and communication functions of the RT-NET data link. The ZYNQ chip processor chip of the ZYNQ module can adopt XC7Z015-2CLG485I of ZYNQ7000 series of xilinx corporation. The PS system of the ZYNQ chip integrates two ARM Cortex-A9 processors, AMBA interconnection, an internal memory, an external memory interface and peripherals. The FPGA of the ZYNQ chip contains rich programmable logic units, DSP and internal ARM.

The overall scheme of the real-time network card based on the ZYNQ is shown in fig. 3, a host interacts with a ZYNQ module through PCIE, the ZYNQ module is connected with a PHY chip through an RMII interface, and the PHY chip is connected with a slave station through a network isolation transformer and an RJ45 interface access bus. The host machine carries out interaction of data frames through a PCIE data bus and a ZYNQ module, the ZYNQ module transmits the data frames to the PHY chip, the PHY chip converts the received RT-NET data frames into differential signals and sends the differential signals to the network, and the data frames are returned to the master station after the slave stations respond.

In an embodiment, as shown in fig. 4 and 5, a real-time network card board developed based on the technical solution provided by the present invention may have the following indexes, including:

the power supply requirement is as follows: the PCIe slot of the case supplies power;

a) the size of the board is as follows: the PCB size is 140mm X60 mm, the double-network-port real-time network card PCB and the size structure placement schematic diagram are shown in FIG. 1 and FIG. 2;

b) the fixed baffle needs to provide 2 sizes of half height and full height;

c) selecting the device type: all devices adopt industrial grade standards;

d) an FPGA manufacturer: XC7Z015-2CLG485I from XILINX;

e) other hardware specifications are shown in table 2 below;

f) the working temperature range of the product is as follows: -30 ℃ to 60 ℃;

main hardware parameters and interface metrics

The real-time network card single board mainly comprises a minimum system of ZYNQ7015+2 DDR3+ eMMC + QSPI FLASH, and is configured with abundant peripheral interfaces, wherein the minimum system comprises 1 PCIex2 interface, 2 paths of gigabit Ethernet interfaces, 1 path of UART serial interface, 1 path of SD card interface and 1 path of JTAG interface.

Fig. 6 and 7 show a hardware configuration diagram of the technical solution of the present invention.

The ZYNQ module and/or the ZYNQ chip provided by the invention can be shown in FIG. 8, the PS system of the chip integrates two ARM cortex-A9 processors,

an interconnect, an internal memory, an external memory interface, and a peripheral. The peripherals mainly comprise a USB bus interface, an Ethernet interface, an SD/SDIO interface, an I2C bus interface, a CAN bus interface, a UART interface, a GPIO and the like. The PS can run independently and start on power-up or reset.

The main parameters of the PS system part are as follows:

application processor based on ARM dual core cortex xa9, ARM-v7 architecture, up to 766MHz

2 CPU-shared based on CPU 32KB level 1 instruction and data cache, 512KB level 2 cache

Boot ROM on chip and 256KB RAM on chip

External memory interface supporting 16/32bitDDR2, DDR3 interfaces

Two gigabytes of real-time network card support: divergent-aggregate DMA, GMII, RGMII, SGMII interfaces

Two USB2.0 OTG interfaces, each supporting at most 12 nodes

Two CAN2.0B bus interfaces

Two SD card, SDIO, MMC compatible controllers

2 SPI, 2 UARTs, 2I 2C interfaces

4 groups of 32bit GPIOs, 54(32+22) as PS systems IO, 64 connected to PL

High bandwidth connection within PS and PS to PL

The main parameters of the PL logic section are as follows:

logic Cells 76K

Look-up table LUTs 46200

Flip-flops (flip-flops): 92400

-multiplier 18x25MACCs 160

-Block RAM：3.3Mb

-4-way high-speed GTP transceiver supporting PCIEGen2x2

2 AD converters that can measure on-chip voltage, temperature sensing and up to 17 external differential input channels, 1 MBPS.

The ZYNQ chip speed rating was-2, industrial grade, packaged as BGA484 with a 0.8mm pin pitch as shown in fig. 9.

The technical scheme of the invention is provided with two DDR3 SDRAM chips (1 GB in total), and the model is H5TQ4G63 AFR-PBI. The DDR3 SDRAM has a total bus width of 32 bits. The maximum operating speed of DDR3 SDRAM can reach 533MHz (data rate 1066 Mbps). The DDR3 memory system is directly connected to the memory interface of BANK 502 of the ZYNQ Processing System (PS). The specific configuration of DDR3 SDRAM is shown in fig. 10A.

The hardware design of DDR3 needs to strictly consider signal integrity, and the matching resistance/terminal resistance, routing impedance control, routing equal length control need to be fully considered when designing a circuit and a PCB pair, so that the high-speed stable work of DDR3 is ensured. The hardware connection of the DDR3 DRAM is shown in fig. 10B.

The schematic diagram of the DDR3 DRAM shown in fig. 10C, and the pin assignment diagram of the DDR3 DRAM shown in fig. 10D.

The device also comprises double-rate synchronous dynamic random access memories (DDR3 DRAM and DDR) which are respectively connected with the ZYNQ module and used for carrying out data interaction with the ZYNQ module. The synchronous dynamic random access memory comprises two synchronous dynamic random access memories; and an address line and a control line of the synchronous dynamic random access memory are respectively connected with the ZYNQ module. One of the synchronous dynamic random access memories and the ZYNQ module adopt a data transmission connection mode of 16 high bits of data; and the other synchronous dynamic random access memory and the ZYNQ module adopt a data transmission connection mode of 16 low bits of data.

The technical scheme of the invention is provided with a 256Mbit Quad-SPI Flash chip with the model of W25Q256FVEI, which uses the 3.3V CMOS voltage standard. Because of the non-volatile nature of QSPI FLASH, in use, it may act as a boot device for the system to store a boot image of the system. These images mainly include the bit files of the FPGA, the application codes of the ARM, and other user data files. QSPI FLASH are shown in fig. 11A.

QSPI FLASH are connected to GPIO ports of PS part BANK500 of ZYNQ chip, and the GPIO port function of these PS terminals needs to be configured as QSPI FLASH interface in system design. QSPI FLASH are connected as shown in FIG. 11B.

QSPI FLASH in FIG. 11C, and QSPI FLASH in FIG. 11D.

The technical scheme of the invention is provided with a large-capacity eMMC FLASH chip with the size of 8GB, the model is THGBMFG6C1LBAIL, the high-speed embedded type multi-media controller is supported by JEDEC e MFG6C1 MMC 1L 1 MMC 5.0 MMC 1L, which supports the HS-MMC interface of JEDEC, and supports the HS-MMC 5.0 standard of the HS-MMC, and the level of which supports the JEDEC of the JEDEC 5.0 standard of which supports the JEDEC, the HS-MMC, the JEC 5.0 standard of which supports the JEC 5.0 standard of the JEDEC, and the JEC 5, and the JEC 1, the level of which support the JEC 1V, the JEC 1, the level of which support the JEC 1, the JEC of which supports the JEDEC with a large capacity, the JEC of which is equipped type, the large capacity, the JEC 1, the JEC of which is equipped type, the large capacity, the one. The data width of the connection between the eMMC FLASH and the ZYNQ is 4 bits. Because of its large capacity and non-volatile nature, eMMC FLASH may be used as a system mass storage device, such as to store applications, system files, and other user data files. The specific model and related parameters of eMMC FLASH are shown in fig. 12A.

The eMMC FLASH is connected to a GPIO port of a PS part BANK501 of the ZYNQ chip, and the GPIO port function of the PS ends needs to be configured as an SD interface in system design. The hardware connection of the eMMC Flash is shown in fig. 12B.

A schematic diagram of the eMMC Flash shown in fig. 12C, and a schematic diagram of chip pin assignment of the eMMC Flash shown in fig. 12D.

The technical scheme of the invention provides active clocks for the PS system and the PL logic part respectively, so that the PS system and the PL logic can work independently.

Wherein, regarding the PS system clock source, the ZYNQ chip provides 33.333MHz clock input for the PS part through the X1 crystal oscillator. The input of the clock is connected to the pin of PS _ CLK _500 of BANK500 of the ZYNQ chip, the principle of which is shown in FIG. 13A.

The clock pin assignment of the PS system clock source is shown in fig. 13B.

Wherein, regarding PL system clock source, the technical scheme of the invention provides single-end 50MHz PL system clock source, and 3.3V power supply. The crystal outputs are connected to the global clock (MRCC) of FPGA BANK13, and this GCLK can be used to drive the user logic circuits within the FPGA, as shown in principle in figure 13C.

The clock pin assignment of the PL system clock source is shown in fig. 13D.

The technical scheme of the invention is provided with a UART-to-USB interface for debugging. The conversion chip adopts a USB-UART chip of Silicon Labs CP2102GM, the USB interface adopts a MINI USB interface, and the conversion chip can be connected to a USB port of a PC by a USB wire to carry out serial port data communication of the core board. The hardware connection mode of the USB to serial port is shown in fig. 14A.

The principle of USB to serial is shown in fig. 14B. The ZYNQ pin assignment for the UART-to-serial port is shown in fig. 14C.

The technical scheme of the invention reserves a JTAG interface for downloading the FPGA program or solidifying the program to the FLASH. In order to prevent the FPGA chip from being damaged by hot plugging, a protection diode is added on a JTAG signal to ensure that the voltage of the signal is in the range accepted by the FPGA, so that the damage of the FPGA is avoided. The principle is shown in fig. 15.

In one embodiment, the technical solution of the present invention has 2-way gigabit ethernet interfaces, wherein a 1-way ethernet interface is a connected PS system side, and the other 1-way ethernet interface is connected to a logical IO port of the PL. The gigabit ethernet interface connected to the PL side needs to be mounted to the AXI bus system of ZYNQ by program call IP.

The Ethernet chip adopts a KSZ9031RNX Ethernet PHY chip of Micrel company to provide network communication service. The ethernet PHY chip at the PS end is connected to the GPIO interface of the PS end BANK501 of ZYNQ. The Ethernet PHY chip on the PL side is connected to the IO of BANK 35. The KSZ9031RNX chip supports 10/100/1000Mbps network transmission rate and carries out data communication with the MAC layer of the Zynq7000 system through an RGMII interface. The KSZ9031RNX supports MDI/MDX self-adaptation, various speed self-adaptation and Master/Slave self-adaptation, and supports the register management of the PHY by the MDIO bus.

The KSZ9031RNX power-up will detect some specific IO level status to determine its own operation mode. Such as default setting information after the GPHY chip is powered on as shown in fig. 16.

When the network is connected to a gigabit Ethernet, ZYNQ and the data of the PHY chip KSZ9031RNX are communicated through an RGMII bus during data transmission, the transmission clock is 125Mhz, and the data are sampled at the rising edge and the falling edge of the clock.

When the network is connected to a hundred mega Ethernet, ZYNQ and the data transmission of the PHY chip KSZ9031RNX are communicated through an RMII bus, and the transmission clock is 25 Mhz. Data is sampled on both the rising and falling edges of the clock.

Fig. 17A shows a hardware connection manner of the 1-way ethernet PHY chip at the ZYNQ PS terminal. Fig. 17B is a schematic diagram of a 1-way ethernet PHY chip at the ZYNQ PS port. Fig. 17C is a diagram of PS-side gigabit ethernet pin assignment.

The hardware connection mode of the 1-path Ethernet PHY chip at the ZYNQ PL end is shown in FIG. 17D. FIG. 17E is a schematic diagram of a ZYNQ PL port 1 Ethernet PHY chip. Fig. 17F is a diagram illustrating PL side gigabit ethernet pin assignment.

The technical scheme of the invention provides an industrial-grade high-speed data transmission PCIe x4 interface, the external dimension of the PCIE card meets the electrical specification requirement of the PCIE card, and the PCIE card can be directly used on a PCIe slot of a common desktop.

The transmitting and receiving signals of the PCIe interface are directly connected with a GTP transceiver of the FPGA, the TX signals and RX signals of the 2 channels are connected to the FPGA in a differential signal mode, and the single-channel communication speed can reach 5G bit bandwidth. The PCIe reference clock is provided to the development board by the PCIe slot of the computer, and the reference clock frequency is 100 MHz.

Fig. 18A shows a hardware connection manner of the PCIe interface according to the technical solution of the present invention, in which a TX transmit signal and a reference clock CLK signal are connected in an AC-coupled mode. As shown in the PCIe x4 interface schematic diagram of fig. 18B. Fig. 18C shows a PCIE x4 interface FPGA pin assignment diagram.

The technical scheme of the invention comprises a Micro SD card interface to provide the function of accessing the SD card memory, and is used for storing a BOOT program of a ZYNQ chip, a Linux operating system kernel, a file system and other user data files.

The SDIO signal is connected to the IO signal of PS BANK501 of ZYNQ because VCCMIO of this BANK is set to 1.8V, but the data level of the SD card is 3.3V, here connected through a TXS02612 level shifter. The hardware connection of Zynq7000PS and the SD card connector is shown in FIG. 19A.

As shown in the schematic diagram of the SD card slot in fig. 19B. The pin assignment diagram of the SD card slot is shown in FIG. 19C.

The power supply input voltage of the technical scheme of the invention is DC12V, and power is supplied through PCIE. The real-time network card board is converted into four power supplies of +5V, +1.2V, +3.3V and 1.8V through a 1-path DC/DC power supply chip MP2303 and a 3-path DC/DC power supply chip MP 1482. The RT-NET power supply principle is shown in FIG. 20.

The size structure diagram of the PCIE real-time network card according to the technical solution of the present invention is shown in fig. 21.

The readable storage medium may be a computer storage medium or a communication medium. Communication media includes any medium that facilitates transfer of a computer program from one place to another. Computer storage media may be any available media that can be accessed by a general purpose or special purpose computer. For example, a readable storage medium is coupled to the processor such that the processor can read information from, and write information to, the readable storage medium. Of course, the readable storage medium may also be an integral part of the processor. The processor and the readable storage medium may reside in an Application Specific Integrated Circuits (ASIC). Additionally, the ASIC may reside in user equipment. Of course, the processor and the readable storage medium may also reside as discrete components in a communication device. The readable storage medium may be a read-only memory (ROM), a random-access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

The present invention also provides a program product comprising execution instructions stored in a readable storage medium. The at least one processor of the device may read the execution instructions from the readable storage medium, and the execution of the execution instructions by the at least one processor causes the device to implement the methods provided by the various embodiments described above.

In the above embodiments of the terminal or the server, it should be understood that the Processor may be a Central Processing Unit (CPU), other general-purpose processors, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of the hardware and software modules within the processor.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. a PCIE real-time network card based on FPGA module, is characterized in that, comprises:

ZYNQ module, including FPGA chip;

At least one PHY chip connected to the ZYNQ module, the PHY chip performs data interaction with the ZYNQ module through the MII and/or RMII interface, and the PHY chip is connected to an external interface;

The PCIE bus is connected to the ZYNQ module, and is used for transferring the received data to the ZYNQ module for processing.

2. the PCIE real-time network card based on FPGA module according to claim 1, is characterized in that,

The ZYNQ module includes an FPGA chip with an ARM core;

The FPGA chip is connected to the host memory through the PCIE bus, and the FPGA chip and the host memory perform data interaction through the PCIE bus.

3. the PCIE real-time network card based on FPGA module according to claim 2, is characterized in that,

The FPGA chip is connected with the clock circuit.

4. the PCIE real-time network card based on FPGA module according to claim 1, is characterized in that,

It also includes a double-rate synchronous dynamic random access memory, which is respectively connected with the ZYNQ module and used for data interaction with the ZYNQ module.

5. the PCIE real-time network card based on FPGA module according to claim 1, is characterized in that,

It also includes any one or more of a PCIex2 interface, a Gigabit Ethernet interface, a UART serial interface, an SD card interface and a JTAG interface respectively connected to the FPGA chip for data interaction.

6. the PCIE real-time network card based on FPGA module according to claim 4, is characterized in that,

The synchronous dynamic random access memory includes two;

The address line and the control line of the synchronous dynamic random access memory are respectively connected with the ZYNQ module.

7. the PCIE real-time network card based on FPGA module according to claim 6, is characterized in that,

One of the synchronous dynamic random access memory and the ZYNQ module adopts a data transmission connection mode of high 16-bit data;

Another synchronous dynamic random access memory and the ZYNQ module adopt a data transmission connection mode of the lower 16 bits of data.

8. the PCIE real-time network card based on FPGA module according to claim 1, is characterized in that,

The ZYNQ module is connected with a QSPI FLASH chip, and the QSPI FLASH chip is used to start the ZYNQ module and start mirroring.

9. the PCIE real-time network card based on FPGA module according to claim 1, is characterized in that,

The ZYNQ module is connected with an eMMC FLASH chip, and the eMMC FLASH chip is used to store any one or more of application programs, system files and data files.

10. the PCIE real-time network card based on FPGA module according to claim 3, is characterized in that,

The clock circuit is used to provide an active clock, and provide clock pulses to the ARM core and the FPGA chip respectively;

The ARM core and the FPGA chip work respectively based on the received active clock.