CN113488491A

CN113488491A - Contact hole forming method of CIS device

Info

Publication number: CN113488491A
Application number: CN202110640968.0A
Authority: CN
Inventors: 肖敬才; 孙少俊; 黄鹏
Original assignee: Hua Hong Semiconductor Wuxi Co Ltd
Current assignee: Hua Hong Semiconductor Wuxi Co Ltd
Priority date: 2021-06-09
Filing date: 2021-06-09
Publication date: 2021-10-08

Abstract

The present application discloses a method for forming a contact hole of a CIS device, and relates to the field of semiconductor manufacturing. The method for forming a contact hole of a CIS device includes providing a substrate on which the CIS device is fabricated, the surface of the substrate includes a transfer gate and a gate spacer, and a floating diffusion region is formed in the substrate; thickness, so that the distance between two adjacent gate spacers increases; a metal silicide barrier layer, an etch stop layer, and an interlayer dielectric layer are sequentially formed on the substrate; contact holes are defined by a photolithography process pattern; according to the contact hole pattern, self-aligned etching of the contact hole is performed to form a contact hole; the problem that the size of the pixel unit in the CIS device is reduced and the device structure is damaged due to the self-aligned etching process of the contact hole is solved; the optimization is achieved The contact hole self-alignment process of the CIS device improves the performance and reliability of the device.

Description

Contact hole forming method of CIS device

Technical Field

The application relates to the field of semiconductor manufacturing, in particular to a contact hole forming method of a CIS device.

Background

With the continuous development of the semiconductor industry, the density and performance of devices in the integrated circuit manufacturing process are also increasing. The CIS device is a semiconductor device capable of converting an optical signal into an electrical signal, and comprises a plurality of pixel units, wherein each pixel unit is composed of a photodiode and a MOS (metal oxide semiconductor) tube, and the photodiodes absorb light energy and convert the light energy into current.

The Floating Diffusion (FD) in the CIS device is used to collect electrons transmitted from the Photodiode (PD) and transmit the electrons to the Source Follower transistor (SF) in a high voltage form to turn the Source Follower transistor on.

At present, the common way to increase the FD voltage is to reduce the capacitance, i.e. reduce the ion implantation area, but this has an impact on the alignment precision of the FD contact hole. In the contact hole self-alignment process, the SIN in the grid side wall is not lost by utilizing the selection ratio of SIN/oxide, and only the surface of the FD area is exposed.

However, as the process node is continuously reduced, the size of the pixel unit is also correspondingly reduced, which results in the reduction of the distance between the gates 11, and when the etching stop layer 14 (CESL) is deposited, the CESL is combined together, so that the bottom thickness and the sidewall thickness of the CESL are different, as shown in fig. 1; this will cause the silicon nitride layer 18 in the gate sidewall to be damaged after the contact hole is self-aligned etched, as shown in fig. 2, which in turn increases the resistance of the contact hole and affects the RC delay of the device.

Disclosure of Invention

In order to solve the problems in the related art, the present application provides a method of forming a contact hole of a CIS device. The technical scheme is as follows:

in one aspect, an embodiment of the present application provides a method for forming a contact hole of a CIS device, including:

providing a substrate for manufacturing a CIS device, wherein the surface of the substrate comprises a transmission grid and a grid side wall, and a floating diffusion region is formed in the substrate;

the thickness of the grid side walls is reduced, so that the distance between every two adjacent grid side walls is increased;

sequentially forming a metal silicide barrier layer, an etching stop layer and an interlayer dielectric layer on a substrate;

defining a contact hole pattern through a photoetching process;

and according to the contact hole pattern, carrying out self-aligned etching on the contact hole to form the contact hole.

Optionally, the thickness of the gate side wall is reduced, and the distance between two adjacent gate side walls is increased, including:

opening a CIS device region through a photoetching process to protect a non-CIS device region;

the thickness of the silicon nitride layer in the grid side wall is reduced through a dry etching process, and the distance between two adjacent grid side walls is increased.

Optionally, the gate side wall is composed of an oxide layer and a silicon nitride layer;

in the grid side wall, the oxide layer is contacted with the transmission grid, and the silicon nitride layer is positioned on the outer side of the oxide layer.

Optionally, the metal silicide blocking layer is composed of an oxide layer and a silicon nitride layer;

forming a metal silicide barrier layer on a substrate, comprising:

depositing an oxide on the substrate to form an oxide layer;

and depositing silicon nitride on the oxide layer to form a silicon nitride layer.

Optionally, when the metal silicide blocking layer is composed of an oxide layer and a silicon nitride layer, performing self-aligned etching of the contact hole according to the pattern of the contact hole to form the contact hole, including:

removing the interlayer dielectric layer corresponding to the contact hole pattern by high-selectivity etching;

removing the etching barrier layer corresponding to the contact hole pattern and the silicon nitride layer in the metal silicide barrier layer through high-selectivity etching;

and over-etching the substrate, removing the oxide layer covering the surface of the substrate in the area corresponding to the contact hole pattern, and exposing the floating diffusion area.

Optionally, the material of the etching barrier layer is silicon nitride.

Optionally, the metal silicide blocking layer is composed of an oxide layer and a silicon-rich oxide layer;

forming a metal silicide barrier layer on a substrate, comprising:

depositing an oxide on the substrate to form an oxide layer;

and depositing a silicon-rich oxide on the oxide barrier layer to form a silicon-rich oxide layer.

Optionally, the metal silicide blocking layer is a silicon-rich oxide layer;

forming a metal silicide barrier layer on a substrate, comprising:

The technical scheme at least comprises the following advantages:

the thickness of the grid side wall is reduced by etching the grid side wall, the distance between two adjacent grid side walls is increased, and then a metal silicide barrier layer, an etching stop layer and an interlayer dielectric layer are formed, so that the etching stop layer is prevented from being combined before the two grid side walls, and then the contact hole is realized by utilizing self-aligned etching; the problem that the structure of the device is damaged in the self-alignment etching process of the contact hole due to the fact that the size of a pixel unit in the CIS device is reduced is solved; the contact hole self-alignment process of the CIS device is optimized, and the performance reliability of the CIS device is improved.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a partial schematic view after forming an etching barrier layer in the fabrication of a CIS device;

FIG. 2 is a partial schematic view of self-aligned etching of a contact hole in CIS device fabrication;

FIG. 3 is a flowchart illustrating a method for forming a contact hole of a CIS device according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram illustrating an embodiment of a method for forming a contact hole of a CIS device according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating an embodiment of a method for forming a contact hole of a CIS device according to the present disclosure;

FIG. 6 is a schematic diagram illustrating an embodiment of a method for forming a contact hole of a CIS device according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram illustrating an embodiment of a method for forming a contact hole of a CIS device according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram illustrating an embodiment of a method for forming a contact hole of a CIS device according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram illustrating an embodiment of a method for forming a contact hole of a CIS device according to the present invention;

wherein: 11, a grid electrode; 12, a metal silicide barrier/oxide layer; 13, a metal silicide barrier layer/silicon nitride layer; 14, etching the stop layer/silicon nitride layer; 15, interlayer dielectric layer/oxide layer; 16, an oxide layer; 17, a floating diffusion region; 18, a silicon nitride layer; 19, etching a region corresponding to the window by using the contact hole; 41, a substrate; 42, a transfer gate.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Referring to fig. 3, a flowchart of a method for forming a contact hole of a CIS device according to an embodiment of the present disclosure is shown, where the method includes at least the following steps:

step 101, providing a substrate for manufacturing a CIS device, wherein a transfer gate and a gate sidewall are formed on the surface of the substrate, and a floating diffusion region is formed in the substrate.

As shown in fig. 4, a transfer gate 42 and a gate sidewall are formed on the surface of the substrate 41, a floating diffusion region 17 is formed in the substrate 41, and the gate sidewall is composed of an oxide layer 16 and a silicon nitride layer 18.

And 102, reducing the thickness of the grid side walls, and increasing the distance between two adjacent grid side walls.

Before the thickness of the grid side wall is reduced, protecting a non-CIS device region on the substrate and exposing the CIS device region on the substrate; the silicon nitride layer 18 in the gate sidewall is etched by an etching process, so that the thickness of the gate sidewall is reduced, and the distance between two adjacent gate sidewalls is increased, as shown in fig. 5.

And 103, forming a metal silicide barrier layer, an etching stop layer and an interlayer dielectric layer on the substrate in sequence.

As shown in fig. 6, a metal silicide blocking layer, an etching stop layer 14, and an interlayer dielectric layer 15 are formed on the substrate 41, wherein the interlayer dielectric layer 15 is located above the etching stop layer 14, and the etching stop layer 14 is located above the metal silicide blocking layer.

At step 104, a contact hole pattern is defined by a photolithography process.

And coating photoresist on the surface of the interlayer dielectric layer, exposing by using a mask plate with a contact hole pattern, and forming the contact hole pattern in the photoresist layer after developing.

And 105, performing self-aligned etching on the contact hole according to the contact hole pattern to form the contact hole.

As shown in fig. 7, 8 and 9, the interlayer dielectric layer 15, the etching stop layer 14, the metal silicide barrier layer and the oxide layer on the surface of the substrate corresponding to the contact hole pattern are self-aligned etched; contact holes 20 are formed.

As shown in fig. 6, when the etching stop layer 14 is formed, the etching stop layer 14 is not bonded between two adjacent transmission gates 42, which does not result in an excessively large difference between the bottom thickness and the sidewall thickness of the etching stop layer 14, and during the self-aligned etching process, the etching speed of the bottom and the sidewall of the etching stop layer 14 is substantially the same, so that even if the contact hole pattern is shifted during the photolithography, i.e., is not completely aligned with the floating diffusion region in the substrate, the silicon nitride layer in the gate sidewall after the self-aligned etching can be prevented from being damaged.

In summary, in the contact hole forming method of the CIS device provided in the embodiment of the present application, the gate sidewalls are etched to reduce the thickness of the gate sidewalls, so that the distance between two adjacent gate sidewalls is increased, and then the metal silicide barrier layer, the etching stop layer, and the interlayer dielectric layer are formed to prevent the etching stop layer from being combined before the two gate sidewalls, and then the contact hole is realized by using self-aligned etching; the problem that the structure of the device is damaged in the self-alignment etching process of the contact hole due to the fact that the size of a pixel unit in the CIS device is reduced is solved; the contact hole self-alignment process of the CIS device is optimized, and the performance reliability of the CIS device is improved.

As shown in fig. 4, the gate sidewall is composed of an oxide layer 16 and a silicon nitride layer 18, in the gate sidewall, the oxide layer 16 is in contact with the transfer gate 42, and the silicon nitride layer 18 is located outside the oxide layer 16.

In an alternative embodiment based on the embodiment shown in fig. 3, the material of the etch stop layer is silicon nitride.

Optionally, the metal silicide blocking layer is composed of an oxide layer and a silicon nitride layer.

Optionally, the metal silicide blocking layer is formed of an oxide layer and a silicon-rich oxide layer.

Optionally, the metal silicide blocking layer is a silicon-rich oxide layer.

In one example, the metal silicide blocking layer is composed of an oxide layer and a silicon nitride layer, and the etching blocking layer is the silicon nitride layer:

forming a metal silicide barrier layer on a substrate can be achieved by the following steps:

step 201, depositing an oxide on a substrate to form an oxide layer.

Optionally, the thickness of the oxide in the metal silicide blocking layer is determined according to process parameters such as the height of the gate, the profile of the side wall, the distance between the gates and the like.

Step 202, depositing silicon nitride on the oxide layer to form a silicon nitride layer.

As shown in fig. 6, the metal silicide blocking layer is composed of an oxide layer 12 and a silicon nitride layer 13.

When the metal silicide barrier layer is composed of an oxide layer and a silicon nitride layer, and the etching barrier layer is the silicon nitride layer, self-alignment etching of the contact hole is carried out according to the pattern of the contact hole to form the contact hole, and the method can be realized by the following steps:

and 301, removing the interlayer dielectric layer corresponding to the contact hole pattern through high-selectivity etching.

When the interlayer dielectric layer 15 is etched, the etching stop layer 14 is used as a self-aligned barrier layer, and the etching amount of the interlayer dielectric layer 15 is ensured by using the high etching selection ratio of the interlayer dielectric layer/the etching stop layer.

The value of the etching selection ratio is determined according to the actual process requirement.

Because the interlayer dielectric layer 15 is an oxide layer, the etching stop layer 14 is a silicon nitride layer, and the high etching selection ratio of oxide/silicon nitride is selected, so that the etching rate of the oxide is greater than that of the silicon nitride; as shown in fig. 7, the interlayer dielectric layer 15 (oxide layer) corresponding to the contact hole pattern is removed.

And step 302, removing the etching barrier layer corresponding to the contact pattern and the silicon nitride layer in the metal silicide barrier layer by high-selectivity etching.

Because the etching stop layer 14 is a silicon nitride layer, the etching stop layer 14 and the silicon nitride layer 13 in the metal silicide barrier layer are removed in the same step of etching; the oxide layer 12 in the metal silicide barrier layer is used as a self-aligned barrier layer, and the etching amount of the etching stop layer 14 and the silicon nitride layer 13 in the metal silicide barrier layer is ensured by utilizing the high etching selection ratio of silicon nitride/oxide; as shown in fig. 8, the etch stop layer 14 (silicon nitride layer) and the silicon nitride layer 13 in the metal silicide blocking layer are removed.

Step 303, performing over-etching on the substrate, and removing the oxide layer covering the substrate in the region corresponding to the contact hole pattern to expose the floating diffusion region.

In the region corresponding to the contact hole pattern, after the silicon nitride layer in the interlayer dielectric layer, the etching stop layer and the metal silicide barrier layer is removed, an oxide layer is covered on the surface of the substrate, so that the substrate is over-etched to open the oxide layer at the bottom of the contact hole and expose the floating diffusion region 17, as shown in fig. 9.

In another example, the metal silicide blocking layer is composed of an oxide layer and a silicon-rich oxide layer:

step 401, depositing an oxide on the substrate to form an oxide layer.

Step 402, depositing a silicon-rich oxide on the oxide layer to form a silicon-rich oxide layer.

In another example, the metal silicide blocking layer is taken as a silicon-rich oxide layer as an example:

step 501, depositing a silicon-rich oxide on a substrate to form a silicon-rich oxide layer.

It should be noted that, when performing the self-aligned etching of the contact hole, a proper etching ratio or etching manner is selected according to the materials of the metal silicide barrier layer and the etching stop layer to form the contact hole.

The contact hole forming method of the CIS device provided by the embodiment of the application can be suitable for a small-size CIS device, and the small-size CIS device refers to a CIS device with a line width smaller than a conventional line width.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims

1. A method for forming a contact hole of a CIS device, wherein the method comprises:

A substrate on which a CIS device is fabricated is provided, the surface of the substrate includes a transfer gate and a gate spacer, and a floating diffusion region is formed in the substrate;

Decrease the thickness of the gate spacers to increase the distance between two adjacent gate spacers;

forming a metal silicide barrier layer, an etching stop layer, and an interlayer dielectric layer in sequence on the substrate;

The contact hole pattern is defined by a photolithography process;

According to the contact hole pattern, self-aligned etching of the contact hole is performed to form the contact hole.

2 . The method according to claim 1 , wherein the reducing the thickness of the gate spacers to increase the distance between two adjacent gate spacers comprises: 3 .

Through the photolithography process, the CIS device area is opened and the non-CIS device area is protected;

The thickness of the silicon nitride layer in the gate spacers is reduced by a dry etching process, so that the distance between two adjacent gate spacers is increased.

3. The method according to claim 1 or 2, wherein the gate spacer is composed of an oxide layer and a silicon nitride layer;

In the gate spacer, the oxide layer is in contact with the transfer gate, and the silicon nitride layer is located outside the oxide layer.

4. The method according to claim 1, wherein the metal silicide barrier layer is composed of an oxide layer and a silicon nitride layer;

Forming a metal silicide barrier layer on the substrate, comprising:

depositing oxide on the substrate to form the oxide layer;

Silicon nitride is deposited on the oxide layer to form the silicon nitride layer.

5. The method according to claim 1 or 4, wherein when the metal silicide barrier layer is composed of an oxide layer and a silicon nitride layer, the self-alignment of the contact hole is performed according to the contact hole pattern. Aligned etching to form contact holes, including:

Remove the interlayer dielectric layer corresponding to the contact hole pattern by highly selective etching;

Remove the etching barrier layer corresponding to the contact hole pattern and the silicon nitride layer in the metal silicide barrier layer by highly selective etching;

The substrate is over-etched, and the oxide layer covering the surface of the substrate in the region corresponding to the contact hole pattern is removed to expose the floating diffusion region.

6. The method according to any one of claims 1 to 5, wherein the material of the etching barrier layer is silicon nitride.

7. The method of claim 1, wherein the metal silicide barrier layer is composed of an oxide layer and a silicon-rich oxide layer;

Forming a metal silicide barrier layer on the substrate, comprising:

depositing oxide on the substrate to form the oxide layer;

A silicon-rich oxide is deposited on the oxide barrier layer to form the silicon-rich oxide layer.

8. The method of claim 1, wherein the metal silicide barrier layer is a silicon-rich oxide layer;

Forming a metal silicide barrier layer on the substrate, comprising: