CN113451244B - Double-sided heat dissipation MOSFET packaging structure and manufacturing method thereof - Google Patents
Double-sided heat dissipation MOSFET packaging structure and manufacturing method thereofInfo
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- CN113451244B CN113451244B CN202110859933.6A CN202110859933A CN113451244B CN 113451244 B CN113451244 B CN 113451244B CN 202110859933 A CN202110859933 A CN 202110859933A CN 113451244 B CN113451244 B CN 113451244B
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- H10W40/22—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/63—Vertical IGFETs
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- H10W40/226—
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- H10W40/228—
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- H10W74/01—
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- H10W74/129—
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Abstract
The structure comprises a chip main body, a first heat dissipation slide, a packaging colloid and a second heat dissipation slide. The chip body is turned over and is connected to the first heat dissipation slide, the source electrode pad and the grid electrode pad of the chip body are respectively communicated with the source electrode island and the grid electrode island of the first heat dissipation slide, the packaging colloid is formed on the first heat dissipation slide, the packaging colloid is provided with a first limiting hole communicated with the drain electrode layer and a second limiting hole outside the drain electrode layer and communicated with the drain electrode island of the first heat dissipation slide, the second heat dissipation slide is turned over and is attached to the packaging colloid, the first drain electrode column of the second heat dissipation slide is inserted into the first limiting hole to conduct the drain electrode layer and the second heat dissipation slide, and the second drain electrode column is inserted into the second limiting hole to conduct the drain electrode island of the second heat dissipation slide and the drain electrode island of the first heat dissipation slide. The double-sided heat dissipation MOSFET packaging structure has the effects of high heat capacity of the two sides of the device, low temperature rise under the impact of instantaneous high power and difficult overheating and burning of transistors in a chip.
Description
Technical Field
The invention relates to the technical field of packaging of power semiconductor devices, in particular to a double-sided heat dissipation MOSFET packaging structure and a manufacturing method thereof.
Background
The MOSFET is a short for Metal-Oxide-Semiconductor Field-Effect Transistor, which is a field effect transistor widely used in analog circuits and digital circuits. MOSFET chips are packaged as is required for general semiconductor packaging, and it is desirable that the smaller the package volume, i.e., the larger the area ratio of the chip in the package size, the better, when the chip package ratio reaches more than 0.64 (the package length and width are each within 1.2 times of the chip length and width), the Chip Size Package (CSP) can be called. The smaller the package size, the heat dissipation problem is a factor that needs to be solved immediately, and the problem of easy heat generation of the power semiconductor device is a factor that needs to be considered from time to time. In the prior art, a MOSFET package structure with double-sided heat dissipation or some design method for enhancing heat dissipation have been proposed.
Chinese patent publication No. CN108288607a discloses a Power MOSFET for enhancing heat dissipation and a design method thereof. In the structural design of MOSFET chip package, the chip package comprises a chip and a lead, wherein the lead is led out from the chip, a bonding pad of Source electrode is arranged on the front surface of the Power MOSFET, a bonding pad of Drain electrode is arranged on the bottom surface of the Power MOSFET, and the lead is electrically connected to the bonding pad of Source electrode and Drain electrode after being led out from the chip respectively, namely, the lead is led out from the chip of the Power MOSFET and is connected to the bonding pad of Source electrode. The pad area of the Source electrode on the front side of the Power MOSFET is matched with the pad area of the Drain electrode on the bottom side. However, if the related technology is adopted in the prior art, the wire is formed by a wire bonding process, the bonding needle of the wire bonding can only be bonded to the contact in the upward consistent direction, when the bottom surface of the Power MOSFET is arranged on the bonding pad of the Drain electrode, the upper surface of the bonding pad of the Source electrode arranged on the front surface of the Power MOSFET is positioned on the top surface of the package, the lower surface of the bonding pad of the Source electrode is positioned on the inner side of the package and faces downwards to the MOSFET chip, the bonding difficulty exists in the wire bonding of the bonding wire of the MOSFET chip, the bonding wire can not be turned 180 degrees to the bonding direction of the bonding needle when the bonding needle is not bonded in the prior art, in addition, the wire is used as the conduction of an electric signal, the too thin wire diameter is unfavorable for heat conduction and dissipation, so the surface of the package has the form of double-sided heat dissipation, the inside of the package lacks a good enough heat conduction mechanism, and the inside of the package can only rely on the epoxy resin layer with limited heat conduction capability. Further studies have found that the resistance of wire bond leaded MOSFET chip packages is typically above 0.3 mR.
Chinese patent publication No. CN111477683a discloses a package structure of a power MOSFET chip. The front side of the MOSFET chip comprises a grid electrode and a source electrode, the back side of the MOSFET chip comprises a drain electrode, a first conductor such as a metal molybdenum radiating fin is electrically connected with the drain electrode on the back side of the MOSFET chip in a face-to-face bonding mode, a second conductor such as a metal molybdenum radiating fin is electrically connected with the source electrode on the front side of the MOSFET chip in a face-to-face bonding mode through pressure welding packaging, a stress buffer area is arranged in the area of the source electrode occupying the front side of the MOSFET chip, and the edge of the second conductor contacted with the source electrode is positioned in the stress buffer area. The stress buffer area arranged on the front surface of the MOSFET chip is obviously impossible, the size of the circular outline of the stress buffer area is slightly smaller than the area occupied by the source electrode on the front surface of the MOSFET chip, because the chip is firstly arranged on the first conductor with the front surface facing upwards in the packaging process, and then the second conductor is arranged on the front surface of the upward chip, the front surface of the chip is adsorbed and contacted by the pick-and-place jig during the chip installation, the second conductor is directly pressed and contacted to the front surface of the chip during the second conductor installation, the front surface of the chip with the source electrode and the grid electrode circuit structure is directly stressed during the two operations, and the transistor structure of the inner part close to the front surface of the chip is easily damaged. In order to electrically connect the third conductor with the grid electrode on the front side of the MOSFET chip (the third conductor is a bonding wire formed by wire bonding in the prior art), the downward pressing of the second conductor needs to avoid the grid electrode connection area, so that the second conductor is difficult to uniformly press down on the front side of the chip, the local stress on the front side of the chip is easily caused by uneven stress, and the transistor close to the front side of the chip is easily damaged.
Chinese patent publication No. CN204464263U discloses a modularized MOSFET package structure. The chip I and the chip II are packaged in the packaging body, the front rewiring metal layer II is connected with the chip I and the chip II respectively through an insulating layer opening on the upper surface of the packaging body, the front rewiring metal layer I is located outside a vertical area of the front face of the chip I, a bonding pad is formed on part of the upper surfaces of the front rewiring metal layer I and the front rewiring metal layer II respectively, the bonding pad is exposed by the protection layer, the metal connector I and the front rewiring metal layer I are arranged on the same side of the chip I, the metal connector II is arranged below the chip I, and the back rewiring metal layer is connected with the metal connector I and the metal connector II. In the related art, a die-sealing technology for attaching the front surface of a chip and a process for depositing metal layers on both sides of a wafer are adopted, and the heat capacity of the extremely thin metal layer is insufficient to exert good packaging double-side heat dissipation. The front-side (also referred to as the processing surface or active surface, i.e., the IC processing surface in the semiconductor process) of the chip is too close to the bonding surface of the package structure, and the front-side of the chip is not protected as in the conventional package structure.
Disclosure of Invention
The invention provides a double-sided radiating MOSFET packaging structure, which has the effects of high heat capacity of the two sides of a device, low temperature rise under instant high-power impact and difficult overheating and burning of a transistor in a chip, and solves the problems that the conventional double-sided radiating structure is easy to generate lamination stress or insufficient heat capacity on the front side of the chip in the packaging process.
The second main objective of the present invention is to provide a method for manufacturing a dual-sided heat dissipation MOSFET package structure, which achieves the effect of reducing the manufacturing difficulty and the production process flow of the MOSFET chip semiconductor package under the dual-sided heat dissipation architecture.
The third objective of the present invention is to provide an electronic device, which can more quickly conduct out the heat in the MOSFET chip.
The main purpose of the invention is realized by the following technical scheme:
the utility model provides a two-sided radiating MOSFET packaging structure, include:
a chip body having a processing surface and an opposite back surface, a source electrode pad and a grid electrode pad are arranged on the treatment surface, and a drain electrode layer is arranged on the back surface;
The first heat dissipation slide is used for overturning and jointing the chip main body in a flip-chip combined mode, and the source electrode pad and the grid electrode pad of the chip main body are respectively communicated with a source electrode island and a grid electrode island of the first heat dissipation slide;
The first packaging colloid is formed on the first heat dissipation slide to seal the chip main body, and is provided with a first limit hole communicated with the drain electrode layer and a second limit hole outside the drain electrode layer, wherein the second limit hole is communicated with a drain electrode island of the first heat dissipation slide;
The second heat dissipation slide glass is arranged on the first packaging colloid in a flip-chip bonding mode, a first drain electrode column and a second drain electrode column which are mutually communicated are arranged on the inner surface of the second heat dissipation slide glass, the inner surface of the second heat dissipation slide glass is turned towards the first packaging colloid, the first drain electrode column is inserted into the first limiting hole to conduct the drain electrode layer and the second heat dissipation slide glass, the second drain electrode column is inserted into the second limiting hole to conduct the second heat dissipation slide glass and the drain electrode island of the first heat dissipation slide glass, and the second heat dissipation surface of the second heat dissipation slide glass is parallel to the packaging bottom surface.
By adopting the technical scheme, the second heat dissipation slide chip is arranged on the first packaging colloid in a flip-chip bonding mode, the second heat dissipation surface of the second heat dissipation slide chip is parallel to the packaging bottom surface, in one-time flip-chip bonding of the second heat dissipation slide chip, the first drain electrode column of the second heat dissipation slide chip is communicated with the drain electrode layer of the chip main body, and the second drain electrode column of the second heat dissipation slide chip is communicated with the drain electrode island of the first heat dissipation slide chip so as to replace bonding wires formed by wire bonding and have high heat capacity. The second heat dissipation carrier can be used as an external heat dissipation sheet in the packaging or/and testing process, can also be used as an internal heat dissipation sheet of a finished product of the packaging structure, has the advantages of short inside and outside, long inside and outside, and solves the problems that in the prior art, the internal heat dissipation sheet is directly adopted to easily generate lamination stress and difficult mold sealing and glue filling on the front surface of a chip, or the external heat dissipation sheet is directly adopted to have high internal heat resistance in the packaging.
The invention can be further configured in a preferred example that the connection of the source pad to the source island and the connection of the gate pad to the gate island comprise coplanar welding, the connection of the first drain post to the drain layer and the connection of the second drain post to the drain island comprise high-low level difference welding or tight fit of metal post plugging, and when the tight fit of metal post plugging is adopted, a layer of covering layer is formed on the upper surface of the first packaging colloid and the inner side walls and the bottoms of the holes of the first limiting hole and the second limiting hole, and the drain layer of the chip main body and the drain of the first heat dissipation slide are electrically interconnected in advance before the second heat dissipation slide is installed.
By adopting the above preferred technical features, the connection of the first drain pillar of the second heat dissipation slide to the drain layer of the chip main body and the connection of the second drain pillar of the second heat dissipation slide to the drain island of the first heat dissipation slide include high-low level difference welding or metal pillar plugging tight fit, and the first heat dissipation surface of the second heat dissipation slide may not need to be parallel to the package bottom surface, so that a larger package margin is allowed. When the tight fit of the metal column is adopted, the drain electrode layer of the chip main body and the drain electrode island of the first heat dissipation slide are electrically interconnected in advance by utilizing the metal covering layer before the second heat dissipation slide is installed, the second drain electrode column can be used for coarse positioning, the first drain electrode column can be used for fine positioning, and the second heat dissipation slide can be accurately positioned on the chip main body.
The invention can be further configured in a preferred example that the packaging structure further comprises a second packaging colloid formed on the first packaging colloid so as to encircle and fix the periphery of the second heat dissipation carrier.
By adopting the preferable technical characteristics, the second packaging colloid is formed on the first packaging colloid, so that the second heat dissipation carrier in the packaging process is converted into the built-in heat dissipation sheet of the finished product from the external heat dissipation sheet.
The present invention may be further configured in a preferred embodiment such that the second encapsulant and the second heat sink sheet together provide a flush package top surface parallel to the package bottom surface provided by the first heat sink sheet.
By adopting the above preferable technical characteristics, the second packaging colloid and the second heat dissipation carrier are utilized to jointly provide a flush packaging top surface and are mutually parallel to the packaging bottom surface, so that the first packaging colloid is not used as a part of the packaging bottom surface or the packaging top surface, the first packaging colloid is formed with wider packaging margin, and only the chip main body can be packaged by the first packaging colloid without bearing the requirement of packaging thickness. The thickness of the second heat dissipation carrier on the first packaging colloid can be used as readjustment of the packaging thickness of the finished product.
The present invention may be further configured in a preferred example such that the second heat sink slide is detachably separated from the first encapsulant prior to the second encapsulant being molded and cured.
By adopting the above preferable technical characteristics, the second heat dissipation slide is detachably separated from the first packaging colloid, so long as the second heat dissipation slide can be trimmed or replaced based on the test result before the second packaging colloid is solidified.
The present invention may be further configured in a preferred example such that the gate island is located at a corner notch of the source island and the drain island is located at a side of the source island away from the corner notch.
By adopting the above preferable technical characteristics, the grid island is positioned at the corner notch of the source island and the drain island is positioned at the side edge of the source island far away from the corner notch, the grid island and the drain island are separated by the source island in the bottom surface of the package, the areas of the drain island and the source island are larger than that of the grid island, and the electromagnetic field effect of the electron flow guided to the drain island on the grid island is greatly reduced. In addition, the grid electrode island, the drain electrode island and the source electrode island are provided with at least two corresponding sides with at least two sides adjacent to four peripheries of the bottom surface of the package, so that the stability of the package process for each island of the first heat dissipation carrier is facilitated.
The present invention may further be configured in a preferred example in that the package structure is a flip chip die size package (FC-CSP), the second heat dissipation surface of the second heat dissipation chip is larger than and covers any one of the drain layer of the chip body and the source island of the first heat dissipation chip, preferably, a plurality of the first drain pillars and a plurality of the second drain pillars are respectively arranged within individual array regions of the inner surface of the second heat dissipation chip, the length of the second drain pillars is larger than the length of the first drain pillars, and more preferably, the array pattern of the first drain pillars or/and the second drain pillars is defined as a hidden identification code of individual MOSFETs of the chip body.
By adopting the above preferable technical characteristics, the chip main body and the second heat dissipation carrier can be combined by the flip chip, and the package structure of the semiconductor power device obtains the form of flip chip size package (FC-CSP) with double-sided heat dissipation under the condition of reduced package size. Preferably, the plurality of first drain columns and the plurality of second drain columns are arranged in a partition array, the longer second drain columns can be used as coarse positioning for mounting the second heat dissipation slide, and the shorter first drain columns can be used as fine positioning for mounting the second heat dissipation slide, so that the operation heat of the chip is effectively transferred to the top surface of the package. More preferably, the pattern of the partitioned array of the plurality of first drain pillars and the plurality of second drain pillars is used as a hidden identification code of the individual MOSFETs of the chip body for identifying the manufacturing information of the chip body. For example, when the dimensions of the chip bodies are different, a majority of the first drain pillars can be bonded to the drain layer of the chip body, forming parallel conductor pillar connections, a minority of the first drain pillars cannot be bonded to the drain layer of the chip body, those first drain pillars can be identified as empty connections by electron flow distribution, or those first limiting holes can be determined as floating connections prior to mounting the second heat sink.
The main purpose of the invention is realized by the following technical scheme:
A manufacturing method of a double-sided heat dissipation MOSFET package structure is provided, a method for manufacturing a double-sided heat-dissipating MOSFET package structure as described above, optionally in combination with any of the above embodiments, the method comprising:
preparing an isolated chip main body, wherein the chip main body is provided with a processing surface and a corresponding back surface, a source electrode pad and a grid electrode pad are arranged on the processing surface, and a drain electrode layer is arranged on the back surface;
the chip main body is turned over in a flip chip bonding mode and is bonded on a first heat dissipation slide, so that the source electrode pad and the gate electrode pad of the chip main body are respectively communicated with a source electrode island and a gate electrode island of the first heat dissipation slide;
forming a first packaging colloid on the first heat dissipation slide to seal the chip main body, wherein the first packaging colloid is provided with a first limiting hole communicated with the drain electrode layer and a second limiting hole outside the drain electrode layer, and the second limiting hole is communicated with a drain electrode island of the first heat dissipation slide;
The first drain electrode column is inserted into the first limiting hole to conduct the drain electrode layer and the second heat dissipation slide, and meanwhile, the second drain electrode column is inserted into the second limiting hole to conduct the drain electrode island of the second heat dissipation slide and the drain electrode island of the first heat dissipation slide.
Through adopting above-mentioned technical scheme, utilize upset isolated second heat dissipation slide glass and make its flip-chip bonding mode set up on the first encapsulation colloid, the same encapsulation equipment that can share with the flip-chip bonding process of chip main part and need not the routing technology to the encapsulation top surface has good heat capacity, and a large amount of heat in taking out the chip, and the encapsulation process is simple and need not invest in professional equipment. In the packaging process, internal stress caused by pressing the processing surface (front surface) of the chip main body is avoided. The silicon perforation structure is not needed to be manufactured in the chip main body, and the effective working area of the transistor in the chip main body can be effectively enlarged.
The present invention in a preferred example may be further configured to:
During the mounting of the chip body, the connection of the source pad to the source island and the connection of the gate pad to the gate island comprise coplanar soldering; when the tight fit of the metal column plug is adopted, a metal covering layer is formed on the upper surface of the first packaging colloid and the inner side walls and the bottoms of the holes of the first limiting hole and the second limiting hole, and the drain electrode layer of the chip main body and the drain electrode island of the first cooling slide are electrically interconnected in advance before the second cooling slide is mounted;
Or/and, after the first packaging colloid is formed, the grid electrode island is positioned at a corner notch of the source electrode island, and the drain electrode island is positioned at the side edge of the source electrode island away from the corner notch;
Or/and, after the second heat dissipation slide is turned over and bonded, forming a second packaging colloid on the first packaging colloid to encircle and fix the periphery of the second heat dissipation slide;
Or/and, before the second packaging colloid is formed and solidified, the second heat dissipation slide is detachably separated relative to the first packaging colloid;
or/and, after forming the second packaging colloid, flattening and grinding the second packaging colloid and the second heat dissipation slide, wherein the second packaging colloid and the second heat dissipation slide jointly provide a flush packaging top surface which is parallel to the packaging bottom surface provided by the first heat dissipation slide;
Or/and, after the second encapsulant is formed, further comprising package singulation dicing to configure the package structure as a flip chip die size package (FC-CSP), the second heat dissipation surface of the second heat dissipation chip being simultaneously larger than and covering any of the drain layer of the chip body and the source island of the first heat dissipation chip.
The technical effects corresponding to the features described above can be achieved by using the above-described preferred technical features, by using the above-described corresponding structural features or combinations of possible structural features thereof.
The main purpose of the invention is realized by the following technical scheme:
An electronic device is provided, which comprises a printed circuit board and a double-sided radiating MOSFET packaging structure which is bonded on the printed circuit board and can be combined by any technical scheme, wherein the source electrode island, the gate electrode island and the drain electrode island which are positioned on the packaging bottom surface of the double-sided radiating MOSFET packaging structure are combined to the printed circuit board by solder, and the second radiating slide is exposed on the packaging top surface of the double-sided radiating MOSFET packaging structure.
By adopting the technical scheme, the electronic device can transfer out the heat of the MOSFET packaging structure more quickly, and the second heat dissipation slide is used for not only connecting the middle of the drain electrode but also being used for heat dissipation of the top surface of the packaging.
In summary, the technical solution of the present invention includes at least one of the following technical effects contributing to the prior art:
1. The double-sided heat dissipation MOSFET packaging structure can further reduce the internal resistance of the package, replaces the original source/grid upward wire bonding connection in the way that the chip flip chip is bonded on the second heat dissipation carrier, replaces the original drain downward installation in the way that the second heat dissipation carrier flip chip is bonded on the first packaging colloid, and reduces the resistance introduced in the DFN5 x 6 packaging mode to below 0.1mΩ, while the packaging resistance connected by wire bond in the prior art is generally above 0.3 mR.
2. In the prior art, the packaging of the MOSFET CHIP is that the front side of the CHIP faces upwards, the source electrode is led out through the internal lead wire of the wire, the lead wire is longer and thinner, the transistor close to the front side of the CHIP is relatively far away from the bottom carrier plate, so that heat conduction in the packaging is not ideal, CHIP operation heat is mainly conducted through the packaging bottom close to the back side of the CHIP and the substrate, the thermal resistance is large, and the heat of the upper surface and the lower surface of the packaging is unbalanced, so that regional hot spots are easily generated, and the CHIP is overheated and burnt.
3. In the prior art, the MOSFET package structure in DFN (Dual Flat No-Lead) package form usually has a plastic package material shell on the exposed surface, and the poor heat conduction is unfavorable for heat dissipation, and the upper and lower surfaces of the package in the example structure of the present application are metal carrier sheets, except for the heat conduction of the lower surface, the heat can be dissipated from the upper surface of the package to the air, the heat dissipation performance can be enhanced, the second heat dissipation slide of the application can be used as an external heat dissipation sheet in the stage of packaging and testing, the heat sink can be used as a built-in heat sink in the finished product stage, and has better adjustable heat dissipation capacity.
4. In the prior art, a radiating fin is arranged on the upper surface of a package of a MOSFET package structure in a DFN DUAL COOL package form, the radiating fin is added in a mode of pressing a layer of built-in metal sheet before plastic package, the built-in radiating fin is adhered to a carrier plate (or a chip) through an adhesive, the adhesive interface of the built-in radiating fin is affected by the pressure of the plastic package, the thickness and the gradient of the built-in radiating fin are difficult to control, and the heat conduction effect is not ideal. In the example structure of the invention, the drain electrode is led out by taking the first limiting hole and the second limiting hole as the through holes of the first packaging colloid, preferably, the metal layer is deposited firstly to serve as the conductive and heat-dissipation connection of the second heat-dissipation slide, the production steps are simpler, the method is compatible with the packaging process of the semiconductor, the large-scale production is easy, and the whole packaging thickness and the inclination of the second heat-dissipation slide on the packaging top surface are easy to control by combining the second packaging colloid and the top surface leveling process.
5. Under the condition of the same packaging outline dimension, the area of the packaged chip can be larger than that of the traditional DFN package, compared with the traditional CSP package, the plastic package material protection of the second radiating fin and the second packaging colloid is arranged on the top surface of the package in the example structure of the invention, the internal chip is not easy to be damaged physically, and the internal chip can be made into the standard packaging dimension, thereby being convenient for production.
6. The front and back sides of the device are jointly formed by the bottom metal substrate and the upper metal substrate, so that double-sided heat dissipation is realized, and compared with WLCSP (wafer level chip size package), the heat capacity of the device is higher, the temperature rise is lower under the instant high-power impact, and the device is not easy to overheat and burn due to the addition of the metal substrates.
7. The package in the example structure of the invention is connected with the first heat dissipation slide chip in a flip-chip bonding mode instead of the Source (Source) and the Gate (Gate) through the lead, and is connected with the Drain (Drain) through the lead, but is connected with the first heat dissipation slide chip in a flip-chip bonding mode by the second heat dissipation slide chip, so that the signal transmission path is short, the delay is small, the inductance is low, and the work of the high-frequency device is facilitated.
Drawings
FIG. 1 is a schematic cross-sectional view of a dual-sided heat-dissipating MOSFET package according to some preferred embodiments of the present invention;
FIG. 2 is a schematic diagram of a bottom surface of a dual-sided heat-dissipating MOSFET package according to some embodiments of the present invention;
FIG. 3 is a schematic diagram of a top surface of a dual-sided heat-dissipating MOSFET package according to some embodiments of the present invention;
Fig. 4 is a schematic cross-sectional view illustrating flip-chip bonding of a chip body and bonding the flip-chip body to a first heat sink in a MOSFET packaging method according to some preferred embodiments of the invention;
fig. 5 is a schematic cross-sectional view of a first encapsulant formed on a first heat spreader according to a MOSFET packaging method according to some preferred embodiments of the present invention;
fig. 6 is a schematic cross-sectional view illustrating a first molding compound having a first limiting hole and a second limiting hole in a MOSFET package method according to some preferred embodiments of the invention;
FIG. 7 is a schematic cross-sectional view of a flip-chip discrete second heat spreader on a first encapsulant in a MOSFET packaging method according to some embodiments of the present invention;
fig. 8 is a schematic cross-sectional view illustrating a flip-chip bonding method for disposing a second heat spreader on a first encapsulant in a MOSFET package method according to some preferred embodiments of the present invention;
FIG. 9 is a schematic cross-sectional view of a second encapsulant formed on a first encapsulant in a MOSFET packaging method according to some preferred embodiments of the present invention;
FIG. 10 is a schematic cross-sectional view of a dual-sided heat-dissipating MOSFET package according to other preferred embodiments of the present invention;
FIG. 11 is a schematic cross-sectional view illustrating a metal cap layer formed on a first encapsulant after a limiting hole is formed in a dual-sided heat dissipation MOSFET packaging method according to another preferred embodiment of the present invention;
fig. 12 is a schematic cross-sectional view of a MOSFET package with dual-sided heat dissipation according to another preferred embodiment of the invention, wherein a metal cover layer is formed and then a separate second heat dissipation carrier is flipped over the first encapsulant.
Reference numerals 10, chip body, 11, treatment surface, 12, back side, 13, source pad, 14, gate pad, 15, drain layer, 20, first heat dissipation carrier, 21, source island, 21A, corner notch, 21B, side, 22, gate island, 23, drain island, 30, first encapsulant, 31, first spacing hole, 32, second spacing hole, 40, second heat dissipation carrier, 41, first drain post, 42, second drain post, 43, first heat dissipation surface, 44, second heat dissipation surface, 50, second encapsulant, 51, package top, 60, solder, 70, metal cover layer.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only examples for understanding a part of the inventive concept of the present invention, and are not representative of all embodiments, nor are they to be construed as the only embodiments. All other embodiments, based on the embodiments of the present invention, which are obtained by those of ordinary skill in the art under the understanding of the inventive concept of the present invention, are within the scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear are referred to in the embodiments of the present invention), the directional indications are merely used to explain the relative positional relationship, movement conditions, and the like between the components in a specific posture, and if the specific posture is changed, the directional indications are correspondingly changed. In order to facilitate understanding of the technical scheme of the present invention, the following describes and explains the double-sided heat dissipation MOSFET package structure and the manufacturing method thereof in further detail, but is not taken as a limitation of the protection scope of the present invention.
The term "flip-chip bonding" as used herein refers to an article flip-chip bondable by a flip-chip bonding machine, which may be a chip or a heat sink, with its processing surface facing up during manufacture and its processing surface facing down during mounting. If the chip is a chip, the processing surface is a device forming surface, and if the chip is a radiating fin, the processing surface is a surface provided with a heat conducting column. For example, in the present example, the processing surface 11 of the chip body 10 faces upward to manufacture a transistor or the like in the semiconductor manufacturing, and the processing surface 11 of the chip body 10 faces downward to be bonded in the package mounting of the chip. The second heat sink 40 is manufactured with the inner surface of the second heat sink 40 facing upward to provide the drain posts 41, 42, and with the package mounting of the second heat sink 40 with the inner surface of the second heat sink 40 facing downward.
The term "heat dissipation carrier sheet" in the specification refers to a heat dissipation exposed area of a certain heat dissipation object corresponding to a package surface above 60%, for example, a occupation area of the first heat dissipation carrier sheet 20 on a package bottom surface above 60%, specifically above 69.4% (as shown in fig. 2), usually not more than 100%, and a occupation area of the second heat dissipation carrier sheet 40 on a package top surface above 60%, specifically above 69.4% (as shown in fig. 3), usually not more than 100%.
The drawings include portions common to many embodiments, and portions having differences or differences in the modified embodiments are described in a text manner. Thus, based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and determine whether individual features or any combination of several features described below can be characterized in the same embodiment or whether features mutually exclusive in technical essence can be characterized only in different variant embodiments.
Fig. 1 is a schematic cross-sectional view of a dual-sided heat dissipation MOSFET package according to some preferred embodiments of the invention, fig. 2 is a schematic bottom-side view of the dual-sided heat dissipation MOSFET package, and fig. 3 is a schematic top-side view of the dual-sided heat dissipation MOSFET package. Referring to fig. 1 to 3, some preferred embodiments of the present invention provide a dual-sided heat dissipation MOSFET package structure, which includes a chip body 10, a first heat dissipation carrier 20 disposed below the chip body 10, a first encapsulant 30 sealing the chip body 10, and a second heat dissipation carrier 40 disposed on the first encapsulant 30.
The chip body 10 has a processing surface 11 and an opposite back surface 12, the processing surface 11 having a source pad 13 and a gate pad 14 disposed thereon, and the back surface 12 having a drain layer 15 disposed thereon. The chip body 10 is provided with a transistor (not shown), and the base material of the chip body 10 is semiconductor, specifically silicon, and may further include SIC, gaN, ga 2O3, siGe, gaAs, or any other semiconductor material, or other group III-V or II-VI compounds. In the example, the processing surface 11 is a surface of the semiconductor process that forms the device, the back surface 12 is a surface opposite to the processing surface 11, the source pad 13 and the gate pad 14 are usually made of metal, the drain layer 15 may also be made of metal, preferably aluminum or other conductive metal, and the source pad 13, the gate pad 14 and the drain layer 15 are all manufactured in a wafer level by a semiconductor manufacturing process and are diced to form individual chip bodies 10. The source pad 13 is electrically connected to the drain layer 15 by applying an electrical bias to the gate pad 14 to form a gate field effect.
The first heat sink 20 is used for flip-chip bonding of the chip body 10, and the source pad 13 and the gate pad 14 of the chip body 10 are respectively connected to the source island 21 and the gate island 22 of the first heat sink 20. Bonding of the pad to the island may be achieved in particular by means of solder 60, such as bumps or balls. The flip-chip bonding method makes the processing surface 11 of the chip body 10 face the first heat dissipation chip 20. In an example, the first heat spreader 20 further includes a drain island 23, and an example distribution of the source island 21, the gate island 22, and the drain island 23 is shown in fig. 2. In area comparison, source island 21 is larger than drain island 23, and drain island 23 is larger than gate island 22. The source islands 21 are spaced between the drain islands 23 and the gate islands 22. The first heat sink 20 is made of metal with good heat conduction, typically copper, iron or alloy thereof. The lower surface of the first heat sink 20 provides the package floor. In an example, the thickness of the first heat dissipation carrier 20 is 8-30% of the total packaging thickness, and the total packaging thickness of the MOSFET packaging structure is about 200-700 μm (micrometers).
The first encapsulant 30 is formed on the first heat sink 20 to seal the chip body 10, and the first encapsulant 30 is provided with a first limiting hole 31 communicating to the drain layer 15 and a second limiting hole 32 outside the drain layer 15, and the second limiting hole 32 communicates to the drain island 23 of the first heat sink 20. Typically, the first encapsulant 30 is a thermally cured insulating material and is molded. The first limiting hole 31 and the second limiting hole 32 may be formed by etching or laser after the first molding compound 30 is molded, or may be formed during the molding compound 30.
The second heat dissipation carrier 40 is disposed on the first encapsulant 30 in a flip-chip bonding manner, a first drain post 41 and a second drain post 42 that are in conduction with each other are disposed on an inner surface of the second heat dissipation carrier 40, the inner surface of the second heat dissipation carrier 40 is turned towards the first encapsulant 30, the first drain post 41 is inserted into the first limiting hole 31 to conduct the drain layer 15 and the second heat dissipation carrier 40, and the second drain post 42 is inserted into the second limiting hole 32 to conduct the second heat dissipation carrier 40 and the drain island 23 of the first heat dissipation carrier 20, and a second heat dissipation surface 44 of the second heat dissipation carrier 40 is parallel to the package bottom. The bond of the post to the pad may be achieved in particular by means of a solder 60, such as a bump or a ball. The second heat sink 40 is made of a metal material with good heat conduction, typically copper, iron or an alloy thereof. The upper surface of the second heat sink sheet 40 (second heat sink surface 44) provides part or all of the package top surface 51. Specifically, referring to fig. 7, the second heat dissipation carrier 40 has a first heat dissipation surface 43 in the packaging process, which is the same as the back surface 12 of the chip body 10, and has the applicability to be mounted by the same flip-chip bonding machine (flip-chip bonder). In an example, the thickness of the main body layer of the second heat dissipation carrier 40 is 5-20% of the total package thickness.
The principle of the above embodiment is that the second heat dissipation carrier 40 is disposed on the first package colloid 30 by flip-chip bonding, and the second heat dissipation surface 44 of the second heat dissipation carrier 40 is parallel to the package bottom surface, in one flip-chip bonding of the second heat dissipation carrier 40, the first drain post 41 of the second heat dissipation carrier 40 conducts the drain layer 15 of the chip main body 10, and the second drain post 42 of the second heat dissipation carrier 40 conducts the drain island 23 of the first heat dissipation carrier 20 to replace the bonding wire formed by wire bonding and has high heat capacity. The second heat dissipation carrier 40 can be used as an external heat dissipation sheet in the packaging or/and testing process, and can also be used as an internal heat dissipation sheet of a finished product of the packaging structure, so that the heat dissipation sheet has the advantages of being short in inside and outside, long in inside and outside, and solving the problems that the prior art directly adopts the internal heat dissipation sheet to easily generate lamination stress and difficult mold sealing and glue filling on the front surface of a chip, or directly adopts the external heat dissipation sheet to have high internal heat resistance in the packaging. In the semiconductor packaging process, the upper surface of the first packaging colloid 30 may not be required to be parallel to the bottom surface of the package, or the first heat dissipation surface 43 of the second heat dissipation carrier 40 may not be required to be parallel to the bottom surface of the package. In addition, since the first drain post 41 is inserted into the first limiting hole 3 and the second drain post 42 is inserted into the second limiting hole 32, the internal stress forming the second heat dissipation surface 44 will not cause the peeling of the second heat dissipation carrier 40.
In a preferred example, referring to fig. 1, the connection of the source pad 13 to the source island 21 and the connection of the gate pad 14 to the gate island 22 comprise coplanar welds, referring again to fig. 1, the connection of the first drain pillar 41 to the drain layer 15 and the connection of the second drain pillar 42 to the drain island 23 comprise high-low level difference welds, or referring again to fig. 10, the connection of the first drain pillar 41 to the drain layer 15 and the connection of the second drain pillar 42 to the drain island 23 are metal stud-mating tight fits. When the metal pillar is soldered with the pillar bottom and the hole bottom by solder 60, the drain layer 15 of the chip body 10 and the drain island 23 of the first heat sink 20 are not electrically interconnected before the second heat sink 40 is mounted. After mounting the second heat sink 40, the connection of the first drain pillar 41 of the second heat sink 40 to the drain layer 15 of the chip body 10 and the second drain pillar 42 of the second heat sink 40 to the drain island 23 of the first heat sink 20 may not need to be parallel to the package bottom surface, allowing for a larger package margin. The longer second drain post 42 may be positioned as a coarse location, the shorter first drain post 41 may be positioned as a fine location, and the second heat sink 40 may be positioned precisely on the chip body 10. The conversion of the first heat dissipation surface 43 of the second heat dissipation slide 40 into the second heat dissipation surface 44 can be achieved by planarization grinding.
In a preferred example, referring to fig. 1 again, the package structure further includes a second encapsulant 50 formed on the first encapsulant 30 to surround and fix the periphery of the second heat sink 40. The second encapsulant 50 is formed on the first encapsulant 30, so that the second heat sink 40 in the packaging process is converted from an external heat sink to an internal heat sink of the finished product. In addition to restricting the movement of the second heat dissipation carrier 40, the second encapsulant 50 has a balancing function of adjusting the thermal expansion coefficients of the upper and lower layers of the package structure in a preferred example, for example, when the lower half of the package structure is thermally expanded to a greater extent than the upper half, the second encapsulant 50 is made of or made of a material or a material with a greater thermal expansion coefficient, so as to achieve the balancing of the thermal expansion coefficients of the upper and lower layers of the package product.
In a preferred embodiment, referring again to fig. 1, the second encapsulant 50 and the second heat sink 40 together provide a flush package top surface 51 parallel to the package bottom surface provided by the first heat sink 20. The second encapsulant 50 and the second heat sink 40 together provide a flush top surface 51 parallel to the bottom surface, so that the first encapsulant 30 is not used as a part of the bottom surface nor as a part of the top surface 51, the first encapsulant 30 is formed with a wider package margin, and the first encapsulant 30 only needs to encapsulate the chip main body 10 and does not bear the requirement of package thickness. The thickness of the second heat spreader 40 on the first encapsulant 30 can be readjusted as the final package thickness.
In a preferred embodiment, referring again to fig. 1 and 7, the second heat sink 40 is detachably separated from the first encapsulant 30 before the second encapsulant 50 is molded and cured. The second heat sink slide 40 is detachably separated from the first encapsulant 30, so long as the second heat sink slide 40 can be trimmed or replaced based on the test results before the second encapsulant 50 is cured.
In a preferred example, referring again to fig. 1 and 2, the gate island 22 is located at a corner notch 21A of the source island 21, and the drain island 23 is located at a side 21B of the source island 21 away from the corner notch 21A. The gate island 22 and the drain island 23 are separated by the source island 21 in the bottom surface of the package by the gate island 22 being located at the corner notch 21A of the source island 21 and the drain island 23 being located at the side 21B of the source island 21 away from the corner notch 21A, and the drain island 23 and the source island 21 have a larger area than the gate island 22, so that the electromagnetic field effect of the electron flow guided to the drain island 23 on the gate island 22 is greatly reduced. In addition, the gate island 22, the drain island 23 and the source island 21 all have at least two sides 21B adjacent to at least two corresponding sides of four peripheral edges of the bottom surface of the package, which is beneficial to the stability of the package process for each island of the first heat spreader 20.
In a preferred example, the package structure is a flip chip die size package (FC-CSP), the second heat dissipation surface 44 of the second heat dissipation chip 40 is larger than and covers any one of the drain layer 15 of the chip body 10 and the source island 21 of the first heat dissipation chip 20 at the same time, preferably, a plurality of the first drain pillars 41 and a plurality of the second drain pillars 42 are respectively arranged in individual array regions of the inner surface of the second heat dissipation chip 40, the length of the second drain pillars 42 is larger than the length of the first drain pillars 41, and more preferably, the array pattern of the first drain pillars 41 or/and the second drain pillars 42 is defined as a hidden identification code of individual MOSFETs of the chip body 10. The chip body 10 and the second heat sink 40 can be bonded by flip chip, and the package structure of the semiconductor power device can be in the form of flip chip size package (FC-CSP) with double-sided heat dissipation under the reduced package size. Preferably, with the partitioned array configuration of the plurality of first drain pillars 41 and the plurality of second drain pillars 42, the longer second drain pillars 42 can be used as a rough location for mounting the second heat sink 40, and the shorter first drain pillars 41 can be used as a fine location for mounting the second heat sink 40, so as to effectively transfer the chip operation heat to the package top surface 51. More preferably, the pattern of the partition array arrangement of the plurality of first drain pillars 41 and the plurality of second drain pillars 42 is used as a hidden identification code of the individual MOSFETs of the chip body 10 for identifying the manufacturing information of the chip body 10. For example, when the dimensions of the chip body 10 are different, a large portion of the first drain pillars 41 can be bonded to the drain layer 15 of the chip body 10 to form parallel conductor pillar connections, a small portion of the first drain pillars 41 cannot be bonded to the drain layer 15 of the chip body 10, and those first drain pillars 41 can be identified as empty connections by electron flow distribution, or those first limiting holes 31 can be determined as empty connections before the second heat sink 40 is mounted.
Referring to fig. 4 to 9 and fig. 1, the present invention further provides a method for manufacturing a dual-sided heat dissipation MOSFET package structure, which is used for manufacturing the dual-sided heat dissipation MOSFET package structure according to any of the above-mentioned technical schemes, and the method comprises the following steps.
Referring to fig. 4, an isolated chip body 10 is prepared, specifically, formed by dicing a wafer, the chip body 10 has a processing surface 11 and a corresponding back surface 12, the processing surface 11 is provided with a source pad 13 and a gate pad 14, and the back surface 12 is provided with a drain layer 15.
Referring to fig. 4 again, the chip body 10 is flipped over and bonded to the first heat spreader 20 by flip-chip bonding, for example, using solder 60 to electrically connect the source pad 13 and the gate pad 14 of the chip body 10 to the source island 21 and the gate island 22 of the first heat spreader 20, respectively. The first heat sink 20 is a unit in the form of a motherboard in this step.
Referring to fig. 5, a first encapsulant 30 is formed on the first heat spreader 20 in a molding manner to encapsulate the chip body 10, and the first encapsulant 30 may be a flat mold covering a motherboard including a plurality of first heat spreader 20. Thereafter or simultaneously, referring to fig. 6, the first encapsulant 30 is provided with a first limiting hole 31 communicated to the drain layer 15 and a second limiting hole 32 outside the drain layer 15, and the second limiting hole 32 is communicated to the drain island 23 of the first heat dissipation carrier 20. After the first limiting hole 31 and the second limiting hole 32 are formed in the first packaging colloid 30, a mask laser hole opening mode can be adopted to burn out the plastic packaging material at the position where the through hole is needed, so that the chip Drain electrode contact hole and the contact hole of the bottom metal substrate are exposed. In a preferred example, but not limited thereto, the first encapsulant 30 is shaped to be pre-cured, and a post-curing process is further performed on the first encapsulant 30, either after the second heat sink 40 is mounted, or during the formation of the second encapsulant 50.
Referring to fig. 7 and 8, a flip-chip bonding machine is used to flip a separate second heat dissipation carrier 40 and a flip-chip bonding method is disposed on the first encapsulant 30, a first drain post 41 and a second drain post 42 that are mutually conductive are disposed on an inner surface of the second heat dissipation carrier 40, and in a flip-chip and bonding process (as shown in fig. 7), the first drain post 41 is inserted into the first limiting hole 31 to conduct the drain layer 15 and the second heat dissipation carrier 40, and meanwhile, the second drain post 42 is inserted into the second limiting hole 32 to conduct the second heat dissipation carrier 40 and the drain island 23 of the first heat dissipation carrier 20. The connection of the post to the bottom of the hole may be accomplished in the example using solder 60. Finally, packaging and separating cutting are carried out to manufacture the discrete packaging structure of the semiconductor power device shown in fig. 1.
The basic principle of the embodiment is that the second heat dissipation carrier 40 is turned over and separated and the flip-chip bonding mode is set on the first packaging colloid 30, the packaging equipment can be shared and the wire bonding process is not needed as the flip-chip bonding process of the chip main body 10, the packaging top surface 51 has good heat capacity, a large amount of heat in the chip is carried out, and the packaging process is simple and special equipment investment is not needed. During the packaging process, internal stress is not caused by pressing the processing surface 11 (front surface) of the chip body 10. The silicon perforation structure is not required to be manufactured in the chip main body 10, and the effective working area of the transistor in the chip main body 10 can be effectively enlarged.
In a preferred example, referring again to fig. 4, the connection of the source pad 13 to the source island 21 and the connection of the gate pad 14 to the gate island 22 during the mounting of the chip body 10 include coplanar welds, and referring again to fig. 7 and 8, the connection of the first drain post 41 to the drain layer 15 and the connection of the second drain post 42 to the drain island 23 during the mounting of the second heat sink 40 include high-low level-difference welds.
In a preferred example, referring to fig. 9, after the second heat sink 40 is turned over and bonded, a second encapsulant 50 is formed on the first encapsulant 30 to enclose and fix the periphery of the second heat sink 40, and before the second encapsulant 50 is formed and cured, the second heat sink 40 is detachably separated from the first encapsulant 30. The material of the second encapsulant 50 may include a thermosetting epoxy resin.
In a preferred embodiment, referring again to fig. 1, after forming the second encapsulant 50, the method further comprises planarizing and polishing the second encapsulant 50 and the second heat spreader 40, wherein the second encapsulant 50 and the second heat spreader 40 together provide a top surface 51 of the package that is flush with the bottom surface of the package provided by the first heat spreader 20.
In a preferred example, after the second encapsulant 50 is formed, package singulation dicing is further included to configure the package structure as a flip chip package (FC-CSP), the second heat dissipation surface 44 of the second heat dissipation chip 40 being larger than and covering both the drain layer 15 of the chip body 10 and any of the source islands 21 of the first heat dissipation chip 20.
Fig. 10 is a schematic cross-sectional view of a dual-sided heat-dissipating MOSFET package according to other preferred embodiments of the invention. The double-sided heat dissipation MOSFET packaging structure comprises a chip main body 10, a first heat dissipation slide 20 positioned below the chip main body 10, a first packaging colloid 30 for sealing the chip main body 10 and a second heat dissipation slide 40 arranged on the first packaging colloid 30.
Referring to fig. 10, the chip body 10 has a processing surface 11 and an opposite back surface 12, the processing surface 11 is provided with a source pad 13 and a gate pad 14, and the back surface 12 is provided with a drain layer 15. The first heat sink 20 is used for flip-chip bonding of the chip body 10, and the source pad 13 and the gate pad 14 of the chip body 10 are respectively connected to the source island 21 and the gate island 22 of the first heat sink 20. The first encapsulant 30 is formed on the first heat sink 20 to seal the chip body 10, and the first encapsulant 30 is provided with a first limiting hole 31 communicating to the drain layer 15 and a second limiting hole 32 outside the drain layer 15, and the second limiting hole 32 communicates to the drain island 23 of the first heat sink 20. The second heat dissipation carrier 40 is disposed on the first encapsulant 30 in a flip-chip bonding manner, a first drain post 41 and a second drain post 42 that are in conduction with each other are disposed on an inner surface of the second heat dissipation carrier 40, the inner surface of the second heat dissipation carrier 40 is turned towards the first encapsulant 30, the first drain post 41 is inserted into the first limiting hole 31 to conduct the drain layer 15 and the second heat dissipation carrier 40, and the second drain post 42 is inserted into the second limiting hole 32 to conduct the second heat dissipation carrier 40 and the drain island 23 of the first heat dissipation carrier 20, and a second heat dissipation surface 44 of the second heat dissipation carrier 40 is parallel to the package bottom.
The difference between the embodiment shown in fig. 10 and the embodiment shown in fig. 1 is that the connection of the first drain pillar 41 to the drain layer 15 and the connection of the second drain pillar 42 to the drain island 23 are made by metal pillar plugging tight fit, and a metal cover layer 70 is formed on the upper surface of the first encapsulant 30 and the inner walls and bottoms of the first and second limiting holes 31 and 32, so that the drain layer 15 of the chip body 10 and the drain island 23 of the first heat sink 20 are electrically interconnected in advance before the second heat sink 40 is mounted. With a tight fit of the metal posts, the first heat dissipation surface 43 of the second heat dissipation chip 40 may not need to be parallel to the package bottom surface, allowing for a larger package margin. When the metal post is inserted and tightly fitted, the metal cover layer 70 is used to electrically interconnect the drain layer 15 of the chip body 10 and the drain island 23 of the first heat sink 40 in advance before the second heat sink 40 is mounted, the second drain post 42 can be positioned as a thick portion, the first drain post 41 can be positioned as a thin portion, and the second heat sink 40 can be positioned on the chip body 10 accurately. As long as the first drain post 41 is inserted into the hole wall of the first limiting hole 31, even if the bottom of the first limiting hole 31 is not pressed, the electrical connection between the second heat sink 40 and the drain layer 15 of the chip body 10 can be achieved.
The resistance introduced by the package structure in the example of the invention under the DFN5 x 6 package structure can be reduced to below 0.1mΩ, while the package resistance of the traditional wire bonding is generally above 0.3 mR. Based on the utilization of the second heat-dissipating carrier 40, the high-current capability of the device is greatly improved by more than 20% compared with the traditional packaging of the same chip.
Referring to fig. 11 and 12, the present invention also provides a method for manufacturing the MOSFET package structure with dual-sided heat dissipation, which includes the steps shown in fig. 4 to 6 until the first limiting hole 31 and the second limiting hole 32 are formed on the upper surface of the first encapsulant 30, and the steps shown in fig. 11 and 12.
In a preferred example, referring to fig. 11, a metal coating layer 70 is formed on the upper surface of the first encapsulant 30 and the inner sidewalls and bottom of the first and second limiting holes 31 and 32 by metal deposition. Thereafter, referring to fig. 12, a flip-chip bonding machine is used to flip an isolated second heat dissipation carrier 40 and the flip-chip bonding method is set on the first encapsulant 30 formed with the metal cover 70, the inner surface of the second heat dissipation carrier 40 is provided with a first drain post 41 and a second drain post 42 that are mutually connected, and in a flip-chip bonding process (refer to fig. 10 in combination), the first drain post 41 is inserted into the first limiting hole 31 to connect the drain layer 15 and the second heat dissipation carrier 40, and meanwhile, the second drain post 42 is inserted into the second limiting hole 32 to connect the second heat dissipation carrier 40 and the drain island 23 of the first heat dissipation carrier 20. In a variation, the connection of the post to the bottom of the hole may be accomplished with solder. Finally, packaging and separating cutting are carried out to manufacture the packaging structure shown in fig. 10.
In other examples, the invention also provides an electronic device, referring to fig. 1 or 10, comprising a printed circuit board (not shown) and a double-sided heat dissipation MOSFET package structure bonded on the printed circuit board, wherein the source island 21, the gate island 22 and the drain island 23 are bonded to the printed circuit board by solder, and the second heat dissipation carrier 40 is exposed on the package top surface 51 of the double-sided heat dissipation MOSFET package structure. The electronic device can transfer heat out of the MOSFET package structure more quickly, and the second heat sink 40 serves not only as a drain intermediate connection but also as a heat sink for the package top surface 51.
The embodiments of the present invention are all preferred embodiments for easy understanding or implementation of the technical solution of the present invention, and are not limited in scope by the present invention, and all equivalent changes according to the structure, shape and principle of the present invention should be covered in the scope of the claimed invention.
Claims (10)
1. A double-sided heat-dissipating MOSFET package structure, comprising:
a chip body having a processing surface and an opposite back surface, a source electrode pad and a grid electrode pad are arranged on the treatment surface, and a drain electrode layer is arranged on the back surface;
The first heat dissipation slide is used for overturning and jointing the chip main body in a flip-chip combined mode, and the source electrode pad and the grid electrode pad of the chip main body are respectively communicated with a source electrode island and a grid electrode island of the first heat dissipation slide;
The first packaging colloid is formed on the first heat dissipation slide to seal the chip main body, and is provided with a first limit hole communicated with the drain electrode layer and a second limit hole outside the drain electrode layer, wherein the second limit hole is communicated with a drain electrode island of the first heat dissipation slide;
The second heat dissipation slide is arranged on the first packaging colloid in a flip-chip bonding mode, a first drain electrode column and a second drain electrode column which are mutually communicated are arranged on the inner surface of the second heat dissipation slide, the inner surface of the second heat dissipation slide is turned towards the first packaging colloid, the first drain electrode column is inserted into the first limiting hole so as to conduct the drain electrode layer and the second heat dissipation slide, the second drain electrode column is inserted into the second limiting hole so as to conduct the second heat dissipation slide and the drain electrode island of the first heat dissipation slide, the second heat dissipation surface of the second heat dissipation slide is parallel to the packaging bottom surface, and the connection between the column and the hole bottom is completed by solder;
The first drain electrode columns and the second drain electrode columns are different in length, the second drain electrode columns are longer than the first drain electrode columns, the first drain electrode columns and the second drain electrode columns are respectively arranged in individual array areas on the inner surface of the second heat dissipation slide sheet to form hidden identification codes of the chip main body, a small part of the first drain electrode columns are not connected to the drain electrode layer of the chip main body, the first drain electrode columns which are in empty connection are identified through electron flow distribution, or which of the first limiting holes are in floating connection is determined before the second heat dissipation slide sheet is installed.
2. The dual sided heat sink MOSFET package of claim 1 wherein the connection of the source pad to the source island and the connection of the gate pad to the gate island comprise coplanar solder, the connection of the first drain stud to the drain layer and the connection of the second drain stud to the drain island comprise high and low level difference solder or metal stud mating tight fit, and when metal stud mating tight fit is employed, a layer of cap layer is formed on the top surface of the first encapsulant and the hole inner sidewalls and bottom of the first and second limiting holes, which electrically interconnects the drain layer of the die body with the drain island of the first heat sink in advance prior to mounting the second heat sink.
3. The dual sided heat dissipating MOSFET package of claim 1 further comprising a second encapsulant formed over said first encapsulant to circumscribe a perimeter of said second heat sink.
4. The dual sided MOSFET package of claim 3, wherein the second encapsulant and the second heat sink together provide a flush top package surface parallel to the bottom package surface provided by the first heat sink.
5. The dual sided heat dissipating MOSFET package of claim 3, wherein the second heat sink is removably separable from the first encapsulant prior to the second encapsulant being shaped and cured.
6. The dual sided heat sink MOSFET package of claim 1, wherein the gate island is located at a corner notch of the source island and the drain island is located at a side of the source island remote from the corner notch.
7. The dual sided heat sink MOSFET package of any of claims 1-6, wherein the package is a flip chip die size package (FC-CSP), the second heat sink surface of the second heat sink is larger than and covers both the drain layer of the die body and any of the source islands of the first heat sink, and the array pattern of the first drain pillars and the second drain pillars is defined as a hidden identification code of an individual MOSFET of the die body.
8. The manufacturing method of the double-sided heat dissipation MOSFET packaging structure is characterized by comprising the following steps of:
preparing an isolated chip main body, wherein the chip main body is provided with a processing surface and a corresponding back surface, a source electrode pad and a grid electrode pad are arranged on the processing surface, and a drain electrode layer is arranged on the back surface;
the chip main body is turned over in a flip chip bonding mode and is bonded on a first heat dissipation slide, so that the source electrode pad and the gate electrode pad of the chip main body are respectively communicated with a source electrode island and a gate electrode island of the first heat dissipation slide;
Forming a first packaging colloid on the first heat dissipation carrier to seal the chip main body;
the first packaging colloid is provided with a first limiting hole communicated with the drain electrode layer and a second limiting hole outside the drain electrode layer, and the second limiting hole is communicated with a drain electrode island of the first heat dissipation slide;
The first drain electrode column is inserted into the first limiting hole to conduct the drain electrode layer and the second heat dissipation slide, and meanwhile, the second drain electrode column is inserted into the second limiting hole to conduct the drain electrode islands of the second heat dissipation slide and the first heat dissipation slide, and the connection between the column and the hole bottom is completed by solder;
The first drain electrode columns and the second drain electrode columns are different in length, the second drain electrode columns are longer than the first drain electrode columns, the first drain electrode columns and the second drain electrode columns are respectively arranged in individual array areas on the inner surface of the second heat dissipation slide sheet to form hidden identification codes of the chip main body, a small part of the first drain electrode columns are not connected to the drain electrode layer of the chip main body, the first drain electrode columns which are in empty connection are identified through electron flow distribution, or which of the first limiting holes are in floating connection is determined before the second heat dissipation slide sheet is installed.
9. The method for manufacturing a double-sided heat dissipating MOSFET package of claim 8, wherein:
During the mounting of the chip body, the connection of the source pad to the source island and the connection of the gate pad to the gate island comprise coplanar soldering; when the tight fit of the metal column plug is adopted, a metal covering layer is formed on the upper surface of the first packaging colloid and the inner side walls and the bottoms of the holes of the first limiting hole and the second limiting hole, and the drain electrode layer of the chip main body and the drain electrode island of the first cooling slide are electrically interconnected in advance before the second cooling slide is mounted;
After the first packaging colloid is formed, the grid electrode island is positioned at a corner notch of the source electrode island, and the drain electrode island is positioned at the side edge of the source electrode island away from the corner notch;
after the second heat dissipation slide is turned over and bonded, a second packaging colloid is formed on the first packaging colloid so as to encircle and fix the periphery of the second heat dissipation slide;
before the second packaging colloid is formed and solidified, the second heat dissipation slide is detachably separated relative to the first packaging colloid;
After the second packaging colloid is formed, the method further comprises the steps of flattening and grinding the second packaging colloid and the second heat dissipation slide, wherein a flush packaging top surface is provided by the second packaging colloid and the second heat dissipation slide together, and the flush packaging top surface is parallel to the packaging bottom surface provided by the first heat dissipation slide;
After the second encapsulant is formed, further comprising package singulation dicing to configure the package structure as a flip chip die size package (FC-CSP), the second heat dissipation surface of the second heat dissipation chip being simultaneously larger than and covering any of the drain layer of the chip body and the source island of the first heat dissipation chip.
10. An electronic device, comprising a printed circuit board and a double-sided MOSFET package bonded to the printed circuit board as claimed in any one of claims 1-7, wherein the source island, the gate island, and the drain island on the bottom surface of the double-sided MOSFET package are solder bonded to the printed circuit board, and the second heat sink is exposed on the top surface of the double-sided MOSFET package.
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| CN114284231A (en) * | 2021-12-27 | 2022-04-05 | 珠海镓未来科技有限公司 | Packaging structure and packaging method of cascaded GaN-based power device |
| CN116072629B (en) * | 2023-03-06 | 2023-06-30 | 广东气派科技有限公司 | Packaging structure for enhancing heat dissipation of high-power radio frequency device and preparation method |
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| CN104733413A (en) * | 2015-03-27 | 2015-06-24 | 江阴长电先进封装有限公司 | MOSFET packaging structure |
| CN106328545A (en) * | 2015-07-02 | 2017-01-11 | 万国半导体(开曼)股份有限公司 | Ultrathin chip double-surface exposed package structure of and manufacturing method thereof |
| CN215183929U (en) * | 2021-07-07 | 2021-12-14 | 深圳真茂佳半导体有限公司 | Double-side heat-dissipation MOSFET packaging structure and electronic device |
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| JP5007529B2 (en) * | 2006-06-22 | 2012-08-22 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| US20100164078A1 (en) * | 2008-12-31 | 2010-07-01 | Ruben Madrid | Package assembly for semiconductor devices |
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|---|---|---|---|---|
| CN104733413A (en) * | 2015-03-27 | 2015-06-24 | 江阴长电先进封装有限公司 | MOSFET packaging structure |
| CN106328545A (en) * | 2015-07-02 | 2017-01-11 | 万国半导体(开曼)股份有限公司 | Ultrathin chip double-surface exposed package structure of and manufacturing method thereof |
| CN215183929U (en) * | 2021-07-07 | 2021-12-14 | 深圳真茂佳半导体有限公司 | Double-side heat-dissipation MOSFET packaging structure and electronic device |
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