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CN113451235A - QFN (quad Flat No lead) packaged semiconductor device - Google Patents

QFN (quad Flat No lead) packaged semiconductor device Download PDF

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Publication number
CN113451235A
CN113451235A CN202110620908.2A CN202110620908A CN113451235A CN 113451235 A CN113451235 A CN 113451235A CN 202110620908 A CN202110620908 A CN 202110620908A CN 113451235 A CN113451235 A CN 113451235A
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Prior art keywords
parts
chip
semiconductor device
pad
packaged semiconductor
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CN202110620908.2A
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Chinese (zh)
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CN113451235B (en
Inventor
马磊
党鹏
杨光
彭小虎
王新刚
庞朋涛
任斌
王妙妙
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Xi'an Hangsi Semiconductor Co ltd
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Xi'an Hangsi Semiconductor Co ltd
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Publication of CN113451235A publication Critical patent/CN113451235A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Epoxy Resins (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Die Bonding (AREA)

Abstract

The invention discloses a QFN (quad flat no-lead) packaged semiconductor device, which comprises a heat dissipation welding disc, a chip and a conductive welding disc which are positioned in an epoxy insulator, wherein a separating groove is formed in one side, away from the chip, of the heat dissipation welding disc, the width of the separating groove is 0.1-0.3 mm, and the separating groove equally separates one side, away from the chip, of the heat dissipation welding disc into at least 2 welding disc monomers; the epoxy insulator comprises the following raw materials in parts by weight: epoxy resin, novolac resin, liquid nitrile rubber, diphenylmethane diisocyanate, diethyl pyrocarbonate, dibenzyl phosphate, silicon micropowder, gamma-methacryloxypropyltrimethoxysilane, 5-fluoro-2-methoxyaniline, 2,4, 6-tris (dimethylaminomethyl) phenol, a mold release agent and a flame retardant. The QFN packaged semiconductor device enhances the overall mechanical property of an epoxy insulator and effectively ensures the stability of a packaging structure.

Description

QFN (quad Flat No lead) packaged semiconductor device
Technical Field
The invention belongs to the technical field of leadless packaging, and particularly relates to a QFN packaged semiconductor device.
Background
The QFN package is widely applied to a PCB, and the application of the QFN package greatly promotes the development of electronic technology. The QFN package has excellent thermal performance mainly because the package bottom has a large area of heat dissipation solder, in order to effectively conduct the heat from the chip to the PCB, the bottom of the PCB must be designed with a heat dissipation pad and a heat dissipation via corresponding to the heat dissipation solder, the heat dissipation pad provides a reliable soldering area, and the heat dissipation via provides a heat dissipation path.
Conventional QFN packages typically have a large area heat dissipation pad in the PCB, which is usually grounded, and although the heat dissipation pad can perform the function of dissipating heat from the chip, the pad is too large, and the solder brushing during the Surface Mount Technology (SMT) process often causes a short circuit between the large heat dissipation pad in the center of the QFN package and other small conductive pads. In addition, as the integrated circuit package is developed to be high density, high integration and high speed, the package structure is also exposed to a series of reliability risks caused by heat generated by the chip. Therefore, how to develop a heat-resistant packaging structure with a short-circuit prevention function is of great significance to the development of high-performance electronic devices.
Disclosure of Invention
The invention aims to provide a QFN package semiconductor device, which has a good short-circuit prevention function, good overall mechanical performance, stable structure and high reliability.
In order to achieve the purpose, the invention adopts the technical scheme that: a QFN package semiconductor device comprises a heat dissipation pad, a chip and a conductive pad, wherein the heat dissipation pad, the chip and the conductive pad are positioned in an epoxy insulator, the chip is positioned on the heat dissipation pad, a silver paste layer is arranged between the chip and the heat dissipation pad, a plurality of conductive pads are arranged on the periphery of the heat dissipation pad, and the conductive pads are connected with the chip through a lead;
a separating groove is formed in one side, away from the chip, of the heat dissipation welding disc, the width of the separating groove is 0.1-0.3 mm, the separating groove divides one side, away from the chip, of the heat dissipation welding disc into at least 2 welding disc monomers in an equal dividing mode, heat conduction insulating strips are filled in the separating groove, a plurality of T-shaped grooves extending into the heat dissipation welding disc are formed in the wall of the separating groove, and T-shaped portions filled in the T-shaped grooves are formed in the heat conduction insulating strips;
the epoxy insulator comprises the following raw materials in parts by weight: 80 parts of epoxy resin, 50 parts of novolac resin, 20 parts of liquid nitrile rubber, 6 parts of diphenylmethane diisocyanate, 7 parts of diethyl pyrocarbonate, 6.5 parts of dibenzyl phosphate, 60 parts of silicon powder, 6 parts of gamma-methacryloxypropyltrimethoxysilane, 0.3 part of 5-fluoro-2-methoxyaniline, 4 parts of 2,4, 6-tris (dimethylaminomethyl) phenol, 3 parts of a release agent and 25 parts of a flame retardant.
The technical scheme of further improvement in the technical scheme is as follows:
1. in the above embodiment, the release agent is stearic acid.
2. In the above scheme, the flame retardant is borate.
3. In the above scheme, the thickness of the heat conducting insulating strip is smaller than the depth of the separation groove.
4. In the above scheme, the area of the bonding pad monomer is notLess than 0.3 x 0.3mm2。
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages:
1. according to the QFN packaged semiconductor device, the liquid nitrile rubber is added into an epoxy resin system according to the formula of an epoxy insulator, 2,4, 6-tri (dimethylaminomethyl) phenol is used as a curing accelerator, and diethyl pyrocarbonate and 5-fluoro-2-methoxybenzene are additionally added, so that the crosslinking density of a cured product is improved, the overall mechanical property of the epoxy insulator is enhanced, and the stability of a packaging structure is effectively ensured.
2. According to the QFN packaged semiconductor device, the epoxy insulator formula is added with diphenylmethane diisocyanate and dibenzyl phosphate on the basis of epoxy resin, linear phenolic resin and liquid nitrile rubber, so that the prepared resin has excellent heat resistance on the premise of ensuring good mechanical property, the glass transition temperature reaches 190-230 ℃, and the requirement of high-power high-heating chip packaging can be met.
3. According to the QFN packaged semiconductor device, the separating grooves are formed in the surfaces of the radiating welding discs far away from the chip, the parts, far away from the chip, of the radiating welding discs are equally divided into at least two welding disc single bodies through the separating grooves in different shapes, and after the radiating welding discs are divided into the plurality of welding disc single bodies, the surface areas, far away from the chip, of the welding disc single bodies are smaller than the surface areas, far away from the chip, of the original radiating welding discs, so that the using amount of solder paste is reduced, and the short circuit phenomenon between the radiating welding discs and the conductive welding discs is effectively controlled; meanwhile, after the heat-conducting insulating strips are filled in the separation grooves, epoxy insulating resin with poor heat-conducting effect cannot be filled in the separation grooves, so that the heat-radiating function of the heat-radiating welding pad part is not affected, and the cost of the surface mount technology can be reduced along with the reduction of the use amount of the solder paste; in addition, when the heat-conducting insulating strip is filled into the separation groove in an injection molding mode, part of resin can enter the T-shaped groove to form a T-shaped part, so that the position of the heat-conducting insulating strip is firmly clamped by the T-shaped part and the T-shaped groove, and the phenomenon that the heat-conducting insulating strip is separated from the separation groove to influence the use of the heat-conducting insulating strip due to injection molding quality problems or external force is avoided.
Drawings
FIG. 1 is a schematic diagram of a QFN packaged semiconductor device in accordance with the present invention;
fig. 2 is an enlarged view of a portion of fig. 1A.
In the above drawings: 1. a heat-dissipating pad; 11. a separation tank; 111. a T-shaped slot; 12. a thermally conductive insulating strip; 121. a T-shaped portion; 13. a bonding pad monomer; 2. a silver paste layer; 3. a chip; 4. a conductive pad; 5. a lead wire; 6. an epoxy insulator.
Detailed Description
The invention is further described below with reference to the following examples:
example (b): a QFN package semiconductor device comprises a heat dissipation pad 1, a chip 3 and conductive pads 4, wherein the heat dissipation pad 1, the chip 3 and the conductive pads 4 are positioned in an epoxy insulator 6, the chip 3 is positioned on the heat dissipation pad 1, a silver paste layer 2 is arranged between the chip 3 and the heat dissipation pad 1, a plurality of conductive pads 4 are arranged on the periphery of the heat dissipation pad 1, and the conductive pads 4 are connected with the chip 3 through leads 5;
a separating groove 11 is formed in one side, away from the chip 3, of the heat dissipation pad 1, the width of the separating groove 11 is 0.1-0.3 mm, the separating groove 11 equally separates one side, away from the chip 3, of the heat dissipation pad 1 into at least 2 pad monomers 13, a heat conduction insulating strip 12 is filled in the separating groove 11, a plurality of T-shaped grooves 111 extending into the heat dissipation pad 1 are formed in the wall of the separating groove 11, and a T-shaped portion 121 filled in the T-shaped grooves 111 is arranged on the heat conduction insulating strip 12;
the thickness of the heat conducting insulating strip 12 is smaller than the depth of the separation groove 11;
the area of the bonding pad single body 13 is not less than 0.3 x 0.3mm2；
The distance between the conductive bonding pad 4 and the heat dissipation bonding pad 1 is 0.3 mm;
the conductive pad 4 is a T-shaped block.
The raw materials of the epoxy insulator 6 comprise the following components in parts by weight: 80 parts of epoxy resin, 50 parts of novolac resin, 20 parts of liquid nitrile rubber, 6 parts of diphenylmethane diisocyanate, 7 parts of diethyl pyrocarbonate, 6.5 parts of dibenzyl phosphate, 60 parts of silicon powder, 6 parts of gamma-methacryloxypropyltrimethoxysilane, 0.3 part of 5-fluoro-2-methoxyaniline, 4 parts of 2,4, 6-tris (dimethylaminomethyl) phenol, 3 parts of a release agent and 25 parts of a flame retardant.
The fine silica powder is fused fine silica powder, the fine silica powder D50 is 4 to 8 μm, and the fine silica powder D100 is 10 to 25 μm.
The release agent is stearic acid, and the flame retardant is borate.
The preparation method of the raw material of the epoxy insulator 6 comprises the following steps:
s1, uniformly mixing the silicon micropowder, the flame retardant and gamma-methacryloxypropyl trimethoxysilane, and carrying out surface treatment;
s2, adding epoxy resin, novolac resin, liquid nitrile rubber, diphenylmethane diisocyanate, diethyl pyrocarbonate, dibenzyl phosphate, 5-fluoro-2-methoxyaniline, 2,4, 6-tris (dimethylaminomethyl) phenol and a release agent, and uniformly mixing;
s3, mixing the mixture at 90-110 ℃ for 3-5 minutes, cooling the product, crushing and sieving.
Comparative examples 1 to 3: the epoxy insulator comprises the following raw materials in parts by weight:
TABLE 2
Components Comparative example 1 Comparative example 2 Comparative example 3
Epoxy resin 90 80 100
Phenol novolac resin 60 45 55
Liquid nitrile rubber 20 5 16
Diphenylmethane diisocyanate 2 6 3
Pyrocarbonic acid diethyl ester 8 3 -
Phosphoric acid dibenzyl ester 6.5 - -
Silicon micropowder 60 90 80
Gamma-methacryloxypropyltrimethoxysilane 5 3 8
5-fluoro-2-methoxyaniline - 1.5 2
2,4, 6-tris (dimethylaminomethyl) phenol 4 0.5 2
Release agent 4 2 5
Release agent 25 10 15
The fine silica powder is fused fine silica powder, the fine silica powder D50 is 4 to 8 μm, and the fine silica powder D100 is 10 to 25 μm.
The release agent in comparative example 1 was stearic acid and the flame retardant was borate; the release agent in comparative example 2 was stearate and the flame retardant was borate; the release agent in comparative example 3 was oxidized polyethylene wax and the flame retardant was molybdate.
The preparation process is the same as the embodiment.
The properties of the epoxy insulators prepared in the above examples and comparative examples 1 to 3 are shown in table 3:
TABLE 3
Figure 864392DEST_PATH_IMAGE002
In each of examples and comparative examples, the molding conditions of the epoxy insulator were as follows: the mold temperature is 180 ℃, and the injection pressure is 700kg/cm2Curing time 2 min.
As shown in the evaluation results in table 3, the epoxy insulators in the embodiments have better overall mechanical properties and heat resistance than the comparative examples, and when used in the QFN package structure, the stability of the package structure can be ensured, and the requirements of high-power and high-heat-generation chip package can be met.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims (5)

1. A QFN packaged semiconductor device, characterized by: the LED packaging structure comprises a radiating pad (1) positioned in an epoxy insulator (6), a chip (3) and a conductive pad (4), wherein the chip (3) is positioned on the radiating pad (1), a silver paste layer (2) is arranged between the chip (3) and the radiating pad (1), a plurality of conductive pads (4) are arranged on the periphery of the radiating pad (1), and the conductive pads (4) are connected with the chip (3) through a lead (5);
a separating groove (11) is formed in one side, away from the chip (3), of the radiating pad (1), the width of the separating groove (11) is 0.1-0.3 mm, the separating groove (11) divides one side, away from the chip (3), of the radiating pad (1) into at least 2 pad monomers (13) in an equal partition mode, a heat-conducting insulating strip (12) is filled in the separating groove (11), a plurality of T-shaped grooves (111) extending into the radiating pad (1) are formed in the wall of the separating groove (11), and a T-shaped portion (121) filled in the T-shaped grooves (111) is arranged on the heat-conducting insulating strip (12);
the epoxy insulator (6) comprises the following raw materials in parts by weight: 80 parts of epoxy resin, 50 parts of novolac resin, 20 parts of liquid nitrile rubber, 6 parts of diphenylmethane diisocyanate, 7 parts of diethyl pyrocarbonate, 6.5 parts of dibenzyl phosphate, 60 parts of silicon powder, 6 parts of gamma-methacryloxypropyltrimethoxysilane, 0.3 part of 5-fluoro-2-methoxyaniline, 4 parts of 2,4, 6-tris (dimethylaminomethyl) phenol, 3 parts of a release agent and 25 parts of a flame retardant.
2. The QFN packaged semiconductor device of claim 1, wherein: the release agent is selected from stearic acid.
3. The QFN packaged semiconductor device of claim 1, wherein: the flame retardant is borate.
4. The QFN packaged semiconductor device of claim 1, wherein: the thickness of the heat conduction insulating strip (12) is smaller than the depth of the separation groove (11).
5. The QFN packaged semiconductor device of claim 1, wherein: the area of the bonding pad single body (13) is not less than 0.3 x 0.3mm2。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04290463A (en) * 1990-12-03 1992-10-15 Motorola Inc Semiconductor package having detached type heat sink-bonding pad
JP2000243891A (en) * 1999-02-24 2000-09-08 Matsushita Electronics Industry Corp Resin sealing type semiconductor device, its manufacture method, and lead frame
KR20090048833A (en) * 2007-11-12 2009-05-15 삼성에스디아이 주식회사 Semiconductor package and its mounting method
WO2013136746A1 (en) * 2012-03-12 2013-09-19 サンアプロ株式会社 Epoxy resin curing accelerator
US20160260645A1 (en) * 2015-01-30 2016-09-08 Panasonic Intellectual Property Management Co., Ltd. Sealing epoxy resin composition, hardened product, and semiconductor device
CN106256853A (en) * 2015-06-22 2016-12-28 味之素株式会社 Molded underfill resin combination
TWM606836U (en) * 2020-09-18 2021-01-21 長華科技股份有限公司 Lead frame

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07242733A (en) * 1994-03-05 1995-09-19 Toshiba Chem Corp Epoxy resin composition and sealed semiconductor device
US6204553B1 (en) * 1999-08-10 2001-03-20 Walsin Advanced Electronics Ltd. Lead frame structure
JP2001081286A (en) * 1999-09-13 2001-03-27 Sumitomo Bakelite Co Ltd Resin paste for semiconductor and semiconductor device using the same
US20030006055A1 (en) * 2001-07-05 2003-01-09 Walsin Advanced Electronics Ltd Semiconductor package for fixed surface mounting
JP3879452B2 (en) * 2001-07-23 2007-02-14 松下電器産業株式会社 Resin-sealed semiconductor device and manufacturing method thereof
US6777788B1 (en) * 2002-09-10 2004-08-17 National Semiconductor Corporation Method and structure for applying thick solder layer onto die attach pad
JP2007016063A (en) * 2005-07-05 2007-01-25 San Apro Kk Epoxy resin composition for sealing semiconductor
KR100782225B1 (en) * 2005-09-02 2007-12-05 엘에스전선 주식회사 Leadframe and semiconductor package with die pads with depressions
US8828806B2 (en) * 2009-06-01 2014-09-09 Shin-Etsu Chemical Co., Ltd. Dam composition for use with multilayer semiconductor package underfill material, and fabrication of multilayer semiconductor package using the same
US9029991B2 (en) * 2010-11-16 2015-05-12 Conexant Systems, Inc. Semiconductor packages with reduced solder voiding
JP5832740B2 (en) * 2010-11-30 2015-12-16 株式会社ダイセル Curable epoxy resin composition
JP5799694B2 (en) * 2011-09-12 2015-10-28 日立化成株式会社 Epoxy resin composition for semiconductor encapsulation and semiconductor device using the same
JP2014007363A (en) * 2012-06-27 2014-01-16 Renesas Electronics Corp Method of manufacturing semiconductor device and semiconductor device
US20140255270A1 (en) * 2013-02-28 2014-09-11 California Institute Of Technology Removing sacrificial layer to form liquid containment structure and methods of use thereof
TWI524482B (en) * 2013-12-11 2016-03-01 南茂科技股份有限公司 Chip package structure and manufacturing method thereof
CN203871318U (en) * 2014-03-17 2014-10-08 长华科技股份有限公司 Double-layer lead frame structure
TWM488042U (en) * 2014-05-23 2014-10-11 Immense Digitize Engineering Co Ltd Visual design module for cloud cooperative working platform
CN104673111B (en) * 2014-06-30 2017-01-11 广东丹邦科技有限公司 Formula and preparation method of epoxy resin based anisotropic conductive adhesive film
CN105778409A (en) * 2014-12-18 2016-07-20 北京首科化微电子有限公司 Epoxy resin composition for semiconductor packaging, and preparation method thereof
CN106479128A (en) * 2016-10-18 2017-03-08 北京中新泰合电子材料科技有限公司 A kind of luminescent semiconductor device epoxy resin composition for packaging and preparation method thereof
KR20180095410A (en) * 2017-02-17 2018-08-27 주식회사 동진쎄미켐 Conductive Adhesive Composition
CN206789537U (en) * 2017-05-02 2017-12-22 泰瑞科微电子（淮安）有限公司 Surface mount rectification chip
CN107275305B (en) * 2017-07-13 2020-03-10 郑州云海信息技术有限公司 QFN chip
CN108129802A (en) * 2017-12-25 2018-06-08 科化新材料泰州有限公司 A kind of composition epoxy resin preparation method of semiconductor-sealing-purpose

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04290463A (en) * 1990-12-03 1992-10-15 Motorola Inc Semiconductor package having detached type heat sink-bonding pad
JP2000243891A (en) * 1999-02-24 2000-09-08 Matsushita Electronics Industry Corp Resin sealing type semiconductor device, its manufacture method, and lead frame
KR20090048833A (en) * 2007-11-12 2009-05-15 삼성에스디아이 주식회사 Semiconductor package and its mounting method
WO2013136746A1 (en) * 2012-03-12 2013-09-19 サンアプロ株式会社 Epoxy resin curing accelerator
US20160260645A1 (en) * 2015-01-30 2016-09-08 Panasonic Intellectual Property Management Co., Ltd. Sealing epoxy resin composition, hardened product, and semiconductor device
CN106256853A (en) * 2015-06-22 2016-12-28 味之素株式会社 Molded underfill resin combination
TWM606836U (en) * 2020-09-18 2021-01-21 長華科技股份有限公司 Lead frame

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