CN113419198B - Vertical Hall sensor structure - Google Patents

Abstract

The present application is applicable to the field of sensor technology, and in particular to a vertical Hall sensor structure. The vertical Hall sensor structure includes: a ring-shaped P well, an N well located in the ring-shaped P well, and P-type regions and N-type regions alternately arranged on the N well, and there is an overlapping area between the P well and the N well. The embodiments of the present application can improve the sensitivity of the device.

Description

A vertical Hall sensor structure

Technical Field

The present application relates to the field of sensor technology, and in particular to a vertical Hall sensor structure.

Background technique

The Hall effect is a type of electromagnetic effect. When current passes through a semiconductor perpendicular to an external magnetic field, the carriers are deflected, and an additional electric field is generated perpendicular to the direction of the current and the magnetic field, thereby generating a potential difference at both ends of the semiconductor. This phenomenon is the Hall effect, and this potential difference is also called the Hall potential difference. The Hall device made according to the Hall effect uses the magnetic field as the working medium to convert the motion parameters of an object into a digital voltage output, so that it has the functions of sensing and switching.

Vertical Hall sensors can detect magnetic fields parallel to the device surface. Currently, vertical Hall sensors have been widely used in the fields of automobiles, medical treatment, instruments, meters or electronic equipment. However, the currently implemented Hall sensors still have the problem of low magnetic field sensitivity.

Summary of the invention

In view of this, an embodiment of the present application provides a vertical Hall sensor structure to solve at least one technical problem in the related art.

In a first aspect, an embodiment of the present application provides a vertical Hall sensor structure, comprising: a ring-shaped P-well, an N-well located in the ring-shaped P-well, and P-type regions and N-type regions alternately arranged on the N-well, and there is an overlapping area between the P-well and the N-well.

In this embodiment, the N-well and the P-type region and N-type region on the N-well form a Hall effect region, and an overlapping region is formed between the P-well and the N-well, thereby increasing the thickness of the equipotential interface, so that the current in the N-well is away from the interface, thereby improving the uniformity of the current volume density in the N-well and improving the sensitivity of the device.

In some embodiments, the P-type region is in a strip shape, passes through the N-well, and has two ends extending into the P-well.

In some embodiments, the N-type region is in a strip shape, passes through the N-well, and has two ends extending into the P-well.

In some embodiments, there are four P-type regions and five N-type regions, and the four P-type regions and the five N-type regions are alternately and evenly spaced on the N-well.

In some embodiments, the five N-type regions have the same shape and size, the four P-type regions have the same shape and size, and the four P-type regions and the five N-type regions are symmetrically distributed on the N-well.

In some embodiments, in the P-type regions and N-type regions alternately arranged on the N-well, the contact holes corresponding to the two outermost N-type regions are connected to each other to form a first port, the contact hole corresponding to the middle N-type region forms a second port, and the contact holes corresponding to the two inner N-type regions form a third port and a fourth port respectively;

The contact holes corresponding to the P-type regions are all grounded;

The first port and the second port output voltage, and the third port and the fourth port are externally connected between a bias voltage and ground; or, the first port and the second port are externally connected between a bias voltage and ground, and the third port and the fourth port output voltage.

In some embodiments, it further includes a plurality of contact holes corresponding to the P-type regions and the N-type regions, and the contact holes are in a continuous strip shape.

In some embodiments, the contact hole is at least partially embedded in the N-well, the P-type region and the N-type region are both disposed in the contact hole, and the contact hole passes through the N-well, with both ends extending into the P-well.

In some embodiments, the upper surface of the P-type region, the upper surface of the N-type region, and the upper surface of the N-well are flush, and the contact hole covers the corresponding P-type region or the N-type region.

In some embodiments, among the P-type regions and N-type regions alternately disposed on the N-well, the minimum distance between the outermost N-type region and the overlapping region is smaller than the width of the outermost N-type region.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

FIG1 is a schematic top view of a vertical Hall sensor structure provided by an embodiment of the present application;

FIG2 is a schematic diagram of a vertical Hall sensor structure provided in FIG1 in the A-A direction;

FIG3 is a working state diagram of a vertical Hall sensor structure provided by an embodiment of the present application;

FIG. 4 is a working state diagram of a vertical Hall sensor structure provided in another embodiment of the present application.

Detailed ways

In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

The term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

"One embodiment" or "some embodiments" described in the specification of the present application means that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the sentences "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

In addition, in the description of the present application, "plurality" means two or more. The terms "first", "second", "third", and "fourth" are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

In order to illustrate the technical solution of the present invention, a specific embodiment is provided below for illustration.

FIG1 is a schematic diagram of a top view of a vertical Hall sensor structure provided in an embodiment of the present application, and FIG2 is a schematic diagram of a cross-sectional view in the A-A direction of a vertical Hall sensor structure provided in FIG1 of the present application.

As shown in FIG. 1 and FIG. 2 , the vertical Hall sensor structure includes: an annular P well 1, an N well 2 located in the annular P well 1, and P-type regions 3 and N-type regions 4 alternately arranged on the N well 2. There is an overlapping region 12 between the P well 1 and the N well 2.

In the embodiment of the present application, the N-well and the P-type region and the N-type region on the N-well form a Hall effect region, and an overlapping region is formed between the P-well and the N-well, thereby increasing the thickness of the equipotential interface, so that the current in the N-well is away from the interface, thereby improving the uniformity of the current volume density in the N-well and improving the sensitivity of the device.

In some embodiments, as shown in FIG. 1 and FIG. 2 , the P-well 1 is roughly in the shape of a rectangular ring, the N-well 2 is roughly in the shape of a cuboid, the N-well 2 is arranged in the center of the P-well 1, and the overlapping region 12 between the N-well 2 and the P-well 1 is roughly in the shape of a rectangular ring. The P-well 1 is a high-voltage P-well. The N-well 2 is a high-voltage N-well. The N-well 2 is a low-doped deep well, and the depth can be 7 to 10 microns, for example, 7 microns, 8 microns or 10 microns. In the embodiment of the present application, there is an overlapping region 12 between the P-well 1 and the N-well 2, and the overlapping region 12 reduces the concentration around the N-well, improves the Gaussian distribution of impurities inside the N-well, and increases the effective depth of the N-well 1.

In some embodiments, as shown in FIG1 , the P-type region 3 is in a strip shape and can penetrate the middle N-well 2, with both ends extending into the P-well 1. The P-type region is a P+ electrode. In these embodiments, by bridging the N-well and the P-well with the P+ active region, the surface carriers of the N-well are neutralized, and the current is allowed to flow in the deeper N-well active region, thereby improving the uniformity of the current volume density in the N-well and reducing the device misalignment.

In some embodiments, as shown in FIG. 1 , the N-type region 4 is in a strip shape and can penetrate the middle N-well 2, with both ends extending into the P-well 1. The N-type region is an N+ electrode. In these embodiments, by connecting the N+ active region across the N-well and the P-well, the device misalignment caused by the asymmetry caused by the misalignment of the mask pair in the production process is reduced.

In some embodiments, as shown in FIG. 1 , contact holes 5 corresponding to the P-type regions 3 and N-type regions 4 are provided on the N-well (not all contact holes are marked in FIG. 1 ), and the contact holes 5 are in the shape of continuous long strips.

In some implementations, the P-type region 3 and the N-type region 4 are disposed in the contact hole 5. The contact hole 5 may be at least partially embedded in the N-well 2. The upper surface of the contact hole 5 may be flush with the upper surface of the N-well 2, or may protrude from the upper surface of the N-well 2.

In some other implementations, as shown in combination with FIG. 1 and FIG. 2 , the upper surfaces of the P-type region 3 and the N-type region 4 are flush with the upper surface of the N-well 2, that is, the N-type region 4 and the P-type region 3 are embedded in the N-well. The upper surface of the P-well 1 is also flush with the upper surface of the N-well 2. As shown in FIG. 1 , the upper surfaces of each N-type region 4 and each P-type region 3 are respectively covered with contact holes 5, which are in the shape of continuous long strips, and the contact holes 5 exceed the central N-well 2, and the two ends extend to the P-well 1.

In these embodiments, by setting the contact holes in a continuous long strip shape, the current density uniformity of the contact surface between the metal and the N+ active area and the P+ active area can be ensured; by covering the N-well and the P-well at the same time with the contact holes, the boundary current between the metal and the P-well and the N-well can be made as uniform as possible, further reducing the device imbalance.

As a non-limiting example, in combination with FIG. 1 and FIG. 2 , there are four P-type regions 3 , which are, from left to right, a first P-type region 31 , a second P-type region 32 , a third P-type region 33 and a fourth P-type region 34 ; there are five N-type regions 4 , which are, from left to right, a first N-type region 41 , a second N-type region 42 , a third N-type region 43 , a fourth N-type region 44 and a fifth N-type region 45 .

As shown in FIG1 , four P-type regions 3 and five N-type regions 4 are alternately arranged in the N-well 2, and the four P-type regions 3 are arranged between the five N-type regions 4 at intervals, and the spacing between adjacent P-type regions and N-type regions is equal, and the four P-type regions 3 and the five N-type regions 4 are symmetrically distributed on the N-well 2. Specifically, as shown in FIG2 , a first P-type region 31 is arranged between the first N-type region 41 and the second N-type region 42; a second P-type region 32 is arranged between the second N-type region 42 and the third N-type region 43; a third P-type region 33 is arranged between the third N-type region 43 and the fourth N-type region 44; and a fourth P-type region 34 is arranged between the fourth N-type region 44 and the fifth N-type region 45. This embodiment is a Hall sensor structure with built-in interconnected vertical 5 holes symmetrically and equidistantly. By symmetrically arranging the P-type region and the N-type region on the N-well, the sensitivity of the device can be improved and the misalignment of the device can be reduced.

In some embodiments, as shown in FIG. 1 and FIG. 2 , the four P-type regions 3 have the same shape and size, the five N-type regions 4 have the same shape and size, and both the P-type regions 3 and the N-type regions 4 are in the shape of a cuboid.

In some embodiments, as shown in Figures 1 and 2, the first N-type region 41 and the fifth N-type region 45 are arranged at the outermost sides, and the contact holes 5 corresponding to the first N-type region 41 and the fifth N-type region 45 on the outer side are connected to each other to form port A, and the contact holes 5 corresponding to the third N-type region 43 in the middle form port B, and the two contact holes 5 corresponding to the two inner second N-type regions 42 and the fourth N-type regions 44 form port C and port D respectively.

Next, the working state of the vertical Hall sensor structure provided by one embodiment of the present application is introduced. FIG3 is a schematic diagram of the working state of the vertical Hall sensor structure provided by one embodiment of the present application; FIG4 is a schematic diagram of the working state of the vertical Hall sensor structure provided by another embodiment of the present application. The Hall effect generates Hall voltage and current to detect the detection magnetic field applied to the active area.

In some embodiments, as shown in FIG. 1 , FIG. 2 and FIG. 3 , the contact holes 5 corresponding to the four P-type regions 3 are all grounded, which can reduce output noise. Port A and port B output voltage. Contact hole C and contact hole D are externally connected between the bias voltage and the ground to generate a current I.

When contact hole C and contact hole D are externally connected between the bias voltage and the ground, the electrons in the two outer first N-type regions 41 and the fifth N-type region 45 first reach the inner second N-type region 42 and the fourth N-type region 44, and then reach the middle third N-type region 43. If a magnetic field parallel to the device surface is applied at this time, the carriers are deflected by the Lorentz force. Carriers of different polarities gather at port A or port B, and a voltage is output between port A and port B.

In some other embodiments, as shown in FIG. 1 , FIG. 2 and FIG. 4 , the contact holes corresponding to the four P-type regions 3 are all grounded, which can reduce output noise. Port A and port B are externally connected between the bias voltage and the ground to generate a current I. Contact holes C and contact holes D output voltage.

In some embodiments of the present application, as shown in combination with FIG. 1 and FIG. 2 , the distance D1 is greater than the width D2 of any N-type region 4. For example, the minimum distance D1 between the left boundary of the first N-type region 41 on the outside and the overlapping region 12 is greater than the width D2 of the first N-type region 41 in the left-right direction, or the minimum distance D1 between the fifth N-type region 45 on the outside and the overlapping region 12 is greater than the width D2 of the fifth N-type region 45 in the left-right direction. By setting the width D1 to be greater than the width D2 of the N-type region, the current density on the left and right sides of the N-type region is improved, so that the current density and uniformity on the left and right sides are approximately the same, and the output offset and noise of the device are further reduced.

In some embodiments of the present application, a suitable process is selected for preparation, and a high-voltage CMOS process is selected. General processes cannot achieve a deeper N-well, which will greatly reduce the sensitivity of the device.

It is understandable that the above content is a further detailed description of the creation of this application in combination with specific/preferred implementation methods, and it cannot be determined that the specific implementation of the creation of this application is limited to these descriptions. For ordinary technicians in the technical field to which the creation of this application belongs, without departing from the creative concept of this application, they can also make several substitutions or modifications to these described implementation methods, and these substitutions or modifications should be deemed to belong to the scope of protection of this patent. In the description of this specification, the description of reference terms "an embodiment", "some embodiments", "preferred embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in combination with the embodiment or example are included in at least one embodiment or example of the present application.

In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradicting each other. Although the embodiments and advantages of the present application have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the scope defined by the appended claims.

In addition, the scope of the invention of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods and steps described in the specification. It will be readily understood by those of ordinary skill in the art that the above disclosures, processes, machines, manufactures, material compositions, means, methods or steps currently existing or to be developed later that perform substantially the same functions as the corresponding embodiments described herein or obtain substantially the same results as the embodiments described herein may be utilized. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, means, methods or steps within their scope.

Claims (6)

1. A vertical Hall sensor structure, characterized in that it comprises: a ring-shaped P-well, an N-well located in the ring-shaped P-well, and P-type regions and N-type regions alternately arranged on the N-well, wherein the N-well and the P-type regions and N-type regions on the N-well form a Hall effect region; there is an overlapping region in a rectangular ring between the P-well and the N-well, which increases the thickness of the equipotential interface; the N-well is a low-doped deep well, and the overlapping region reduces the concentration around the N-well; The P-type region is in a strip shape, runs through the N-well and the overlapping region, and both ends extend into the P-well; the N-type region is in a strip shape, runs through the N-well and the overlapping region, and both ends extend into the P-well; There are four P-type regions in total, and five N-type regions in total, and the four P-type regions and the five N-type regions are alternately and evenly spaced on the N-well; In the P-type regions and N-type regions alternately arranged on the N-well, the contact holes corresponding to the two outermost N-type regions are connected to each other to form a first port, the contact hole corresponding to the middle N-type region forms a second port, and the contact holes corresponding to the two inner N-type regions form a third port and a fourth port respectively; The contact holes corresponding to the P-type regions are all grounded; The first port and the second port output voltage, and the third port and the fourth port are externally connected between a bias voltage and ground; or, the first port and the second port are externally connected between a bias voltage and ground, and the third port and the fourth port output voltage. 2. The vertical Hall sensor structure according to claim 1, characterized in that the five N-type regions have the same shape and size, the four P-type regions have the same shape and size, and the four P-type regions and the five N-type regions are symmetrically distributed on the N-well. 3 . The vertical Hall sensor structure according to claim 1 , further comprising a plurality of contact holes corresponding to each of the P-type regions and the N-type regions, wherein the contact holes are in a continuous strip shape. 4. The vertical Hall sensor structure as described in claim 3 is characterized in that the contact hole is at least partially embedded in the N-well, the P-type region and the N-type region are both arranged in the contact hole, and the contact hole passes through the N-well, and both ends extend into the P-well. 5. The vertical Hall sensor structure according to claim 3, characterized in that the upper surface of the P-type region, the upper surface of the N-type region and the upper surface of the N-well are flush, and the contact hole covers the corresponding P-type region or the N-type region. 6. The vertical Hall sensor structure according to claim 1, characterized in that, among the P-type regions and N-type regions alternately arranged on the N-well, the minimum distance between the outermost N-type region and the overlapping region is less than the width of the outermost N-type region.