CN108535669A - Hall device and its imbalance removing method applied to three-dimensional Hall sensor - Google Patents

Abstract

The invention relates to a Hall device applied to a three-dimensional Hall sensor and an offset elimination method thereof. It can be integrated on a chip to realize monolithic integrated three-dimensional Hall sensor, and the Hall device includes a horizontal Hall device and a vertical Hall device; and an orthogonal coupling rotating current technology is also proposed. The present invention improves and innovates the structures of the horizontal Hall device and the vertical Hall device, improves their performance, and enables them to be applied to monolithically integrated three-dimensional Hall sensors; and the method of the present invention can realize the adjustment of the offset voltage Elimination, so that the three-dimensional detection of the magnetic field can be realized through a single chip, which is of great help to the application of magnetic field detection.

Description

Hall device applied to three-dimensional Hall sensor and its offset elimination method

technical field

The invention relates to a Hall device applied to a three-dimensional Hall sensor and an offset elimination method thereof.

Background technique

In recent years, Hall sensors based on CMOS technology have many advantages such as low power consumption, low cost, high integration, high reliability and strong anti-interference ability, and are widely used in automobile manufacturing, medical electronics, instrumentation and consumer electronics and other fields. However, as people's requirements for magnetic field detection are getting higher and higher, Hall sensors are required to be able to detect magnetic fields in all directions and realize the measurement of three-dimensional magnetic fields. Hall sensors are mainly divided into horizontal type and vertical type. The horizontal Hall sensor is mainly used to detect the magnetic field in the Z-axis direction. It was developed earlier and has excellent performance. The vertical Hall sensor is mainly used for magnetic field detection in the X and Y axis directions. Due to the structure and process of the device itself, the sensitivity of the vertical Hall sensor is relatively low and the offset is large. Integrating the horizontal Hall device and the vertical Hall device on one chip can realize monolithically integrated three-dimensional Hall sensor. Therefore, the high-performance Hall device is the key to realize the three-dimensional Hall sensor. As the core module of the Hall sensor, it determines the overall performance of the Hall sensor.

The traditional three-dimensional magnetic field measurement method mainly uses a special packaging method to place three one-dimensional Hall devices in three different directions, and then package them together to achieve three-dimensional measurement of the magnetic field. This method can be realized only with a one-dimensional horizontal Hall device, but the requirements for packaging are relatively high, and it is not a monolithically integrated three-dimensional Hall sensor, and the cost is relatively high. In order to realize a high-performance single-chip integrated three-dimensional Hall sensor, the present invention proposes horizontal and vertical Hall devices applied to the three-dimensional Hall sensor, and innovates and optimizes the device structure to improve the sensitivity of the Hall device. reduces its initial offset. And a technique combining quadrature coupling with spinning current is proposed to reduce the residual offset of the Hall device.

Contents of the invention

The purpose of the present invention is to provide a Hall device applied to a three-dimensional Hall sensor and its offset elimination method. By improving and innovating the structure of the horizontal Hall device and the vertical Hall device, its performance is improved so that it can It is applied to a monolithically integrated three-dimensional Hall sensor; and the method of the invention can realize the elimination of the offset voltage, so that the three-dimensional detection of the magnetic field can be realized through a single chip, which is of great help to the application of the magnetic field detection.

In order to achieve the above object, the technical solution of the present invention is: a Hall device applied to a three-dimensional Hall sensor, which can be integrated on a chip to realize a monolithic integrated three-dimensional Hall sensor. The Hall device includes a horizontal Hall sensor. Hall device and vertical Hall device.

In an embodiment of the present invention, the horizontal Hall device includes a P-type substrate layer, an N well layer, and a P+ implant layer arranged sequentially from bottom to top, and the P+ implant layer does not completely cover the N well layer to expose The four corners of the N well layer also include the N+ injection region layer arranged at the four corners of the N well layer and the metal layer covering the P+ injection region layer and the N+ injection region layer, and the N well layer is used as the active region of the horizontal Hall device. , the N+ implantation zone layer is used as the contact end of the horizontal Hall device.

In an embodiment of the present invention, a cavity is opened on the top of the P-type substrate layer to set the N well layer, so that the N well layer is completely placed in the cavity of the P-type substrate layer.

In an embodiment of the present invention, the P-type substrate layer and the P+ implantation region layer are grounded.

In an embodiment of the present invention, the vertical Hall device includes a P-type substrate layer, a P well layer, a deep N well layer, a P+ injection region layer, and an N+ implant region layer, and a step is opened on the upper part of the P-type substrate layer. type cavity, the middle part of the stepped cavity is provided with the deep N well layer, and the periphery of the stepped cavity is provided with the P well layer, so that the P well layer surrounds the deep N well layer; the P type substrate layer The P+ implantation layer is also set on the top to surround the P well layer; there are 5 N+ implantation layers and are arranged on the deep N well layer at intervals, and a P+ implantation layer is also arranged between each N+ implantation layer; The deep N well layer is used as the active area of the vertical Hall device, and the N+ injection region layer is used as the contact terminal of the vertical Hall device.

In an embodiment of the present invention, the opening width of the P well ring formed by the P well layer increases from small to large from the N+ implantation layer at the middle position to the N+ implantation layer at both sides.

The present invention also provides an offset elimination method based on the above-mentioned Hall device, which is an offset elimination method combining orthogonal coupling and rotating current, and the specific implementation is as follows:

The Hall device is equivalent to a Wheatstone bridge, and the two Hall devices are coupled orthogonally, that is, the first end of the first Wheatstone bridge and the first end of the second Wheatstone bridge are connected to the MOS The drain terminals of the tube switches M1 and M5, the second terminal of the first Wheatstone bridge and the second terminal of the second Wheatstone bridge are connected to the drain terminals of the MOS tube switches M2 and M6, and the drain terminals of the first Wheatstone bridge The third end and the third end of the second Wheatstone bridge are connected to the drain ends of the MOS tube switches M4 and M7, and the fourth end of the first Wheatstone bridge is connected to the fourth end of the second Wheatstone bridge To the drain terminals of MOS tube switches M3 and M8, the source terminal of M1 and the source terminal of M2 are connected to VDD, the source terminal of M3 and the source terminal of M4 are connected to GND, the gate terminal of M1, the gate terminal of M2, and the M3 The gate terminal of M4 and the gate terminal of M4 are respectively connected to CLK0, CLK1, CLK1B, CLK0B clock signals, wherein CLK0 and CLK1 are a pair of non-overlapping complementary clocks; The source terminals of M6 and M6 are connected as the first voltage output terminal, the source terminals of M7 and M8 are connected as the second voltage output terminal,

Then combined with the rotating current technology, in the first phase stage of the rotating current technology, that is, when the clock signal CLK0 is at a low level, M1 and M4 are turned on, and the current flows from top to bottom. At this time, the output voltage is:

V _OUT = V _hall + V _offset (1)

In the second phase phase of the rotating current technology, that is, when the clock signal CLK1 is at a low level, M2 and M3 are turned on, and the current flows from right to left. At this time, the output voltage is:

V _OUT ＝-V _hall +V _offset (2)

From (1) and (2), it can be seen that the polarity of the output Hall voltage V _Hall changes in the two phases, while the polarity of the offset voltage V _offset remains unchanged; therefore, after subtraction by the subsequent signal processing circuit , can effectively suppress the imbalance.

Compared with the prior art, the present invention has the following beneficial effects: the present invention improves and innovates the structure of the horizontal Hall device and the vertical Hall device, improves its performance, and enables it to be applied to monolithically integrated three-dimensional Hall devices. Er sensor; and the method of the present invention can realize the elimination of the offset voltage, so that the three-dimensional detection of the magnetic field can be realized through a single chip, which is of great help to the application of the magnetic field detection.

Description of drawings

Figure 1 is a structural diagram of a traditional horizontal Hall device.

Fig. 2 is a structural diagram of an improved horizontal Hall device applied to a three-dimensional Hall sensor.

FIG. 3 is a cross-sectional view of FIG. 2 .

FIG. 4 is a structural diagram of a conventional vertical Hall device.

FIG. 5 is a structural diagram of an improved vertical Hall device applied to a three-dimensional Hall sensor.

Figure 6 is a model diagram of a Wheatstone bridge.

FIG. 7 is a top view of an improved vertical Hall device.

Figure 8 is a schematic diagram of the orthogonal coupling technology

Figure 9 is a schematic diagram of spinning current technology

Figure 10 is a schematic diagram of the orthogonal coupling spinning current technology

Detailed ways

The technical solution of the present invention will be specifically described below in conjunction with the accompanying drawings.

The invention provides a Hall device applied to a three-dimensional Hall sensor, which can be integrated on a chip to realize a monolithic integrated three-dimensional Hall sensor, and the Hall device includes a horizontal Hall device and a vertical Hall device .

The horizontal Hall device includes a P-type substrate layer, an N well layer, and a P+ injection region layer arranged sequentially from bottom to top, and the P+ injection region layer does not completely cover the N well layer to expose the four corners of the N well layer. The N+ injection region layer at the four corners of the N well layer and the metal layer covering the P+ injection region layer and the N+ injection region layer, the N well layer is used as the active region of the horizontal Hall device, and the N+ injection region layer is used as the horizontal type The contact terminal of the Hall device. A cavity is opened on the upper part of the P-type substrate layer to set the N well layer, so that the N well layer is completely placed in the cavity of the P-type substrate layer. The P-type substrate layer and the P+ implantation region layer are grounded.

The vertical Hall device includes a P-type substrate layer, a P well layer, a deep N well layer, a P+ injection region layer, and an N+ injection region layer, and a stepped cavity is opened on the upper part of the P-type substrate layer. The deep N well layer is set in the middle of the cavity, and the P well layer is set on the periphery of the stepped cavity, so that the P well layer surrounds the deep N well layer; the P+ implantation region is also set on the P-type substrate layer layer, to surround the P well layer; there are 5 N+ implantation layer layers and are arranged on the deep N well layer at intervals, and a P+ implantation layer is also arranged between each N+ implantation layer; the deep N well layer is used as a vertical The active region of the type Hall device, and the N+ injection region layer is used as the contact terminal of the vertical type Hall device. The opening width of the P well ring formed by the P well layer increases from small to large from the N+ implantation region layer at the middle position to the N+ implantation region layers on both sides.

The present invention also provides an offset elimination method based on the above-mentioned Hall device, which is an offset elimination method combining orthogonal coupling and rotating current, and the specific implementation is as follows:

The Hall device is equivalent to a Wheatstone bridge, and the two Hall devices are coupled orthogonally, that is, the first end of the first Wheatstone bridge and the first end of the second Wheatstone bridge are connected to the MOS The drain terminals of the tube switches M1 and M5, the second terminal of the first Wheatstone bridge and the second terminal of the second Wheatstone bridge are connected to the drain terminals of the MOS tube switches M2 and M6, and the drain terminals of the first Wheatstone bridge The third end and the third end of the second Wheatstone bridge are connected to the drain ends of the MOS tube switches M4 and M7, and the fourth end of the first Wheatstone bridge is connected to the fourth end of the second Wheatstone bridge To the drain terminals of MOS tube switches M3 and M8, the source terminal of M1 and the source terminal of M2 are connected to VDD, the source terminal of M3 and the source terminal of M4 are connected to GND, the gate terminal of M1, the gate terminal of M2, and the M3 The gate terminal of M4 and the gate terminal of M4 are respectively connected to CLK0, CLK1, CLK1B, CLK0B clock signals, wherein CLK0 and CLK1 are a pair of non-overlapping complementary clocks; The source terminals of M6 and M6 are connected as the first voltage output terminal, the source terminals of M7 and M8 are connected as the second voltage output terminal,

Then combined with the rotating current technology, in the first phase stage of the rotating current technology, that is, when the clock signal CLK0 is at a low level, M1 and M4 are turned on, and the current flows from top to bottom. At this time, the output voltage is:

V _OUT = V _hall + V _offset (1)

In the second phase phase of the rotating current technology, that is, when the clock signal CLK1 is at a low level, M2 and M3 are turned on, and the current flows from right to left. At this time, the output voltage is:

V _OUT ＝-V _hall +V _offset (2)

From (1) and (2), it can be seen that the polarity of the output Hall voltage V _Hall changes in the two phases, while the polarity of the offset voltage V _offset remains unchanged; therefore, after subtraction by the subsequent signal processing circuit , can effectively suppress the imbalance.

The following is the specific implementation process of the present invention.

The invention mainly includes horizontal and vertical Hall devices and offset elimination technology applied to three-dimensional Hall sensors.

In order to improve the problems of low sensitivity and large initial offset of the traditional Hall device, the invention optimizes and innovates the structure of the Hall device. The structure of the traditional horizontal Hall device is shown in Figure 1. The device uses the N well as the active region, and heavily doped N implants are performed at the four corners of the device as the contact terminals of the Hall device. The horizontal type of this structure The Hall device has large offset and low sensitivity, and is not suitable for the front end of the three-dimensional Hall sensor. Therefore, on this basis, the present invention improves the structure and improves its performance. The structural diagrams of the horizontal Hall device applied to the three-dimensional Hall device are shown in Figures 2 and 3. The specific steps of device fabrication: Electron injection is performed on the silicon wafer of the P-type substrate to form a well, which is used as the active area of the Hall device . Then, a highly doped P implant is performed on the surface of the Hall device to form a P+ shielding layer to reduce the effective thickness of the device. In this way, the sensitivity of the horizontal Hall device can be improved. In addition, grounding the P+ layer and the P substrate in the horizontal Hall device can effectively reduce device misalignment and surface parasitic effects of the device. Subsequently, heavily doped N implants are performed at the four corners of the Hall device to form an N+ contact region as the contact terminal of the Hall device. Finally, a layer of metal is covered on the surface of the Hall device to reduce the interference of noise from other modules inside the chip on the Hall device.

The traditional five-contact-hole vertical Hall device is shown in Figure 4. It can be seen that the five-contact-hole vertical Hall device has five electrodes, but usually, the Hall device has only four electrodes, and two of them are biased. set electrode and two Hall voltage sensing electrodes. Therefore, the two outermost contact holes of the vertical Hall device with five contact holes are usually shorted together as an electrode. Because under the same process, the performance of the vertical Hall device is lower than that of the horizontal Hall device. In order to improve the performance of the vertical Hall device, it is necessary to improve the conventional vertical Hall device. The structural diagram of the vertical Hall device applied to the three-dimensional Hall device in the present invention is shown in Figure 5, using a deep N well as the active region of the vertical Hall device can improve the geometric factor of the device, thereby improving the sensitivity of the device . At the same time, the present invention utilizes the P well provided in the process to wrap a circle around the outer side of the deep N well as a protection ring for the device, and overlaps with the deep N well to control the overlapping distance between the two. On the one hand, this method can limit the lateral size of the Hall device, and on the other hand, it helps to reduce the lateral expansion effect of deep N well implantation, so that the current flows deeper into the device, thereby improving the sensitivity of the device. In addition, in order to reduce the impurity concentration inside the deep N well and increase the effective depth of the deep N well, by optimizing the width of the N+ contact hole and performing local P+ implantation between the N+ contact holes and adjusting the distance between the P+ implantation region and the N+ contact hole , using the impurity compensation function of the P+ implantation region to reduce the impurity concentration inside the N well. This method can not only effectively improve the Gaussian distribution of impurities inside the deep N well, but also reduce the short-circuit effect between contact holes, thereby promoting the current to flow deep inside the device, and helping to increase the effective active region depth and reduce the offset of the device.

But in fact, the initial offset of the vertical Hall device is relatively large, which is often beyond the processing range of the circuit, so it is necessary to further reduce its initial offset. The Hall device can be equivalent with the Wheatstone bridge model, as shown in Figure 6, the bridge model consists of four equivalent resistors R1, R2, R3, R4. For the horizontal Hall device, ideally, since the horizontal Hall device has four-fold rotational symmetry, the four resistors R1, R2, R3, and R4 of the resistance bridge are equal, so there is no offset. But for the five-hole vertical Hall device, the resistances on the resistive bridge are not equal, so the initial offset of the vertical Hall device is much larger than that of the horizontal Hall device. Therefore, in order to reduce the initial misadjustment of the vertical Hall device, the present invention innovates the structure of the vertical Hall device to make the four equivalent resistances R1, R2, and R3 on the bridge model of the five-contact hole vertical Hall device as far as possible , R4 are close to equal, so that a certain initial offset can be reduced. As shown in Figure 7, the present invention is based on the five-contact-hole vertical Hall device structure proposed above, and then carries out an innovative design, by changing the shape of the P-well on the inner edge of the device, the opening width of the P-well ring surrounded by the inner edge of the device is It is larger at the external contact than the internal contact. In this way, the equivalent resistances R1, R2, R3, and R4 on the resistor bridge can be closer to equal, which helps to reduce the initial offset of the device.

In order to eliminate the residual offset of the Hall device, the present invention proposes an offset elimination technology combining orthogonal coupling and rotating current.

Quadrature coupling technology is an offset cancellation technology applied to Hall devices. As shown in Figure 8, the Hall device is equivalent to a Wheatstone bridge. In the figure, the two Hall devices are orthogonally coupled, and it can be seen that the orthogonal coupling means that the bias directions of the two Hall devices are staggered by 90° from each other. Ideally, the four equivalent resistors on a Wheatstone bridge are the same. But in reality, the four equivalent resistances in the bridge are not exactly the same, so an offset voltage will be generated at the output. However, the output offset voltages of the Hall devices in the two bias directions are opposite in polarity and have the same magnitude, so the offset can be eliminated by adding the two. The offset voltage of the Hall device can be expressed as:

The basic working principle of the spinning current technique is similar to that of the quadrature coupling technique, but it can be accomplished using only a single Hall device. As shown in Figure 9, the Hall device switches the working mode through the mutual conversion of the four ports. By periodically switching the Hall device between two different bias directions and summing the two signals, the offset signals of the two states usually have opposite signs, while the Hall output voltage has the same sign. Therefore, after summing, a large part of the offset of the Hall device is canceled.

When the bias current flows from top to bottom, the output voltage of the Hall device is:

V _OUT =V _H +V _OP (2)

When the bias current rotates 90° and flows from left to right, the voltage at the output of the Hall device is:

V _OUT =V _H -V _OP (3)

It can be seen that the sign of the Hall voltage of the two phases is the same, but the sign of the offset voltage is opposite, so the addition of the two output voltages can suppress the offset voltage.

In order to further reduce the residual offset, the present invention combines the above two techniques to propose an orthogonally coupled spinning current technique, which can more effectively reduce the residual offset of the Hall device. As shown in Figure 10, two Hall devices are used for orthogonal coupling, combined with spinning current technology, where CLK0 and CLK1 are a pair of non-overlapping complementary clocks. The phases of CLK0b and CLK1b are opposite to those of CLK0 and CLK1 respectively. The clock signals CLK0, CLK0b, CLK1, CLK1b control the turn-on and turn-off of the MOS transistor switches M1-M4.

In the first phase stage of the rotating current technology, that is, when the clock signal CLK0 is at a low level, the MOS transistors M1 and M4 are turned on, and the current flows from top to bottom. At this time, the output voltage is:

V _OUT =V _hall +V _offse0 (4)

In the second phase stage, that is, when the clock signal CLK1 is at low level, the MOS transistors M2 and M3 are turned on, and the current flows from right to left. At this time, the output voltage is:

V _OUT ＝-V _hall +V _offset (5)

It can be seen from (4) and (5) that the polarity of the output Hall voltage V _Hall changes in the two phases, while the polarity of the offset voltage V _offset remains unchanged. Therefore, the offset can be effectively suppressed after being subtracted by the subsequent signal processing circuit.

The above are the preferred embodiments of the present invention, and all changes made according to the technical solution of the present invention, when the functional effect produced does not exceed the scope of the technical solution of the present invention, all belong to the protection scope of the present invention.

Claims (7)

1. a kind of hall device being applied to three-dimensional Hall sensor, which is characterized in that can be integrated on a chip, realize monolithic Integrated three-dimensional Hall sensor, the hall device includes horizontal type hall device and vertical-type hall device.

2. the hall device according to claim 1 for being applied to three-dimensional Hall sensor, which is characterized in that the horizontal type Hall device includes the P type substrate layer set gradually from the bottom up, N well layer, P+ injection region layer, and P+ injections region layer not exclusively covers N well layer further includes being set to the N+ injection region layer of N well layer quadrangle and being overlying on P+ injection region layer to note with N+ to expose N well layer quadrangle Enter the metal layer in region layer, active area of the N well layer as horizontal type hall device, N+ injects region layer as horizontal type Hall The contact jaw of device.

3. the hall device according to claim 2 for being applied to three-dimensional Hall sensor, which is characterized in that the p-type lining Bottom top offers a cavity, the N well layer is arranged so that N well layer is completely disposed in the cavity of P type substrate layer.

4. the hall device according to claim 2 or 3 for being applied to three-dimensional Hall sensor, which is characterized in that the p-type Substrate layer and P+ injection region layer ground connection.

5. the hall device according to claim 1 for being applied to three-dimensional Hall sensor, which is characterized in that the vertical-type Hall device includes P type substrate layer, p-well layer, deep N-well layer, P+ injections region layer, N+ injection region layer, and P type substrate layer top is opened Equipped with ladder cavity, the deep N-well layer is arranged in the middle part of the ladder cavity, and the P is arranged in the circumference of ladder cavity Well layer, so that p-well layer ring packet deep N-well layer；The P+ injections region layer is also set up on P type substrate layer, with ring packet p-well layer；N+ is noted Enter region layer to be 5 and be spaced on deep N-well layer, P+ injection region layer is additionally provided between each N+ injections region layer；The deep N-well Active area of the layer as vertical-type hall device, N+ inject contact jaw of the region layer as vertical-type hall device.

6. the hall device according to claim 5 for being applied to three-dimensional Hall sensor, which is characterized in that p-well layer is formed P-well ring, opening width from the N+ in centre position inject region layer to the N+ of both sides injection region layer from small to large.

7. a kind of imbalance removing method based on any hall device of claim 1 to 6, it is characterised in that：This method is It is orthogonal to couple the imbalance removing method being combined with rotatory current, it is implemented as follows：

Hall device is equivalent at Wheatstone bridge, and two hall devices are subjected to orthogonal coupling, i.e. the first Wheatstone bridge First end be connected with the first end of the second Wheatstone bridge and be connected to the drain terminal of metal-oxide-semiconductor switch M1, M5, the first Wheatstone bridge Second end is connected with the second end of the second Wheatstone bridge is connected to the drain terminal of metal-oxide-semiconductor switch M2, M6, and the of the first Wheatstone bridge Three ends are connected with the third end of the second Wheatstone bridge is connected to the drain terminal of metal-oxide-semiconductor switch M4, M7, and the 4th of the first Wheatstone bridge the End is connected with the 4th end of the second Wheatstone bridge is connected to the drain terminal of metal-oxide-semiconductor switch M3, M8, and the source of M1, the source of M2 are connected It is connected to VDD, the source of M3, the source of M4, which are connected, is connected to GND, the grid end of M1, the grid end of M2, the grid end of M3, the grid end of M4 difference It is connected to CLK0, CLK1, CLK1B, CLK0B clock signal, wherein CLK0 and CLK1 are a pair of non-overlapping complementary clocks；CLK0B, The opposite in phase with CLK0 and CLK1, the source of M5, the source of M6 are connected as first voltage output end, M7 CLK1B respectively Source, the source of M8 is connected as second voltage output end；

Rotatory current technology is then combined, in the first phase stage of rotatory current technology, i.e. clock signal CLK0 is low level When, M1 and M4 conductings, electric current flow from the top down, and output voltage is at this time：

V_OUT=V_hall+V_offset (1)

In the second phase stage of rotatory current technology, i.e. when clock signal CLK1 is low level, M2 and M3 conductings, electric current is from the right side It flows to the left, output voltage is at this time：

V_OUT=-V_hall+V_offset (2)

The output end Hall voltage V it can be seen from (1) and (2)_HallIt changes in the polarity of two phases, and offset voltage V_offsetPolarity it is constant always；Therefore after follow-up signal processing circuit subtracts each other, imbalance can be effectively inhibited.