CN113364274A - Low-area high-current-efficiency charge pump circuit and nonvolatile memory - Google Patents
Low-area high-current-efficiency charge pump circuit and nonvolatile memory Download PDFInfo
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- CN113364274A CN113364274A CN202110607482.7A CN202110607482A CN113364274A CN 113364274 A CN113364274 A CN 113364274A CN 202110607482 A CN202110607482 A CN 202110607482A CN 113364274 A CN113364274 A CN 113364274A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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Abstract
The invention discloses a charge pump circuit with low area and high current efficiency and a nonvolatile memory, comprising at least one stage of charge pump, wherein the unit area capacitance value of a charge-discharge capacitor of the charge pump is larger than that of a high-voltage grid oxide layer capacitor; in the technical scheme, on the premise that the withstand voltage value of the charge-discharge capacitor of the charge pump is larger than the voltage difference between the upper electrode plate and the lower electrode plate of the charge-discharge capacitor of the charge pump, the charge-discharge capacitor of the charge pump can adopt any one of a low-voltage grid oxide layer capacitor, a low-voltage grid oxide layer capacitor and an MOM capacitor which are formed in parallel, a PIP capacitor and an MOM capacitor which are formed in parallel and a high-voltage grid oxide layer capacitor and an MOM capacitor which are formed in parallel as required, on the basis of not increasing the layout area of a chip, the unit area capacitance value of the charge-discharge capacitor of the charge pump is improved, and the current efficiency of the charge pump is further improved.
Description
Technical Field
The present invention relates to the field of non-volatile flash memory technologies, and in particular, to a charge pump circuit with low area and high current efficiency and a non-volatile memory.
Background
The NOR FLASH needs to carry out different high-voltage bias on word lines/bit lines/a substrate during read/write/erase operation, the bias voltage needs 10V to-10V when the bias voltage is highest, and the external supply voltage is generally in the range of 1.6V to 3.6V, so that the requirement of 10V to-10V is met by a charge pump circuit for carrying out boosting or reducing voltage on the basis of the external supply voltage.
A general charge pump circuit is composed of a capacitor/switch/clock, and an on-chip capacitor of the NOR FLASH is generally implemented by using a gate oxide layer of a high-voltage MOS device because the on-chip capacitor needs to withstand a high voltage of 10V to-10V, as shown in the following fig. 1, which is an example of a high-voltage N-type MOS device: the high-voltage MOS grid electrode of the current mainstream NOR FLASH chip manufacturer has the characteristics that the thickness of a high-voltage grid electrode oxidation layer is 170A; the capacitance per unit area of the high-voltage grid oxide layer is 2 fF/um ^ 2.
1. In the competitive memory market, increasing the capacitance per unit area means reducing the chip area and enhancing the competitiveness, but the capacitance per unit area of the high voltage gate oxide layer is relatively fixed, and it is difficult to further increase the capacitance per unit area.
2. As shown in fig. 1, a source terminal and a drain terminal of another plate of the high-voltage MOS device capacitor form a P/N node on the substrate, which brings extra parasitic capacitance, and the useless parasitic capacitance is charged and discharged by a clock continuously during the operation of the charge pump, so that the current efficiency of the charge pump circuit is greatly reduced, and the requirement cannot be met.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a charge pump circuit with low area and high current efficiency and a nonvolatile memory, aiming at solving the problem that the unit area capacitance value of a high-voltage grid oxide layer capacitor adopted by the charge pump in the existing NOR FLASH is too small to meet the production requirement.
The technical scheme of the invention is as follows: a charge pump circuit with low area and high current efficiency comprises at least one stage of charge pump, wherein the unit area capacitance value of the charge-discharge capacitance of the charge pump is larger than that of the high-voltage grid oxide layer capacitance.
The charge pump circuit with low area and high current efficiency is characterized in that the withstand voltage value of a charge and discharge capacitor of the charge pump is larger than the voltage difference of an upper electrode plate and a lower electrode plate of the charge and discharge capacitor of the charge pump.
The charge pump circuit with low area and high current efficiency is characterized in that a charge and discharge capacitor of the charge pump adopts a low-voltage grid oxide layer capacitor.
The charge pump circuit with low area and high current efficiency is characterized in that a charge and discharge capacitor of the charge pump is formed by connecting a low-voltage grid oxide layer capacitor and an MOM capacitor in parallel.
The charge pump circuit with low area and high current efficiency is characterized in that a charge-discharge capacitor of the charge pump adopts a PIP capacitor.
The charge pump circuit with low area and high current efficiency is characterized in that a charge-discharge capacitor of the charge pump is formed by connecting a PIP capacitor and an MOM capacitor in parallel.
The charge pump circuit with low area and high current efficiency is characterized in that the PIP capacitor comprises a PIP capacitor applied to a positive voltage charge pump and a PIP capacitor applied to a negative voltage charge pump.
The charge pump circuit with low area and high current efficiency is characterized in that a charge and discharge capacitor of the charge pump is formed by connecting a high-voltage grid oxide layer capacitor and an MOM capacitor in parallel.
The charge pump circuit with low area and high current efficiency comprises at least two stages, wherein the charge pump of each stage adopts any one of a low-voltage grid oxide layer capacitor, a low-voltage grid oxide layer capacitor and an MOM capacitor which are formed in parallel, a PIP capacitor and an MOM capacitor which are formed in parallel, and a high-voltage grid oxide layer capacitor and an MOM capacitor which are formed in parallel.
A non-volatile memory comprising a low area, high current efficiency charge pump circuit as claimed in any one of the preceding claims.
The invention has the beneficial effects that: the invention provides a charge pump circuit with low area and high current efficiency and a nonvolatile memory, on the premise that the withstand voltage value of a charge-discharge capacitor of the charge pump is larger than the voltage difference of an upper electrode plate and a lower electrode plate of the charge-discharge capacitor of the charge pump, the charge-discharge capacitor of the charge pump can be formed by connecting a low-voltage grid oxide layer capacitor, a low-voltage grid oxide layer capacitor and an MOM capacitor in parallel, connecting a PIP capacitor, a PIP capacitor and the MOM capacitor in parallel and connecting a high-voltage grid oxide layer capacitor and the MOM capacitor in parallel according to requirements, and on the basis of not increasing the layout area of a chip, the unit area capacitance value of the charge-discharge capacitor of the charge pump is improved, so that the current efficiency of the charge pump is improved.
Drawings
Fig. 1 is a schematic diagram of a high voltage N-type MOS device in the prior art.
Fig. 2 is a schematic diagram of a low area, high current efficiency charge pump circuit of the present invention.
Fig. 3 is a schematic diagram of a PIP capacitor applied to a positive voltage charge pump in the present invention.
Fig. 4 is a schematic diagram of a PIP capacitor applied to a negative voltage charge pump in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 2, a charge pump circuit with low area and high current efficiency includes at least one stage of charge pump, and the charge pump has a charge-discharge capacitor with a unit area capacitance value larger than that of the high-voltage gate oxide layer capacitor.
Example 1
And the charge and discharge capacitor of the charge pump adopts a low-voltage grid oxide layer capacitor.
In the embodiment, the low-voltage grid oxide layer capacitor is used as the charge and discharge capacitor of the charge pump, so that the unit area capacitance value of the charge and discharge capacitor of the charge pump can be improved; the current mainstream NOR FLASH manufacturers manufacture 1.8V low voltage gate oxide capacitance with the following parameters:
the thickness of the low-voltage grid oxide layer is 50A;
the unit area capacitance of the low-voltage grid oxide layer is 8fF/um ^ 2;
the withstand voltage of the low-voltage grid oxide layer is 4V;
compared with the high-voltage gate oxide layer capacitor, the unit area capacitance of the low-voltage gate oxide layer capacitor is four times that of the high-voltage gate oxide layer capacitor, and the ideal area is reduced to 1/4.
However, because of the voltage resistance limitation of the low voltage gate oxide capacitor, the method can only be applied to a charge pump with low bias voltage. In an ideal case, each stage of charge pump can raise an external power supply voltage (denoted as VCC) by 1 time, and assuming that in the nth stage of charge pump, the voltage of the upper plate of the capacitor is (N +1) × VCC, because the synchronous swing of the lower plate and the upper plate of the capacitor is VCC, the voltage difference between the upper plate and the lower plate of the capacitor is (N +1) × VCC-VCC = N × VCC under an ideal case, and according to the withstand voltage limit of the low-voltage gate oxide layer capacitor, the operation safety of the low-voltage gate oxide layer capacitor is ensured, so that N × VCC < the withstand voltage value of the low-voltage gate oxide layer capacitor, that is, the low-voltage gate oxide layer capacitor can only be applied to the charge pump in which the voltage difference between the upper plate and the lower plate of the capacitor is smaller than the withstand voltage value of the low-voltage gate oxide layer capacitor.
Example 2
The charge-discharge capacitor of the charge pump is formed by connecting a low-voltage grid oxide layer capacitor and an MOM (metal-oxide-metal, MOM, metal-oxide-metal) capacitor in parallel, and the MOM capacitor can be connected with any device capacitor in parallel without consuming the area of a layout, so that the area can be further reduced and the current efficiency of the charge pump can be improved.
The parameters of MOM capacitors manufactured by mainstream manufacturers are as follows:
the MOM capacitor has withstand voltage of more than 10V;
the unit area capacitance of the MOM capacitor is 0.9fF/um ^ 2.
Example 3
Wherein, the charge-discharge capacitor of the charge pump adopts a PIP (Poly Inter poly direct Poly) capacitor.
Fig. 3 (in fig. 3, 1 is a control gate + substrate, which is a segment of the capacitor driven by a clock due to a relatively large parasitic capacitance, and 2 is a floating gate, which is a current output path connected to the charge pump at the other end of the capacitor due to a relatively small parasitic capacitance) is a schematic diagram of a PIP capacitor for a positive voltage charge pump, which uses a parallel connection of a TUNOX capacitor between the Floating Gate (FG) and the HVNW (high voltage N well) and an ONO capacitor between the floating gate and the Control Gate (CG) for the purpose of increasing the capacitance. The parameters of PIP capacitors manufactured by mainstream manufacturers are as follows:
TUNOX capacitance thickness of 100A;
the thickness of the ONO capacitor is 140A;
the unit area capacitance of the TUNOX + ONO capacitor is 6fF ^ 2;
compared with the high-voltage gate oxide layer capacitor, the unit area capacitance of the PIP capacitor is three times that of the high-voltage gate oxide layer capacitor, and the ideal area is reduced to 1/3.
The floating grid of the positive voltage charge pump is used as the upper pole plate of the capacitor to apply high voltage, so electrons formed by the HVNW are accumulated into an accumulated capacitor, and the source and drain ends are both N-type, so the substrate and the source and drain ends are naturally connected, the substrate does not need to be contacted independently, and the area of a layout is further reduced.
Fig. 4 (in fig. 4, 3 is a control gate + substrate, which is a section of the capacitor driven by a clock because of a relatively large parasitic capacitance, and 4 is a floating gate, which is a section of the capacitor driven by a clock because of a relatively small parasitic capacitance, and which is connected to a current output path of the charge pump at the other end of the capacitor) is a schematic diagram of a PIP capacitor used for a negative voltage charge pump, which uses a parallel connection of a TUNOX capacitor between the Floating Gate (FG) and a TPW (high voltage p-well) and an ONO capacitor between the floating gate and the Control Gate (CG) to increase the capacitance. The parameters of PIP capacitors manufactured by mainstream manufacturers are as follows:
TUNOX capacitance thickness of 100A
ONO capacitor thickness of 140A
Unit area capacitance of TUNOX + ONO capacitance of 6fF ^2
Compared with the high-voltage gate oxide layer capacitor, the unit area capacitance of the PIP capacitor is three times that of the high-voltage gate oxide layer capacitor, and the ideal area is reduced to 1/3.
The floating grid of the negative-pressure charge pump is used as an upper polar plate of the capacitor to apply negative high voltage, so that holes formed by TPW are accumulated into an accumulated capacitor, and the substrate and the source and drain ends are naturally connected because the source and drain ends are all in a P type, and the substrate does not need to be contacted independently, so that the area of a layout is further reduced.
The typical withstand voltage of the PIP capacitor is 7V to 8V, and the operation safety of the low PIP capacitor is ensured according to the withstand voltage limit of the PIP capacitor, so that N × VCC < the withstand voltage value of the PIP capacitor (i.e., N × VCC <7V to 8V), that is, the PIP capacitor can only be applied to a charge pump in which the voltage difference between the upper and lower plates of the capacitor is smaller than the withstand voltage value of the PIP capacitor.
Example 4
The charge-discharge capacitor of the charge pump is formed by connecting a PIP capacitor and an MOM capacitor in parallel, and the MOM capacitor can be connected in parallel with any device capacitor without consuming the layout area, so that the area can be further reduced and the current efficiency of the charge pump can be further improved.
The parameters of MOM capacitors manufactured by mainstream manufacturers are as follows:
the MOM capacitor has withstand voltage of more than 10V;
the unit area capacitance of the MOM capacitor is 0.9fF/um ^ 2.
As shown in fig. 3 and 4, M1 (metal 1) and M2 (metal 2) form another part of useful capacitance through the sidewall capacitance between the same layer of metal and insulating layer, and the voltage resistance is ensured through reasonable spacing.
Example 5
The charge-discharge capacitor of the charge pump is formed by connecting a high-voltage grid oxide layer capacitor and an MOM capacitor in parallel, and the MOM capacitor can be connected with any device capacitor in parallel without consuming the area of a layout, so that the area can be further reduced and the current efficiency of the charge pump can be improved.
The parameters of MOM capacitors manufactured by mainstream manufacturers are as follows:
the MOM capacitor has withstand voltage of more than 10V;
the unit area capacitance of the MOM capacitor is 0.9fF/um ^ 2.
The unit area capacitance value of the MOM capacitor can reach 50% of that of the high-voltage grid oxide layer capacitor, and the current efficiency of the charge pump can be increased on the basis of not consuming the layout area.
In some embodiments, when the low-area high-current-efficiency charge pump circuit includes a multi-stage charge pump, the capacitor in any one of embodiments 1 to 5 is selected as the charge pump capacitor in each stage of charge pump according to actual needs and the limitation of the voltage difference between the upper and lower plates of the capacitor in the corresponding charge pump, so that the same embodiment mode can be simultaneously adopted in the multi-stage charge pump, or the capacitors in different embodiment modes can be combined between different charge pumps in the multi-stage charge pump.
The technical scheme also protects a nonvolatile memory which comprises the charge pump circuit with low area and high current efficiency.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. The charge pump circuit with low area and high current efficiency is characterized by comprising at least one stage of charge pump, wherein the unit area capacitance value of a charge-discharge capacitor of the charge pump is larger than that of a high-voltage grid oxide layer capacitor.
2. The charge pump circuit of claim 1, wherein the voltage resistance of the charge-discharge capacitor of the charge pump is greater than the voltage difference between the upper and lower plates of the charge-discharge capacitor of the charge pump.
3. The low area, high current efficiency charge pump circuit of claim 2, wherein the charge pump charge-discharge capacitor is a low voltage gate oxide capacitor.
4. The low area, high current efficiency charge pump circuit of claim 3, wherein the charge pump charge and discharge capacitors are formed by low voltage gate oxide capacitors in parallel with the MOM capacitor.
5. The low area, high current efficiency charge pump circuit of claim 2, wherein the charge pump charge-discharge capacitor is a PIP capacitor.
6. The low area high current efficiency charge pump circuit of claim 5, wherein the charge pump charge-discharge capacitor is formed by parallel connection of PIP capacitor and MOM capacitor.
7. The low area, high current efficiency charge pump circuit of claim 6, wherein said PIP capacitors include a PIP capacitor applied to a positive voltage charge pump and a PIP capacitor applied to a negative voltage charge pump.
8. The low area, high current efficiency charge pump circuit of claim 2, wherein the charge pump charge and discharge capacitors are formed by high voltage gate oxide capacitors in parallel with the MOM capacitors.
9. The low area high current efficiency charge pump circuit of claim 2, wherein said charge pump comprises at least two stages, and the charge and discharge capacitance of each stage of charge pump is formed by connecting a low voltage gate oxide capacitor, a low voltage gate oxide capacitor and an MOM capacitor in parallel, a PIP capacitor and an MOM capacitor in parallel, or a high voltage gate oxide capacitor and an MOM capacitor in parallel.
10. A non-volatile memory comprising the low-area high-current-efficiency charge pump circuit of any one of claims 1 to 9.
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| CN202110607482.7A CN113364274A (en) | 2021-06-01 | 2021-06-01 | Low-area high-current-efficiency charge pump circuit and nonvolatile memory |
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| CN202110607482.7A CN113364274A (en) | 2021-06-01 | 2021-06-01 | Low-area high-current-efficiency charge pump circuit and nonvolatile memory |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6157252A (en) * | 1998-09-09 | 2000-12-05 | The Engineering Consortium, Inc. | Battery polarity insensitive integrated circuit amplifier |
| CN101197371A (en) * | 2006-12-06 | 2008-06-11 | 上海华虹Nec电子有限公司 | Coupling capacitance structure and manufacturing method thereof |
| CN103762157A (en) * | 2014-01-20 | 2014-04-30 | 无锡紫芯集成电路系统有限公司 | Method for manufacturing capacitors with large unit capacitance in ordinary LOGIC process |
| US20150054867A1 (en) * | 2012-04-25 | 2015-02-26 | Hewlett-Packard Development Company, L.P. | Print nozzle amplifier with capacitive feedback |
-
2021
- 2021-06-01 CN CN202110607482.7A patent/CN113364274A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6157252A (en) * | 1998-09-09 | 2000-12-05 | The Engineering Consortium, Inc. | Battery polarity insensitive integrated circuit amplifier |
| CN101197371A (en) * | 2006-12-06 | 2008-06-11 | 上海华虹Nec电子有限公司 | Coupling capacitance structure and manufacturing method thereof |
| US20150054867A1 (en) * | 2012-04-25 | 2015-02-26 | Hewlett-Packard Development Company, L.P. | Print nozzle amplifier with capacitive feedback |
| CN103762157A (en) * | 2014-01-20 | 2014-04-30 | 无锡紫芯集成电路系统有限公司 | Method for manufacturing capacitors with large unit capacitance in ordinary LOGIC process |
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Application publication date: 20210907 |
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