CN113363154B - Method for forming semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure includes: providing a substrate, wherein the substrate is provided with a fin structure; forming a pseudo gate structure crossing the fin structure on the substrate, wherein the pseudo gate structure covers part of the top surface and the side wall surface of the fin structure; forming first grooves in fin structures on two sides of the pseudo gate structure; after forming the first groove, forming a first dielectric layer on the substrate, wherein the dummy gate structure is positioned in the first dielectric layer; removing the pseudo gate structure and the second fin portion layer covered by the pseudo gate structure, and forming gate openings in the first dielectric layer and between adjacent first fin portion layers; forming a gate structure in the gate opening, wherein the gate structure surrounds each first fin part layer; removing the first dielectric layer after forming the gate structure to expose the first groove; and after the first dielectric layer is removed, forming a source-drain doping layer in the first groove. The semiconductor structure formed by the method has better performance.

Description

Formation method of semiconductor structure

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background technique

With the development of semiconductor technology, the control ability of the traditional planar metal-oxide semiconductor field effect transistor on the channel current becomes weaker, resulting in serious leakage current. Fin Field Effect Transistor (FinFET) is an emerging multi-gate device, which generally includes a fin protruding from the surface of the semiconductor substrate, a gate structure covering part of the top surface and sidewall of the fin, located at the gate The source and drain doped regions in the fins on both sides of the pole structure. Compared with planar metal-oxide semiconductor field effect transistors, fin field effect transistors have stronger short-channel suppression capability and stronger operating current.

With the further development of semiconductor technology, the size of integrated circuit devices is getting smaller and smaller, and the traditional fin field effect transistor has limitations in further increasing the operating current. Specifically, since only the area close to the top surface and the sidewall of the fin is used as the channel region, the volume of the fin used as the channel region is relatively small, which is helpful for increasing the operating current of the fin field effect transistor. cause restrictions. Therefore, a fin field effect transistor with a gate-all-around (GAA) structure is proposed, which increases the volume used as the channel region and further increases the gate-all-around area of the channel. Structural FinFET operating current.

However, the performance of the fin field effect transistor with surrounding trench gate structure in the prior art needs to be improved.

Contents of the invention

The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which improves the stress of the source-drain doped layer, thereby improving the performance of the semiconductor structure.

In order to solve the above-mentioned technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate with a fin structure on the substrate, and the fin structure includes a plurality of composite layers overlapping along the normal direction of the surface of the substrate. Fin layers, each composite fin layer includes a second fin layer and a first fin layer located on the surface of the second fin layer; a dummy gate structure straddling the fin structure is formed on the base, The dummy gate structure covers part of the top surface and the sidewall surface of the fin structure; a first groove is formed in the fin structure on both sides of the dummy gate structure; after the first groove is formed, the Forming a first dielectric layer on the substrate, and the dummy gate structure is located in the first dielectric layer; removing the dummy gate structure and the second fin layer covered by the dummy gate structure, in the A gate opening is formed in the first dielectric layer and between adjacent first fin layers; a gate structure is formed in the gate opening, and the gate structure surrounds each first fin layer; the gate is formed After the structure, the first dielectric layer is removed to expose the first groove; after the first dielectric layer is removed, a source-drain doped layer is formed in the first groove.

Optionally, the method for forming the first groove includes: using the dummy gate structure as a mask, etching the fin structure until the substrate surface is exposed, and the fins on both sides of the dummy gate structure The first groove is formed in the fin structure.

Optionally, the method for forming the gate opening includes: removing the dummy gate structure, forming an initial gate opening in the first dielectric layer; removing the second fin layer exposed by the initial gate opening, so that The initial gate opening forms the gate opening.

Optionally, the bottom layer of the fin structure is the first fin layer; before forming the dummy gate structure, an isolation structure covering part of the fin structure is formed on the substrate, and the isolation structure The top surface of the first fin layer is lower than the top surface of the bottommost first fin layer.

Optionally, it further includes: after forming the first groove and before forming the first dielectric layer, removing part of the second fin layer exposed on the sidewall of the first groove, and A second groove is formed between the lower layers; a first sidewall film is formed in the second groove, on the surface of the isolation structure, and on the surface of the dummy gate structure; after the formation of the first sidewall film, a The first medium layer, and the first medium layer covers the surface of the first side wall membrane and the surface of the isolation structure.

Optionally, further comprising: after removing the first dielectric layer and before forming the source-drain doped layer, etching the first sidewall film until the sidewall surface of the first fin layer and the surface of the base are exposed , forming a first sidewall in the second groove; after forming the first sidewall, forming the source-drain doped layer, the source-drain doped layer covering the sidewall surface of the first sidewall and the first fin layer sidewall surface.

Optionally, the material of the first sidewall film is different from that of the first medium layer, and the material of the first sidewall film is different from that of the isolation structure; the material of the first medium layer Including: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride; the material of the first sidewall film includes: silicon oxide, silicon nitride, silicon oxynitride, carbon Silicon oxide, silicon carbonitride or silicon carbonitride; the material of the isolation structure includes: silicon oxide, silicon nitride, silicon nitride oxide, silicon carbide, silicon carbonitride or silicon carbonitride.

Optionally, the forming process of the first sidewall film includes: a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

Optionally, the method for forming the first dielectric layer includes: forming an initial dielectric film on the surface of the first sidewall film, the initial dielectric film covering the top surface and the sidewall surface of the dummy gate structure; etching The initial dielectric film until the top surface of the dummy gate structure is exposed, and the first dielectric layer is formed on the substrate.

Optionally, a first etching process is used to remove the first dielectric layer, and an etching rate of the first dielectric layer in the first etching process is greater than an etching rate of the first sidewall film.

Optionally, the first sidewall film is etched using a second etching process, and the etching rate of the first sidewall film in the second etching process is greater than the etching rate of the isolation structure .

Optionally, the material of the first fin layer is different from that of the second fin layer; the material of the first fin layer is single crystal silicon or single crystal silicon germanium; the material of the second fin layer The material is single crystal silicon or single crystal silicon germanium.

Optionally, the dummy gate structure includes: a dummy gate dielectric layer and a dummy gate layer located on the surface of the dummy gate dielectric layer; the method for forming the dummy gate structure includes: forming a dummy gate on the substrate The dummy gate dielectric layer film of the fin structure; the dummy gate film is formed on the dummy gate dielectric film; the dummy gate dielectric film and the dummy gate film are etched until the top surface of the fin structure is exposed, so that the The dummy gate dielectric film forms a dummy gate dielectric layer, and the dummy gate film forms a dummy gate layer to form the dummy gate structure.

Optionally, the dummy gate structure further includes: second sidewalls located on the dummy gate dielectric layer and the sidewall surfaces of the dummy gate layer.

Optionally, the gate structure includes: an interface layer, a gate dielectric layer located on the surface of the interface layer, and a gate electrode layer located on the surface of the gate dielectric layer; the method for forming the gate structure includes: An interface film is formed on the surface of the gate opening and the surface of the first dielectric layer; a gate dielectric film is formed on the surface of the interface film; a gate electrode film is formed on the surface of the gate dielectric film, and the gate electrode film fills the gate opening ; planarizing the gate electrode film, gate dielectric film and interface film to form the gate structure.

Optionally, it also includes: performing heat treatment after forming the interface film and gate dielectric film and before forming the gate electrode film; the parameters of the heat treatment include: the heat treatment process includes: spike annealing or laser annealing, the heat treatment The temperature range is 850 degrees Celsius to 1200 degrees Celsius.

Optionally, the forming process of the source-drain doped layer includes: an epitaxial growth process.

Optionally, further comprising: after forming the source-drain doped layer, forming a second dielectric layer on the substrate; forming a first conductive structure and a second conductive structure in the second dielectric layer, the first A conductive structure is electrically connected to the gate structure, and the second conductive structure is electrically connected to the source-drain doped layer.

Optionally, it also includes: after forming the source-drain doped layer and before forming the second dielectric layer, forming a contact resistance layer on the surface of the source-drain doped layer; after forming the contact resistance layer, forming The second dielectric layer is formed on the surface of the contact resistance layer.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

In the method for forming a semiconductor structure provided by the technical solution of the present invention, after forming the gate structure, the first dielectric layer is removed to expose the first groove; layer. The formation of the source-drain doped layer occurs after the process of forming the gate structure, which can avoid the high-temperature heat treatment process for forming the gate structure, thereby reducing the material of the source-drain doped layer under high temperature conditions. The impact is beneficial to ensure that the source-drain doped layer has a greater stress on the channel, so that the channel has a higher carrier mobility, and thus is beneficial to improving the performance of the semiconductor structure.

Further, the process of etching the first sidewall film to form the first sidewall in the second groove is after removing the first dielectric layer. Because the first sidewall film is in the second groove, the surface of the isolation structure and the surface of the dummy gate structure, and because the material of the first sidewall film is different from that of the first dielectric layer, so that In the subsequent process of removing the first dielectric layer, the first sidewall film located on the surface of the isolation structure can protect the isolation structure from being etched, thereby ensuring that the isolation structure is not affected by the process , so that the isolation structure can play a better isolation effect and improve the performance of the formed semiconductor structure.

Description of drawings

1 to 3 are structural schematic diagrams of each step of a method for forming a semiconductor structure;

4 to 15 are structural schematic diagrams of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

Detailed ways

As mentioned in the background, existing semiconductor structures perform poorly.

The reason for the poor performance of the semiconductor structure will be described in detail below in conjunction with the accompanying drawings. FIG. 1 to FIG. 3 are structural schematic diagrams of each step of a method for forming a semiconductor structure.

Referring to FIG. 1 , a semiconductor substrate 100 is provided, and the semiconductor substrate 100 has a fin 110 and an isolation structure 101. The fin 110 includes a first fin layer 111 with several layers overlapping along the normal direction of the surface of the semiconductor substrate 100, and a fin layer 111 located at In the second fin layer 112 of the two adjacent first fin layers, the isolation structure 101 covers part of the sidewall of the fin 110 .

Referring to FIG. 2 , a dummy gate structure 120 across the fin 110 is formed; using the dummy gate structure 120 as a mask, the fins 110 on both sides of the dummy gate structure 120 are removed to form a groove 121 .

Referring to FIG. 3 , the source-drain doped layer 130 is epitaxially formed in the grooves 121 on both sides of the dummy gate structure 120; after the source-drain doped layer 130 is formed, the dummy gate structure 120 and the second fin layer 112 are removed to form A gate opening (not shown in the figure); a gate structure 150 is formed in the gate opening, and the gate structure 150 is also located between adjacent first fin layers 111 .

In the above method, the gate opening is used to form the gate structure 150 . The gate opening is formed by removing the dummy gate structure 120 and the second fin layer 112 covered by the dummy gate structure 120, so the gate structure 150 can surround the first fin layer 111, and the gate structure controls the channel Enhanced capabilities.

However, after the source-drain doped layer 130 is formed, the gate opening is formed; the gate structure 150 is formed in the gate opening. The forming method of the gate structure 150 includes: forming an interface film (not shown in the figure) in the gate opening; forming a gate dielectric film (not shown in the figure) on the surface of the interface film; A gate electrode film (not shown) is formed on the surface of the dielectric film, and the gate electrode film fills the gate opening; planarize the gate electrode film, gate dielectric film and interface film, and form a gate electrode in the gate opening. Structure 150. In the process of forming the gate structure 150, high-temperature heat treatment is required, because the high-temperature heat treatment can repair the defects of the gate dielectric film, so that the formed gate dielectric layer has fewer defects, and at the same time, it can also make the interface film Densification, which is conducive to improving the reliability and turn-on voltage of semiconductor devices. However, the high-temperature heat treatment is likely to cause a high-temperature impact on the material of the formed source-drain doped layer 130, resulting in a decrease in the stress of the source-drain doped layer 130 on the channel, affecting the carrier mobility in the channel. , making the performance of the formed semiconductor structure poor.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: after forming the first groove, forming a first dielectric layer on the substrate, and the gate structure is located in the In the first dielectric layer; remove the dummy gate structure and the second fin layer covered by the dummy gate structure, and form in the first dielectric layer and between adjacent first fin layers A gate opening; a gate structure is formed in the gate opening, and the gate structure surrounds each first fin layer; after the gate structure is formed, the first dielectric layer is removed to expose the first concave Groove: after removing the first dielectric layer, a source-drain doped layer is formed in the first groove. The performance of the semiconductor structure formed by the method is better.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

4 to 15 are structural schematic diagrams of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

Please refer to FIG. 4 , a substrate 200 is provided, and the substrate 200 has a fin structure, and the fin structure includes several layers of composite fin layers 210 overlapping along the normal direction of the substrate surface, and each composite fin layer 210 includes a first The second fin layer 212 and the first fin layer 211 located on the surface of the second fin layer.

The material of the base 200 is semiconductor material. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multiple semiconductor materials composed of III-V group elements, silicon-on-insulator (SOI) or germanium-on-insulator. Wherein, the multiple semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

The material of the first fin layer 211 is different from that of the second fin layer 212; the material of the first fin layer 211 is single crystal silicon or single crystal silicon germanium; the material of the second fin layer 212 The material is single crystal silicon or single crystal silicon germanium.

In this embodiment, the material of the first fin layer 211 is single crystal silicon, and the material of the second fin layer 212 is single crystal silicon germanium. In other embodiments, the material of the first fin layer is single crystal silicon germanium, and the material of the second fin layer is single crystal silicon.

It should be noted that, in this embodiment, the bottom layer of the fin structure is the first fin layer 211 .

Please continue to refer to FIG. 4 , an isolation structure 201 covering part of the fin structure is formed on the substrate 200 , and a top surface of the isolation structure 201 is lower than a top surface of the bottommost first fin layer 211 .

The isolation structure 201 covers part of the bottommost first fin layer 111 .

The method for forming the isolation structure 201 includes: forming an isolation structure film (not shown) covering the fin structure on the substrate 200 ; and etching back the isolation structure film to form the isolation structure 201 .

The process for forming the isolation structure film is a deposition process, such as a fluid chemical vapor deposition process. The isolation structure film is formed by a fluid chemical vapor deposition process, so that the filling performance of the isolation structure film is better.

Referring to FIG. 5 , a dummy gate structure spanning the fin structure is formed on the substrate 200 , and the dummy gate structure covers part of the top surface and the sidewall surface of the fin structure.

Specifically, in this embodiment, the dummy gate structure is located on the surface of the isolation structure 201 and crosses the fin structure.

The method for forming the dummy gate structure includes: forming a dummy gate dielectric layer film (not shown in the figure) covering the fin structure on the substrate 200; forming a dummy gate on the dummy gate dielectric film film (not shown in the figure); etch the dummy gate dielectric film and the dummy gate film until the top surface of the fin structure is exposed, so that the dummy gate dielectric film forms a dummy gate dielectric layer, and the dummy gate film A dummy gate layer is formed to form the dummy gate structure.

The dummy gate structure includes: a dummy gate dielectric layer 202 across the fin structure and a dummy gate layer 220 located on the surface of the dummy gate dielectric layer 202 .

The material of the dummy gate dielectric layer 202 is silicon oxide. The material of the dummy gate layer 220 is polysilicon.

In this embodiment, the dummy gate structure further includes: second sidewalls 204 located on the sidewall surfaces of the dummy gate dielectric layer 202 and the dummy gate layer 220 .

The forming method of the second spacer 204 includes: forming a second sidewall material film (not shown in the figure) on the surface of the fin structure, the sidewall surface of the dummy gate dielectric layer, and the top surface and sidewall surface of the dummy gate layer. practice); etch the second sidewall material film until the top surface of the dummy gate layer 220 and the surface of the fin structure are exposed, the second sidewall is formed on the fin structure, and the The second sidewall is located on the sidewall surfaces of the dummy gate dielectric layer 202 and the dummy gate layer 220 .

The second sidewalls 204 are used to protect the sidewalls of the dummy gate layer 220 to prevent morphology defects in the subsequently formed gate layer from affecting the electrical properties of the semiconductor structure.

In this embodiment, the top surface of the dummy gate structure further has a dummy gate protection layer 203 , and the dummy gate protection layer 203 serves as a planarization stop layer.

The material of the dummy gate protection layer 203 includes silicon oxide or silicon nitride.

Referring to FIG. 6 , first grooves 205 are formed in the fin structures on both sides of the dummy gate structure.

The first groove 205 provides a space for subsequent formation of source and drain doped layers.

The method for forming the first groove 205 includes: using the dummy gate structure as a mask, etching the fin structure until the surface of the substrate 200 is exposed, and the fins on both sides of the dummy gate structure The first groove 205 is formed in the structure.

The process of removing the fin structures on both sides of the dummy gate structure is anisotropic dry etching. The anisotropic dry etching process is conducive to the formation of the first groove 205 with a better shape, avoiding etching damage to the fin structure at the bottom of the dummy gate structure, thereby benefiting the performance of the formed semiconductor structure .

Referring to FIG. 7 , part of the second fin layer 212 exposed on the sidewall of the first groove 205 is removed to form a second groove 206 between adjacent first fin layers 211 .

The second groove 206 is located between adjacent first fin layers 211 .

The second groove 206 provides a space for subsequent formation of the second sidewall.

The process of removing part of the second fin layer 212 is a wet etching process. The wet etching solution has a good selection ratio for silicon and silicon germanium, which can ensure that the morphology of silicon is not affected while silicon germanium is removed. The wet etching solution used in this embodiment is: hydrogen chloride gas with a volume percentage of 20% to 90%, and a temperature of 25 to 300 degrees Celsius.

In other embodiments, portions of the second fin layer are not removed.

Referring to FIG. 8 , after forming the second groove 206 , a first sidewall film 230 is formed in the second groove 206 , on the surface of the isolation structure 201 , and on the surface of the dummy gate structure.

The first side wall film 230 provides a material layer for subsequent formation of the first side wall.

The material of the first sidewall film 230 is different from the material of the isolation structure 201, so that the etching of the isolation structure 201 is avoided during the subsequent process of etching the first sidewall film 230 to form the first sidewall. damage, to ensure the isolation effect of the isolation structure 201.

The material of the first sidewall film 230 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride; the material of the isolation structure 201 includes: silicon oxide, nitrogen silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

In this embodiment, the material of the first sidewall film 230 is silicon nitride, and the material of the isolation structure 201 is silicon oxide.

The forming process of the first sidewall film 230 includes: chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

The material of the first side wall film 230 is also different from the material of the first dielectric layer formed subsequently.

Referring to FIG. 9 , after forming the first sidewall film 230 , a first dielectric layer 240 is formed on the substrate 200 , and the dummy gate structure is located in the first dielectric layer 240 .

The first dielectric layer 240 provides support for subsequent formation of a gate opening, so as to form a gate structure in the gate opening.

It should be noted that the dummy gate structure is located in the first dielectric layer 240, and the first dielectric layer 240 covers the sidewall surface of the dummy gate structure, so that subsequent removal of the dummy gate structure can A gate opening is formed in a dielectric layer 240 .

In this embodiment, the first dielectric layer 240 covers the surface of the first sidewall film 230 and the surface of the isolation structure 201 .

Specifically, the top surface of the first dielectric layer 240 is flush with the top surface of the dummy gate structure.

The method for forming the first dielectric layer 240 includes: forming an initial dielectric film (not shown in the figure) on the surface of the first side wall film 230, and the initial dielectric film covers the top surface and side of the dummy gate structure. wall surface; etching the initial dielectric film until the top surface of the dummy gate structure is exposed, and forming the first dielectric layer 240 on the substrate 200 .

The process for forming the initial dielectric film is a deposition process, such as a plasma chemical vapor deposition process or a fluid chemical vapor deposition process.

The process of etching the initial dielectric film includes: a chemical mechanical polishing process.

The material of the first dielectric layer 240 is different from that of the first side wall film 230 .

The material of the first dielectric layer 240 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

Since the first sidewall film 230 covers the sidewall surface and the top surface of the dummy gate structure, the first dielectric layer 240 covers the surface of the first sidewall film 230, so that the first dielectric layer 240 covers The surface of the side wall of the dummy gate structure satisfies the need for subsequent removal of the dummy gate structure to form a gate opening, while the first dielectric layer 240 provides support for forming the gate structure.

Please refer to FIG. 10 , remove the dummy gate structure and the second fin layer 212 covered by the dummy gate structure, in the first dielectric layer 240 and between adjacent first fin layers 211 Gate openings 250 are formed.

The gate opening 250 provides a space for subsequent formation of a gate structure.

The forming method of the gate opening 250 includes: removing the dummy gate structure, forming an initial gate opening (not shown in the figure) in the first dielectric layer 240; removing the second gate opening exposed by the initial gate opening. In the fin layer 212 , the initial gate opening forms the gate opening 250 .

In this embodiment, a dry etching process is used to remove the second fin layer 212 exposed by the initial gate opening. The etch selectivity ratio is 50-200, so as to reduce the etching damage to the first fin layer 211 and make the morphology of the first fin layer 211 better.

Referring to FIG. 11 , a gate structure 260 is formed in the gate opening 250 , and the gate structure 260 surrounds each first fin layer 211 .

Specifically, in this embodiment, the gate structure 260 is also located between adjacent first fin layers 211, so that the gate structure 260 can surround the first fin layer 211, increasing the The ability of the gate structure 260 to control the channel.

The gate structure 260 includes: an interface layer (not shown in the figure), a gate dielectric layer (not shown in the figure) located on the surface of the interface layer, and a gate electrode layer located on the surface of the gate dielectric layer ( not shown in the figure).

The forming method of the gate structure 260 includes: forming an interface film (not shown in the figure) on the surface of the gate opening 250 and the surface of the first dielectric layer 240; forming a gate dielectric film (not shown in the figure) on the surface of the interface film shown); form a gate electrode film (not shown in the figure) on the surface of the gate dielectric film, and the gate electrode film fills the gate opening 250; planarize the gate electrode film, gate dielectric film and interface film, forming the gate structure.

In this embodiment, after forming the interface film and the gate dielectric film, before forming the gate electrode film, it further includes: performing heat treatment; the parameters of the heat treatment include: the process of the heat treatment includes: spike annealing or laser annealing , the temperature range of the heat treatment is 850 degrees Celsius to 1200 degrees Celsius.

The effect of the heat treatment is: on the one hand, it repairs the defects of the gate dielectric film, so that the formed gate dielectric layer has fewer defects; on the other hand, it can make the interface film denser, which is beneficial to improve the The reliability of the 211 interface, therefore, the heat treatment is beneficial to improve the reliability and turn-on voltage of the semiconductor device.

The material of the interface layer includes silicon oxide. The process of forming the interface layer includes an oxidation process. The function of the interface layer includes: repairing the surface of the first fin layer 211 exposed by the gate opening 250 .

The material of the gate dielectric layer in this embodiment is a high-k dielectric material (dielectric coefficient greater than 3.9); the high-k dielectric material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide , tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

The material of the gate electrode layer is metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.

In this embodiment, the top surface of the gate structure further has a gate protection layer 261, and the gate protection layer 261 is used to protect the top surface of the gate structure to prevent the gate structure from being affected by subsequent processes, so as to The performance of the formed semiconductor structure is enhanced.

The materials of the gate protection layer 261 and the first dielectric layer 240 are different, and the materials of the gate protection layer 261 include: silicon oxide or silicon nitride.

In this embodiment, the material of the gate protection layer 261 is silicon nitride.

Referring to FIG. 12 , after the gate structure 260 is formed, the first dielectric layer 240 is removed to expose the first groove 205 .

In this embodiment, the first dielectric layer 230 is removed to expose the first side wall film 230 located on the bottom surface of the first groove 205 .

After the gate structure 260 is formed, the first dielectric layer 240 is removed to expose the first groove 205, and a source-drain doped layer will be formed in the first groove 205, so that the source The formation of the drain doped layer occurs after the process of forming the gate structure 260, which can avoid the high-temperature heat treatment process for forming the gate structure 260, thereby reducing the damage to the material of the source-drain doped layer under high temperature conditions. The impact is beneficial to ensure that the source-drain doped layer has a greater stress on the channel, so that the channel has a higher carrier mobility, and thus is beneficial to improving the performance of the semiconductor structure.

The first etching process is used to remove the first dielectric layer 240 , and the etching rate of the first dielectric layer 240 in the first etching process is greater than the etching rate of the first spacer film 230 . In this embodiment, the first etching process is a dry etching process, and the process parameters include: the etching gas used includes NH ₃ , NF ₃ and He, wherein the flow rate of NH ₃ is 50 standard ml/min- 800 standard ml/min, the flow rate of NF ₃ is 30 standard ml/min to 300 standard ml/min, the flow rate of He is 500 standard ml/min to 3000 standard ml/min, and the pressure is 2 Torr to 30 Torr.

Since the materials of the first dielectric layer 240 and the first sidewall film 230 are different, a larger etching selectivity ratio for the first dielectric layer 240 and the first sidewall film 230 can be satisfied. At the same time, the first sidewall film 230 is in the second groove 206 (shown in FIG. 7 ), the surface of the isolation structure 201 and the surface of the dummy gate structure, so that the subsequent removal of the first dielectric layer 240 During the process, the first side wall film 230 can protect the isolation structure 201 at the bottom of the first side wall film 230 to avoid etching the isolation structure 201, thereby ensuring that the isolation structure 201 It is not affected by the process, so that the isolation structure 201 can play a better isolation role and improve the performance of the formed semiconductor structure.

Referring to FIG. 13 , the first sidewall film 230 is etched until the sidewall surface of the first fin layer 211 and the surface of the substrate 200 are exposed, and a first sidewall 270 is formed in the second groove 206 .

The function of the first spacer 270 is to electrically isolate the gate structure 260 located in the gate opening 250 from the subsequently formed source-drain doped layer, so as to meet process requirements.

The method for etching the first sidewall film 230 includes: using the dummy gate structure as a mask, etching the first sidewall film 230, and forming the first sidewall film 230 in the second groove 206. The side wall 270 , the side wall of the first side wall 270 is flush with the side wall of the second side wall 204 .

The first sidewall film 230 is etched by a second etching process, and the etching rate of the first sidewall film 230 by the second etching process is greater than the etching rate of the isolation structure 201 . In this embodiment, the second etching process is a dry etching process, and the process parameters include: the etching gas used includes CH ₃ F, N ₂ and O ₂ , wherein the flow rate of CH ₃ F is 10 standard milliliters /min to 100 standard ml/min, the flow rate of NF ₃ is 50 standard ml/min to 500 standard ml/min, and the flow rate of O ₂ is 10 standard ml/min to 200 standard ml/min.

Please refer to FIG. 14 , after removing the first dielectric layer 240 , a source-drain doped layer 280 is formed in the first groove 205 .

In this embodiment, after the first spacer film 230 is etched to form the first spacer 270 , a source-drain doped layer 280 is formed in the first groove 205 .

The formation process of the source-drain doped layer 280 includes: an epitaxial growth process.

The source-drain doping layer 280 contains doping ions. In this embodiment, during the process of forming the source-drain doped layer 280 , an in-situ doping process is used to dope ions.

When the semiconductor device is a P-type device, the material of the source-drain doped layer 280 includes: silicon, germanium or silicon germanium; the dopant ions are P-type ions, including boron ions, BF ^2- ions or indium Ions; when the semiconductor device is an N-type device, the material of the source-drain doped layer 280 includes: silicon, gallium arsenide or indium gallium arsenide; the dopant ions are N-type ions, including phosphorus ions or arsenic ion.

Referring to FIG. 15 , a contact resistance layer 281 is formed on the surface of the source-drain doped layer 280 .

The contact resistance layer 281 is used to reduce the contact resistance between the source-drain doped layer 280 and the subsequently formed first conductive structure, thereby improving the performance of the formed semiconductor structure.

The method for forming the contact resistance layer 281 includes: forming a metal layer (not shown in the figure) on the surface of the source-drain doped layer 280, the gate structure 260, and the surface of the isolation structure 201; performing annealing treatment to make the metal layer React with the surface of the source-drain doped layer 280 to form the contact resistance layer 281; after forming the contact resistance layer 281, remove the unreacted metal layer.

The material of the contact resistance layer 281 includes: titanium silicon compound.

Please continue to refer to FIG. 15 , after the source-drain doped layer 280 is formed, a second dielectric layer 290 is formed on the substrate 200 .

In this embodiment, after the contact resistance layer 281 is formed, a second dielectric layer 290 is formed on the surface of the contact resistance layer 281 .

The second dielectric layer 290 is used to provide support for forming the first conductive structure and the second conductive structure.

The material of the second dielectric layer 290 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

In this embodiment, the material of the second dielectric layer 290 is silicon oxide.

Please continue to refer to FIG. 15 , a first conductive structure 291 and a second conductive structure 291 are formed in the second dielectric layer 290 , the first conductive structure 291 is electrically connected to the gate structure 260 , and the second conductive The structure 292 is electrically connected to the source-drain doped layer 280 .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (16)

1. A method for forming a semiconductor structure, comprising: A substrate is provided, on which there is a fin structure, the fin structure includes several layers of composite fin layers overlapping along the normal direction of the surface of the substrate, each composite fin layer includes a second fin layer and a a first fin layer on the surface of the lower layer; forming a dummy gate structure across the fin structure on the substrate, the dummy gate structure covering part of the top surface and sidewall surface of the fin structure; forming first grooves in the fin structures on both sides of the dummy gate structure; After forming the first groove, forming a first dielectric layer on the substrate, and the dummy gate structure is located in the first dielectric layer; removing the dummy gate structure and the second fin layer covered by the dummy gate structure, and forming gate openings in the first dielectric layer and between adjacent first fin layers; forming a gate structure within the gate opening, the gate structure surrounding each first fin layer; After forming the gate structure, removing the first dielectric layer to expose the first groove; After removing the first dielectric layer, forming a source-drain doped layer in the first groove; The bottom layer of the fin structure is the first fin layer; before forming the dummy gate structure, an isolation structure covering part of the fin structure is formed on the substrate, and the top surface of the isolation structure is low on the bottommost first fin layer top surface; After forming the first groove and before forming the first dielectric layer, part of the second fin layer exposed by the sidewall of the first groove is removed, and a second fin layer is formed between adjacent first fin layers. a groove; forming a first sidewall film in the second groove, on the surface of the isolation structure, and on the surface of the dummy gate structure; after forming the first sidewall film, forming the first dielectric layer on the substrate, And the first dielectric layer covers the surface of the first side wall membrane and the surface of the isolation structure; After removing the first dielectric layer and before forming the source-drain doped layer, etch the first sidewall film until the sidewall surface of the first fin layer and the surface of the base are exposed. A first sidewall is formed in the groove; after the first sidewall is formed, the source-drain doped layer is formed, and the source-drain doped layer covers the sidewall surface of the first sidewall and the side of the first fin layer wall surface. 2. The method for forming a semiconductor structure according to claim 1, wherein the method for forming the first groove comprises: using the dummy gate structure as a mask, etching the fin structure until The substrate surface is exposed, and the first groove is formed in the fin structure on both sides of the dummy gate structure. 3. The method for forming a semiconductor structure according to claim 1, wherein the method for forming the gate opening comprises: removing the dummy gate structure, forming an initial gate opening in the first dielectric layer; removing The second fin layer exposed by the initial gate opening makes the initial gate opening form the gate opening. 4. The method for forming a semiconductor structure according to claim 1, wherein the material of the first sidewall film is different from that of the first dielectric layer, and the material of the first sidewall film is different from that of the first dielectric layer. The materials of the isolation structure are different; the materials of the first dielectric layer include: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbonitride; the first sidewall film The material includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride; the material of the isolation structure includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide , silicon carbonitride or silicon carbonitride. 5. The method for forming a semiconductor structure according to claim 1, wherein the forming process of the first sidewall film comprises: a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. 6. The method for forming a semiconductor structure according to claim 1, wherein the method for forming the first dielectric layer comprises: forming an initial dielectric film on the surface of the first sidewall film, and the initial dielectric film covers The top surface and the sidewall surface of the dummy gate structure; etching the initial dielectric film until the top surface of the dummy gate structure is exposed, and forming the first dielectric layer on the substrate. 7. The formation method of semiconductor structure as claimed in claim 1, is characterized in that, adopts first etching process to remove described first dielectric layer, and the etching rate of described first etching process to first dielectric layer Greater than the etch rate of the first sidewall film. 8. The method for forming a semiconductor structure according to claim 1, wherein the first sidewall film is etched by a second etching process, and the first sidewall film is etched by the second etching process. The etch rate of the film is greater than the etch rate of the isolation structure. 9. The method for forming a semiconductor structure according to claim 1, wherein the material of the first fin layer is different from that of the second fin layer; the material of the first fin layer is a single crystal Silicon or single crystal silicon germanium; the material of the second fin layer is single crystal silicon or single crystal silicon germanium. 10. The method for forming a semiconductor structure according to claim 1, wherein the dummy gate structure comprises: a dummy gate dielectric layer and a dummy gate layer positioned on the surface of the dummy gate dielectric layer; The forming method of the electrode structure includes: forming a dummy gate dielectric film covering the fin structure on the substrate; forming a dummy gate film on the dummy gate dielectric film; etching the dummy gate dielectric film and the dummy gate The pole film until the top surface of the fin structure is exposed, the dummy gate dielectric film forms a dummy gate dielectric layer, the dummy gate film forms a dummy gate layer, and the dummy gate structure is formed. 11. The method for forming a semiconductor structure according to claim 10, wherein the dummy gate structure further comprises: a second spacer located on the sidewall surface of the dummy gate dielectric layer and the dummy gate layer . 12. The method for forming a semiconductor structure according to claim 1, wherein the gate structure comprises: an interface layer, a gate dielectric layer located on the surface of the interface layer, and a gate dielectric layer located on the surface of the gate dielectric layer Gate electrode layer; the forming method of the gate structure includes: forming an interface film on the surface of the gate opening and the surface of the first dielectric layer; forming a gate dielectric film on the surface of the interface film; forming a gate dielectric film on the surface of the gate dielectric film. electrode film, and the gate electrode film fills the gate opening; planarize the gate electrode film, gate dielectric film and interface film to form the gate structure. 13. The method for forming a semiconductor structure according to claim 12, further comprising: performing heat treatment after forming the interface film and gate dielectric film and before forming the gate electrode film; the heat treatment process includes: Annealing or laser annealing, the temperature range of the heat treatment is 850°C-1200°C. 14 . The method for forming a semiconductor structure according to claim 1 , wherein the forming process of the source-drain doped layer comprises: an epitaxial growth process. 15. The method for forming a semiconductor structure according to claim 1, further comprising: after forming the source-drain doped layer, forming a second dielectric layer on the substrate; A first conductive structure and a second conductive structure are formed therein, the first conductive structure is electrically connected to the gate structure, and the second conductive structure is electrically connected to the source-drain doped layer. 16. The method for forming a semiconductor structure according to claim 15, further comprising: after forming the source-drain doped layer and before forming the second dielectric layer, forming a layer on the surface of the source-drain doped layer forming a contact resistance layer; after forming the contact resistance layer, forming the second dielectric layer on the surface of the contact resistance layer.