CN113345881A

CN113345881A - Control circuit

Info

Publication number: CN113345881A
Application number: CN202010098557.9A
Authority: CN
Inventors: 李建兴; 黄晔仁; 林文新; 邱俊榕; 邱华琦
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2020-02-18
Filing date: 2020-02-18
Publication date: 2021-09-03

Abstract

A control circuit is applied in a specific device, the specific device has III-V semiconductor materials, and includes a control electrode, a first electrode and a second electrode, the control circuit includes a first transistor and an electrostatic discharge protection circuit , the first transistor is coupled between the first and second electrodes, and has III-V semiconductor materials, the electrostatic discharge protection circuit is coupled to the control electrode, the first transistor and the second electrode, when an electrostatic discharge event occurs, the electrostatic discharge The discharge protection circuit provides a discharge path for discharging an electrostatic discharge current from the control electrode to the second electrode.

Description

Control circuit

Technical Field

The present invention relates to a high electron mobility device, and more particularly, to a high electron mobility device for an Electrostatic Discharge (ESD) protection circuit.

Background

High Electron Mobility Transistor (HEMT) has a High output voltage, and thus is widely used in High power semiconductor devices to meet the market demand of consumer electronics, communication hardware, electric vehicles, or home appliances. However, when an ESD event occurs, the HEMT is likely to be affected by the ESD current.

Disclosure of Invention

The invention provides a control circuit which is applied to a specific device. The specific device has III-V semiconductor material and includes a control electrode, a first electrode and a second electrode. The control circuit comprises a first transistor and an electrostatic discharge protection circuit. The first transistor is coupled between the first and second electrodes and has a III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. When an ESD event occurs, the ESD protection circuit provides a discharge path for discharging an ESD current from the control electrode to the second electrode.

The invention also provides a high electron mobility device, which comprises a substrate, a control electrode, a first electrode, a second electrode and a control circuit. The substrate has a iii-v semiconductor material. The control electrode, the first electrode and the second electrode are formed on the substrate. The control circuit comprises a first transistor and an electrostatic discharge protection circuit. The first transistor is coupled between the first and second electrodes and has a III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. When an ESD event occurs, the ESD protection circuit provides a discharge path for discharging an ESD current from the control electrode to the second electrode.

Drawings

FIG. 1 is a schematic diagram of a high electron mobility device of the present invention;

FIG. 2 is a schematic diagram of an ESD protection circuit according to the present invention;

FIG. 3 is another schematic diagram of an ESD protection circuit according to the present invention.

[ description of symbols ]

100: a high electron mobility device;

110: a substrate;

120: a control electrode;

130. 140: an electrode;

150: a control circuit;

151. 200 and 300: an electrostatic discharge protection circuit;

152. 230, 330: a transistor;

r1, R2: a resistance device;

210. 220, 310, 320: an impedance device;

340: a back-to-back diode pair;

d1, D2: and a diode.

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of each device in the embodiments is for illustration and not for limiting the invention. In addition, the repetition of the reference numbers in the embodiments is for the purpose of simplifying the description and does not imply any relationship between the different embodiments.

Fig. 1 is a schematic view of a high electron mobility device of the present invention. As shown in fig. 1, the hemt 100 includes a substrate (substrate)110, a control electrode 120,

electrodes

130 and 140, and a control circuit 150. In one possible embodiment, the HEMT 100 is a High Electron Mobility Transistor (HEMT). In the present embodiment, the substrate 110 is made of a iii-v semiconductor material, such as gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or silicon germanium (SiGe).

Control electrode 120, electrode 130, and electrode 140 are formed over substrate 110. In one possible embodiment, when the hemt 100 is a hemt, the control electrode 120 serves as a gate (gate) of the hemt. In this example, the electrode 130 serves as a drain (drain) of the hemt, and the electrode 140 serves as a source (source) of the hemt.

The control circuit 150 is formed over the substrate 110. In the present embodiment, the control circuit 150 is integrated in the hemt 100 to prevent the hemt 100 from being affected by an esd current. As shown in fig. 1, the control circuit 150 includes an electrostatic discharge protection circuit (ESD protection circuit)151 and a transistor 152.

The transistor 152 is coupled between the

electrodes

130 and 140. In one possible embodiment, transistor 152 has a group iii-v semiconductor material. The present invention does not limit the structure of the transistor 152. In the present embodiment, the transistor 152 is also a high electron mobility transistor. As shown in fig. 1, the transistor 152 has a drain coupled to the electrode 130, a source coupled to the electrode 140, and a gate coupled to the esd protection circuit 151.

When an ESD event occurs on one of the

electrodes

130 and 140 and the other of the

electrodes

130 and 140 is coupled to ground, the gate voltage of the transistor 152 is gradually increased by a parasitic capacitance (not shown) between the gate and the drain of the transistor 152. When a voltage between the gate and the source of the transistor 152 is greater than a threshold voltage (threshold voltage) of the transistor 152, the transistor 152 is turned on. Therefore, an electrostatic discharge current is discharged from the electrode 130 to the electrode 140, or from the electrode 140 to the electrode 130.

In the present embodiment, the esd protection circuit 151 is coupled to the control electrode 120, the transistor 152 and the electrode 140, for preventing an esd current from entering the gate of the transistor 152 from the control electrode 120. For example, when an esd event occurs on the control electrode 120 and the electrode 140 is coupled to ground, the esd protection circuit 151 provides a discharge path (not shown) for discharging an esd current from the control electrode 120 to the electrode 140. Therefore, the gate of the transistor 152 is not damaged by electrostatic discharge stress (ESD stress). However, when the esd event does not occur, the esd protection circuit 151 cuts off the discharge path. At this time, the hemt 100 operates according to the voltage levels of the control electrode 120 and the

electrodes

130 and 140.

FIG. 2 is a schematic diagram of an ESD protection circuit according to one embodiment of the present invention. In the present embodiment, the esd protection circuit 200 includes

impedance devices

210 and 220 and a transistor 230. The impedance device 210 is coupled between the control electrode 120 and the transistor 152. In one possible embodiment, the impedance device 210 is a resistor device R1. Resistive device R1 is coupled between control electrode 120 and the gate of transistor 152. The resistance of the resistor device R1 may be between 100 Ω and 200 Ω. The present invention does not limit the structure of the impedance device 210. In other embodiments, the impedance device 210 is a transistor. In this case, the transistor constituting the impedance device 210 may also be a high electron mobility transistor.

The impedance device 220 is coupled to the transistor 230 and the electrode 140. The present invention does not limit the structure of the impedance device 220. In one possible embodiment, the impedance device 220 is a resistor device R2. In this example, the resistor device R2 is coupled between the gate of the transistor 230 and the electrode 140. The present invention does not limit the structure of the impedance device 220. In other embodiments, the impedance device 220 is a transistor. In this example, the transistor constituting the impedance device 220 may be a high electron mobility transistor.

The transistor 230 is coupled between the control electrode 120 and the electrode 140. In one possible embodiment, the transistor 230 has a group iii-v semiconductor material. In this example, the transistor 230 is formed on the same substrate (e.g., 110) as the hemt 100. The present invention does not limit the structure of the transistor 230. In the present embodiment, the transistor 230 is also a high electron mobility transistor, and has a drain coupled to the control electrode 120, a source coupled to the electrode 140, and a gate coupled to the impedance device 220.

When an ESD event occurs on the control electrode 120 and the electrode 140 is coupled to ground, the gate voltage of the transistor 230 gradually increases due to a parasitic capacitance (not shown) between the gate and the drain of the transistor 230. When the voltage between the gate and the source of the transistor 230 is greater than the threshold voltage of the transistor 230, the transistor 230 is turned on to discharge an electrostatic discharge current from the control electrode 120 to the electrode 140. Therefore, the electrostatic discharge current does not enter the gate of the transistor 152. When the esd event does not occur, the impedance device 220 pulls down the gate voltage of the transistor 230 to prevent the transistor 230 from being turned on.

In addition, when an ESD event occurs on the electrode 130 and the control electrode 120 is coupled to ground, the gate voltages of the

transistors

152 and 230 gradually increase due to the gate-drain parasitic capacitance of the

transistors

152 and 230, respectively. When the voltage between the gate and the source of the

transistors

152 and 230 is greater than the respective threshold voltage, the

transistors

152 and 230 are turned on. Therefore, the electrostatic discharge current flows from the electrode 130, through the transistor 152, the electrode 140, and the transistor 230, and flows into the control electrode 120.

Similarly, when an ESD event occurs on the control electrode 120 and the electrode 130 is coupled to ground, the gate voltage of the transistor 230 gradually increases due to the gate-drain parasitic capacitance of the transistor 230. When the voltage between the gate and the source of the transistor 230 is greater than the threshold voltage of the transistor 230, the transistor 230 is turned on. At this time, since a part of the current flows through the resistance device 210, the gate voltage of the transistor 152 also gradually rises. When the voltage between the gate and the source of the transistor 152 is greater than the threshold voltage of the transistor 152, the transistor 152 is turned on. Accordingly, the electrostatic discharge current flows from the control electrode 120, through the transistor 230, the electrode 140, and the transistor 152, and flows into the electrode 130.

In other embodiments, the transistor 230 can be turned on quickly when an esd event occurs by adjusting the channel size of the transistor 230 or the resistance of the impedance device 220, so as to prevent the gate of the transistor 152 from being damaged by the esd current. In addition, the performance of the ESD protection circuit 320 can be adjusted by increasing the area of the transistor 230 or decreasing the on-resistance (Ron) of the transistor 230.

FIG. 3 is another schematic diagram of an ESD protection circuit according to the present invention. In the present embodiment, the esd protection circuit 300 includes

impedance devices

310 and 320, a transistor 330, and a back-to-back diode pair 340. The impedance device 310 is coupled between the control electrode 120 and the transistor 152. The impedance device 320 is coupled to the transistor 330 and the electrode 140. Since the characteristics of the

impedance devices

310 and 320 are similar to those of the

impedance devices

210 and 220 of fig. 2, the description thereof is omitted.

The transistor 330 is coupled between the control electrode 120 and the electrode 140. In one possible embodiment, the transistor 330 has a group iii-v semiconductor material. In the present embodiment, the transistor 230 is also a high electron mobility transistor, and has a gate coupled to one end of the impedance device 320, a drain coupled to the control electrode 120, and a source coupled to the other end of the impedance device 320 and the electrode 140.

The back-to-back diode pair 340 is coupled between the control electrode 120 and the transistor 330. In the present embodiment, the back-to-back diode pair 340 includes diodes D1 and D2. The cathode (cathode) of the diode D1 is coupled to the control electrode 120, and the anode (anode) thereof is coupled to the anode of the diode D2. The cathode of the diode D2 is coupled to the gate of the transistor 330 and the impedance device 320. The present invention is not limited to the types of diodes D1 and D2. In one embodiment, the diode D1 is a schottky diode (schottky diode), and the diode D2 is a PN junction diode.

When an ESD event occurs on the control electrode 120 and the electrode 140 is coupled to ground, the gate voltage of the transistor 330 gradually increases due to a parasitic capacitance (not shown) between the gate and the drain of the transistor 330. In the present embodiment, since a part of the current flows through the back-to-back diode pair 340, the rising speed of the gate voltage of the transistor 330 can be increased. Since the transistor 330 is turned on rapidly, an ESD current is discharged from the control electrode 120 to the electrode 140. Therefore, the gate of the transistor 152 is not damaged by the esd current. When the esd event does not occur, the impedance device 320 pulls down the gate voltage of the transistor 330 to prevent the transistor 330 from being turned on.

transistors

152 and 330 gradually increase due to the gate-drain parasitic capacitances of the

transistors

152 and 330. In the present embodiment, since a part of the current flows through the back-to-back diode pair 340, the rising speed of the gate voltage of the transistor 330 can be increased. When the voltages between the gates and the sources of the

transistors

152 and 330 are greater than the respective threshold voltages, the

transistors

152 and 330 are turned on. Therefore, the electrostatic discharge current flows from the electrode 130, through the transistor 152, the electrode 140, and the transistor 330, and flows into the control electrode 120.

Similarly, when an ESD event occurs on the control electrode 120 and the electrode 130 is coupled to ground, the gate voltage of the transistor 330 gradually increases through the gate-drain parasitic capacitance of the transistor 330 and the back-to-back diode pair 340. When the voltage between the gate and the source of the transistor 330 is greater than the threshold voltage of the transistor 330, the transistor 330 is turned on. At this time, since a part of the current flows through the resistance device 310, the gate voltage of the transistor 152 also gradually rises. When the voltage between the gate and the source of the transistor 152 is greater than the threshold voltage of the transistor 152, the transistor 152 is turned on. Therefore, the electrostatic discharge current flows from the control electrode 120, through the transistor 330, the electrode 140, and the transistor 152, and flows into the electrode 130.

In other embodiments, the transistor 330 can be turned on quickly by adjusting the channel size of the transistor 330 or the resistance of the impedance device 320 when an esd event occurs, so as to prevent the gate of the transistor 152 from being damaged by the esd current. In addition, the performance of the ESD protection circuit 300 can be adjusted by increasing the area of the transistor 330 or decreasing the on-resistance of the transistor 330.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.

Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the systems, devices, or methods described in the embodiments of the present invention may be implemented in hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention is subject to the claims.

Claims

1. A control circuit, characterized in that it is applied to a specific device, the specific device has Group III and V semiconductor materials, and comprises a control electrode, a first electrode and a second electrode, and the control circuit includes :

a first transistor, coupled between the first electrode and the second electrode, and having group III and V semiconductor materials; and

An electrostatic discharge protection circuit is coupled to the control electrode, the first transistor and the second electrode, wherein when an electrostatic discharge event occurs, the electrostatic discharge protection circuit provides a discharge path for discharging a An electrostatic discharge current is discharged from the control electrode to the second electrode.

2. The control circuit according to claim 1, wherein the electrostatic discharge protection circuit comprises:

a first impedance device coupled between the control electrode and the first transistor;

a second transistor coupled between the control electrode and the second electrode; and

A second impedance device is coupled to the second transistor and the second electrode.

3. The control circuit of claim 2, further comprising:

A back-to-back diode pair is coupled between the control electrode and the second transistor.

4. The control circuit of claim 3, wherein the back-to-back diode pair comprises:

a first diode having a first cathode and a first anode, the first cathode being coupled to the control electrode; and

A second diode has a second cathode and a second anode, the second cathode is coupled to the second transistor, and the second anode is coupled to the first anode.

5 . The control circuit according to claim 4 , wherein the first diode is a Schottky diode, and the second diode is a PN junction diode. 6 .

6 . The control circuit of claim 2 , wherein the first transistor and the second transistor are made of III-V semiconductor materials. 7 .

7 . The control circuit according to claim 2 , wherein the first impedance device and the second impedance device are resistive devices. 8 .

8 . The control circuit of claim 2 , wherein the first transistor has a first gate, a first drain and a first source, and the first gate is coupled to the In the first impedance device, the first drain electrode is coupled to the first electrode, and the first source electrode is coupled to the second electrode.

9 . The control circuit of claim 8 , wherein the second transistor has a second gate, a second drain and a second source, and the second gate is coupled to the A second impedance device, the second drain is coupled to the control electrode, and the second source is coupled to the second electrode.

10 . The control circuit of claim 1 , wherein when the electrostatic discharge event does not occur, the electrostatic discharge protection circuit cuts off the discharge path. 11 .