KR101873219B1 - GaN-BASED POWER SWITCHING DEVICE - Google Patents

Abstract

The present invention relates to an AlGaN/GaN heterojunction power semiconductor device which constructs, as a single stage, a gate current booster for amplifying a switching driving signal and integrates the gate current booster into a chip having a power switching device formed therein. A GaN-based power switching device has a monolithic integrated circuit chip structure formed by integrating a power switching transistor with a gate current booster which receives a driving signal of the power switching transistor and amplifies the driving signal to generate a driving gate current. The gate current booster includes: a driving transistor of which a source terminal is grounded, which receives the driving signal through a gate terminal, and of which a drain terminal is connected to a gate terminal of the power switching transistor; and a variable resistor of which one end is connected to the gate terminal of the power switching transistor and the other end is connected to a first power supply to provide a variable resistance value. Thus, driving current of a power switch is able to be sufficiently boosted.

Description

GaN-BASED POWER SWITCHING DEVICE [0001]

The present invention relates to a gallium nitride-based power switching device, and more particularly, to an AlGaN / GaN heterojunction power semiconductor device in which a gate current booster for amplifying a switching driving signal is formed as a single stage, To a gallium nitride based power switching device.

Silicon carbide (SiC) and gallium nitride (GaN) based semiconductors with wide bandgap have been developed to meet the requirements of next generation power Semiconductors are attracting much attention. Unlike SiC, a GaN-based electronic device in which aluminum gallium nitride (AlGaN) is grown on GaN can be fabricated to have a high-performance heterojunction structure by forming a two-dimensional electron gas (2DEG) at the interface. The AlGaN / GaN heterojunction structure has a polarization effect that provides high carrier density and low on-resistance and frequency performance with strong mobility, thereby enabling fast switching operation with low power loss and high efficiency RF power amplification.

Higher switching speeds reduce the overall power module size and weight because the passive components of the power integrated circuit (IC) are smaller. On the other hand, a great deal of attention must be paid to the gate driver of a power switching field effect transistor (FET). As the switching speed increases, the switching power loss occurring every on / off switching time period has a significant effect on the overall power conversion efficiency. The length of the switching time depends on how quickly the gate capacitance of the switching FET is charged and discharged. Generally, the gate drive signal is generated by a logic circuit or microprocessor's controller IC that can not provide a high current, thereby limiting the charge-discharge rate of the switching FET. A gate current booster is a configuration in which a low level input signal from a controller IC is boosted and a boosted current is supplied to a power switching FET to enable a fast switching operation.

A typical type of gate current booster has a structure that allows fast charge and discharge of the gate capacitance of the switching FET 20 using a CMOS push-pull inverter chain 10 as shown in Fig. At this time, each stage of the inverter chain 10 is composed of a pair of PMOS and CMOS. Since the low level input current from the controller IC is boosted at each stage, the final output current level of the gate current booster is proportional to the number of stages. Therefore, in order to perform a fast switching operation, the number of stages in the inverter chain 10 must be increased, thereby increasing the area of the circuit.

In addition, the conventional power semiconductor device has a problem that the parasitic effect, that is, the overshoot ringing phenomenon, occurs due to the interconnection between the switching FET and the gate driver circuit, thereby limiting the safe operation region.

Korean Patent Publication No. 10-2014-0040813

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems of the prior art, and it is an object of the present invention to provide a CMOS inverter which can sufficiently boost the driving current of a power switch even in a single stage inverter structure by replacing NMOS and PMOS, which are CMOS structures of an inverter, with a gallium nitride- The present invention is directed to a gallium nitride based power switching device.

Further, the present invention can integrate the inverter circuit on the same substrate as the AlGaN / GaN heterojunction power switching FET by constructing the MOS-HFET and the mesa resistor having the AlGaN / GaN heterojunction structure as the inverter stages, The present invention provides a gallium nitride based power switching device that does not require any additional process for constructing a gallium nitride based semiconductor device and can prevent a parasitic effect caused by inter-circuit connection.

According to an aspect of the present invention, there is provided a power switching device including a power switching transistor, and a gate current booster for receiving a driving signal of the power switching transistor and amplifying the driving signal to generate a driving gate current, A GaN-based power switching device having an integrated circuit chip structure, wherein the gate current booster has a source terminal grounded and receiving the drive signal through a gate terminal, and a drain terminal connected to a gate terminal of the power switching transistor A coupled driving transistor; And a variable resistor having one end connected to the gate terminal of the power switching transistor and the other end connected to the first power supply to provide a variable resistance value.

Here, the driving transistor may include: a substrate; A buffer layer which is a gallium nitride material formed on the substrate; A barrier layer which is an aluminum gallium nitride-based material formed on the buffer layer; A gate insulating layer formed on the barrier layer; A first source electrode and a first drain electrode which are located in contact with the barrier layer through the gate insulating layer; And a first gate electrode located between the first source electrode and the first drain electrode and spaced apart from the barrier layer by the gate insulating layer.

The variable resistor may further include: a substrate; A buffer layer which is a gallium nitride material formed on the substrate; A barrier layer which is an aluminum gallium nitride-based material formed on the buffer layer; A gate insulating layer formed on the barrier layer; And a first ohmic electrode and a second ohmic electrode disposed in contact with the barrier layer through the gate insulating layer.

On the other hand, the variable resistor is integrated on the same substrate as the driving transistor, The buffer layer; The barrier layer; The gate insulating layer; And a first ohmic electrode and a second ohmic electrode disposed in contact with the barrier layer through the gate insulating layer.

The power switching transistor may further include: a substrate; A buffer layer which is a gallium nitride material formed on the substrate; A barrier layer which is an aluminum gallium nitride-based material formed on the buffer layer; A gate insulating layer formed on the barrier layer; A second source electrode and a second drain electrode penetrating the gate insulating layer and located in contact with the barrier layer; And a second gate electrode located between the second source electrode and the second drain electrode and spaced apart from the barrier layer by the gate insulating layer.

Wherein the power switching transistor is integrated on the same substrate as the driving transistor or the variable resistor and the driving transistor, The buffer layer; The barrier layer; The gate insulating layer; A second source electrode and a second drain electrode penetrating the gate insulating layer and located in contact with the barrier layer; And a second gate electrode located between the second source electrode and the second drain electrode and spaced apart from the barrier layer by the gate insulating layer.

The first distance, which is the source-drain distance of the first source electrode and the first drain electrode, may be a half of the second distance that is the source-drain distance of the second source electrode and the second drain electrode. have.

According to the present invention, by replacing the CMOS circuit of the inverter for boosting the drive signal of the power switch with the gallium nitride-based MOS-HFET and the resistor, boosting efficiency can be maximized even in a single stage structure.

Further, according to the present invention, since the inverter circuit is implemented as a monolithic integrated circuit on the same substrate as the AlGaN / GaN heterojunction power switching FET, no additional process is required to construct the inverter circuit, It is possible to prevent an overshoot ringing phenomenon of a driving signal caused by the driving signal.

1 is a diagram illustrating a power switching device to which a conventional gate current booster is applied.
2 is a circuit diagram showing a gallium nitride based power switching device according to an embodiment of the present invention.
3 is a vertical cross-sectional view illustrating a structure of a driving transistor and a power switching transistor of a gallium nitride based power switching device according to an embodiment of the present invention.
4 is a vertical cross-sectional view illustrating a load structure of a variable resistor of a gallium nitride based power switching device according to an embodiment of the present invention.
5 is a graph showing input / output voltage waveforms of driving transistors in a gallium nitride based power switching device according to an embodiment of the present invention.
6A is an integration diagram of a gallium nitride based power switching device fabricated according to an embodiment of the present invention.
6B is a circuit diagram corresponding to the apparatus shown in FIG. 6A.
7A is a circuit diagram of a gallium nitride based power switching device fabricated according to an embodiment of the present invention, connected to a test circuit board.
7B is a view illustrating an embodiment in which a gallium nitride-based power switching device manufactured according to an embodiment of the present invention is connected to a test circuit board.
8A is a graph illustrating characteristics of a variable resistor of a gallium nitride based power switching device according to an embodiment of the present invention.
8B is a graph illustrating characteristics of a driving transistor of a gallium nitride based power switching device according to an embodiment of the present invention.
8C is a graph illustrating characteristics of a power switching transistor of a gallium nitride based power switching device according to an embodiment of the present invention.
9A and 9B are graphs showing a gate driving waveform of a power switching transistor according to a variation of a variable resistance value of a gallium nitride based power switching apparatus according to an embodiment of the present invention.
10A and 10B are graphs comparing switching characteristics of a gallium nitride based power switching device according to an embodiment of the present invention with switching characteristics of a conventional device.
11 is a graph showing dynamic switching characteristics of a gallium nitride based power switching device according to an embodiment of the present invention.
12A and 12B are graphs showing the switching characteristic of the gallium nitride based power switching device of the present invention in which the gate current booster is monolithically integrated.
12C and 12D are graphs showing the switching characteristics of a power switching transistor without a gate current booster in zooming.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The shape and the size of the elements in the drawings may be exaggerated for clarity and the same elements are denoted by the same reference numerals in the drawings.

And throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between. Also, when a component is referred to as " comprising " or " comprising ", it does not exclude other components unless specifically stated to the contrary .

Furthermore, the terms " first ", " second ", and the like are used to distinguish one element from another element, and the scope of the right should not be limited by these terms. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

FIG. 2 is a circuit diagram showing a gallium nitride based power switching device according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a driving transistor 110 and a power switching transistor of a gallium nitride based power switching device according to an embodiment of the present invention. 4 is a vertical cross-sectional view illustrating a load structure of a variable resistor 130 of a gallium nitride based power switching device according to an embodiment of the present invention. Referring to FIG. 4, The system power switching device includes a gate current booster 100 and a power switching transistor 200.

The gate current booster 100 receives a drive signal for turning on or off the power switching transistor 200 from a control circuit (not shown), amplifies the applied drive signal to generate a drive gate current, The drive gate current is applied to the gate terminal of the power switching transistor 200. [ At this time, the gate current booster 100 includes the driving transistor 110 and the variable resistor 130.

The source terminal of the driving transistor 110 is grounded and receives a driving signal through a gate terminal thereof. The drain terminal of the driving transistor 110 is connected to the gate terminal of the power switching transistor 200. At this time, the driving transistor 110 is a MOS-HFET having an AlGaN / GaN heterojunction structure epitaxially grown on a silicon substrate and includes a substrate 111, a buffer layer 112, a barrier layer 113, a cap layer 114, And may include a gate insulating layer 115, a first source electrode 116, a first drain electrode 117, a first gate electrode 118 and an insulating layer 119.

First, the substrate 111 is preferably a Si (Silicon) substrate which is suitable for depositing gallium nitride (GaN), but is not limited thereto. Here, the substrate 111 may have a thickness of about 625 占 25 占 and a resistivity of about 9000? 占 ㎝ m.

Further, although not shown, a nucleation layer, which is a layer for forming nuclei of crystal growth, may be formed on the substrate 111 before the barrier layer 113 is formed. Here, the nucleation layer prevents a melt-back phenomenon caused by reaction between the substrate 111 and the buffer layer 300. In this case, the meltback phenomenon refers to a phenomenon in which gallium contained in the buffer layer 112 is in contact with and reacts with the substrate 111 made of silicon. When a meltback phenomenon occurs, the crystallinity of the semiconductor device is destroyed. In addition, the nucleation layer may serve to enable the buffer layer 112 to be grown on top to be well wetted.

The buffer layer 112 is formed on the substrate 111 or the nucleation layer and can buffer the difference between the lattice constant and the thermal expansion coefficient between the substrate 111 and the barrier layer 400 formed on the substrate 111 . The buffer layer 112 is preferably made of a GaN-based material. However, the buffer layer 112 is not limited to the GaN-based material, and may be a GaN-based compound such as an AlGaN (Inuminum Gallium Nitride) And a compound layer of various compositions may be formed by a doping or ion implantation process. At this time, the thickness of the buffer layer 112 is preferably about 3 탆 to 4 탆, and preferably about 3.8 탆, but is not limited thereto.

A GaN-based channel layer (not shown) may be formed on the buffer layer 112 to a thickness of about 332 nm, but is not limited thereto.

인 것인 바람직하나, 버퍼층(112) 또는 채널층과의 계면에 분극 현상이 일어날 수 있는 한 GaN계 물질, InGaN계 물질 및 AlInGaN계 물질 등의 GaN 기반의 화합물을 다양하게 형성하여 적용할 수 있으며, 도핑 또는 이온 주입 공정으로 다양한 조성의 화합물 층을 형성하여 사용할 수 있다. 다만, 배리어층(113)과 버퍼층(112)을 모두 알루미늄(Al)을 포함하는 재질을 사용하는 경우에는 분극 현상을 일으키기 위하여 배리어층(113)에 포함된 알루미늄의 비율이 버퍼층(112)에 포함된 알루미늄의 비율보다 높아야 한다. 이 때, 배리어층(113)의 두께는 약 20nm, 바람직하게는 22.5nm인 것이 바람직하나 이에 한정되지 않는다.The barrier layer 113 is formed on the buffer layer 112 or the channel layer by sequentially stacking the buffer layer 112 of GaN or the channel layer of GaN and the barrier layer 113 of AlGaN to form a heterojunction thin film structure of AlGaN / Whereby a two-dimensional electron channel (2DEG) by polarization is formed at the interface thereof. Here, the barrier layer 113 is an AlGaN layer, for example,

A GaN-based material such as a GaN-based material, an InGaN-based material, and an AlInGaN-based material may be formed and applied in various forms as long as the polarization can occur at the interface with the buffer layer 112 or the channel layer , A doping process, or an ion implantation process. However, when a material including aluminum (Al) is used for both the barrier layer 113 and the buffer layer 112, the ratio of aluminum contained in the barrier layer 113 is included in the buffer layer 112 Aluminum ratio. At this time, the thickness of the barrier layer 113 is preferably about 20 nm, preferably about 22.5 nm, but is not limited thereto.

At this time, an undoped GaN-based cap layer 114 may be formed on the barrier layer 113 to a thickness of about 1.25 nm or 2 nm, but is not limited thereto.

The first source electrode 116 is formed on the source trench through the cap layer 114 and a part of the barrier layer 113 is etched so that the first source electrode 116 is symmetric with respect to the first drain electrode 117 and the gate trench, The gate insulating layer 115 and the cap layer 114 penetrate through the gate insulating layer 115 and the barrier layer 113, respectively. At this time, the first source electrode 116 is formed of Si / Ti / Al / Mo / Au (Silicon about 5 nm / Titanium about 20 nm / Aluminum about 60 nm / Molybdenum about 35 nm / Aurum about 50 nm) as Ohmic contacts, And alloying it at about 800 캜 for about 30 seconds in a nitrogen atmosphere, but the present invention is not limited thereto.

The first drain electrode 117 is formed in a drain trench formed by etching a part of the barrier layer 113 through the cap layer 114. The first source electrode 116 and the gate trench are symmetrical The gate insulating layer 115 and the cap layer 114 penetrate through the gate insulating layer 115 and the barrier layer 113, respectively. At this time, the first drain electrode 117 is formed of Si / Ti / Al / Mo / Au (about 5 nm / about 20 nm / about 60 nm / about 35 nm / About 50 nm), and then alloying the metal layer at about 800 캜 for about 30 seconds in a nitrogen atmosphere. However, the present invention is not limited thereto.

The gate insulating layer 115 may be formed by a plasma enhanced chemical vapor deposition (PECVD) process after the first source electrode 116 and the first drain electrode 117 are formed in the barrier layer 113 and the gate trench is etched. Chemical Vapor Deposition). Here, the gate insulating layer 115, less than about 1㎛ of silicon dioxide (SiO₂) material, preferably, but may be deposited so as to reach a thickness of about 33nm is not limited to this, SiN _x, Al ₂ O _3, HfO _2, and so on.

Further, the first gate electrode 118 is formed by depositing a metal thin film on a gate insulating layer 115 deposited on a gate trench, with a Schottky junction. Here, the first gate electrode 118 may be formed by depositing a metal thin film of Mo / Au (Molybdenum about 20 nm / Aurum about 200 nm), but is not limited thereto. At this time, the source electric field electrode 121 is deposited on the first source electrode 116, the drain field electrode 122 is deposited on the first drain electrode 117 by depositing a metal thin film of Mo / Au (about 20 nm / about 200 nm) But is not limited thereto.

The gate trenches are recessed to the buffer layer 112 or the channel layer to ensure a normally non-conductive property, and when formed with the structure as described above, the threshold voltage may be about 2V.

The insulating layer 119 can be deposited on the structure in which the source electrode 121 and the like are formed. At this time, it is preferable that the insulating layer 119 is formed of silicon nitride (SiN _x ). However, the insulating layer 119 is not limited thereto and all insulating materials such as SiO 2, Al ₂ O ₃ and HfO ₂ can be applied.

Thereafter, a contact hole extending to the source and drain elec- trodes 121 and 122 is formed in the insulating layer 119 by using a lithography and etching process, for example, a reactive ion etching process, HFET structure as shown in FIG. 3 may be formed by depositing a metal such as tungsten in the contact holes on the metal layer 121 and then depositing a field plate metal layer.

The power switching transistor 200 has the same structure as that of the driving transistor 110 described above except that the power source switching transistor 200 is connected to the first source electrode 116 and the first drain electrode 117 through the source- Drain distance (for example, 20 占 퐉) between the second source electrode and the second drain electrode on the stack structure of the power switching transistor 200 is larger than the distance (for example, 10 占 퐉) And may be formed to have a distance of two times.

The variable resistor 130 is connected at one end to the gate terminal of the power switching transistor 200 and the other end is connected to the first power source. The resistance of the variable resistor 130 is measured by a sheet resistance obtained by Transmission Line Measurements (TLM) dimensional electron channel layer of heterogeneous junctions of AlGaN / GaN, The variable resistor 130 has an AlGaN / GaN heterojunction structure epitaxially grown on a silicon substrate and includes a substrate 111, a buffer layer 112, a barrier layer 113, a cap layer 114, a gate insulating layer 115, a first ohmic electrode 131, a second ohmic electrode 132, and an insulating layer 119.

Since the variable resistor 130 is integrated on the same chip as the driving transistor 110, the description of the structure that overlaps with that of the driving transistor 110 will be omitted for the sake of convenience.

On the other hand, the first ohmic electrode 131 is formed in the trench formed by etching the part of the barrier layer 113 through the cap layer 114. At this time, the first ohmic electrode 131 is formed of Si / Ti / Al / Mo / Au (Silicon having a thickness of about 5 nm / nm) as Ohmic contacts together with the first source electrode 116 and the first drain electrode 117, Titanium about 20 nm / Aluminum about 60 nm / Molybdenum about 35 nm / Aurum about 50 nm), and then alloying the metal layer at about 800 ° C. for about 30 seconds in a nitrogen atmosphere. However, the present invention is not limited thereto.

The second ohmic electrode 132 is formed in the trench formed by etching the part of the barrier layer 113 through the cap layer 114. [ At this time, the second ohmic electrode 132 is formed of Si / Ti / Al / Si with the first source electrode 116, the first drain electrode 117, and the first ohmic electrode 131 as Ohmic contacts. But is not limited to, depositing a metal layer of Mo / Au (about 5 nm / about 20 nm / about 60 nm / about 35 nm / about 50 nm) and alloying it at about 800 ° C. for about 30 seconds in a nitrogen atmosphere.

The first electric field electrode 141 is formed on the first ohmic electrode 131 and the second electric field electrode 142 is formed on the second ohmic electrode 132 by depositing a metal thin film of Mo / Au (about 20 nm / about 200 nm) But is not limited thereto.

At this time, the insulating layer 119 may be deposited on the structure in which the first electric field electrode 141 and the like are formed. Thereafter, contact holes extending to the first electric field electrode 141 and the second electric field electrode 142 can be formed in the insulating layer 119 using a lithography and etching process, for example, a reactive ion etching process.

The gate current booster 100 as described above amplifies the low level drive signal of a control circuit (not shown), and the boosted current enables fast charge and discharge in response to the gate capacitance of the power switching transistor 200. The gate current booster 100 includes a driving transistor 110 which is a recessed normally-off AlGaN / GaN MOS-HFET replacing the NMOS and PMOS portions of the conventional CMOS structure, And a variable resistor 130, which is a resistance of a resistor (Mesa).

Here, the resistance load of the variable resistor 130 is implemented as an AlGaN / GaN 2DEG channel layer designed as a sheet resistance value obtained by a transmission line measurement (TLM) as shown in FIG. The 2DEG sheet resistance is much larger than the metal-based thin film resistor, so the chip area required for the inverter stage can be much smaller. Further, since the laminated structure of the AlGaN / GaN MOS-HFET is used as it is, no additional processing step is required to fabricate the resistor. In the monolithic chip fabrication in which the gate current booster 100 and the power switching transistor 200 are integrated, the normally-closed AlGaN / GaN MOS-HFET as the driving transistor 110 is connected to the power switching FET 200, Can be produced at the same time. That is, as with the variable resistor 130, no additional process is required for monolithic integration of the driving transistor 110 and the power switching transistor 200.

)는 가변 저항(130)의 하기 수학식 1에 따라 부하 저항 값(

)에 의해 결정된다.Unlike the conventional CMOS inverter, the output charge current ("

Of the variable resistor 130 according to the following expression (1) of the variable resistor 130

).

는 전원 전압이고,

는 구동 트랜지스터(110)의 턴온 시 드레인 소스 간 전압을 의미한다.here,

Is a power supply voltage,

Means a drain-source voltage when the driving transistor 110 is turned on.

) 및 출력 전압(

) 파형을 도시한 그래프로, 게이트 전류 부스터(100)의 안전한 스위칭 동작을 보장하기 위하여, 구동 트랜지스터(110)인 AlGaN/GaN MOS-HFET의 온 상태 전압 강하는 전력 스위칭 트랜지스터(200)의 게이트 임계 전압보다 충분히 작도록 설정될 수 있다.5 is a graph showing the relationship between the input voltage (FIG. 5) of the driving transistor 110 in the gallium nitride based power switching apparatus according to an embodiment of the present invention

) And the output voltage (

The on-state voltage drop of the AlGaN / GaN MOS-HFET, which is the driving transistor 110, is determined by the gate threshold of the power switching transistor 200, The voltage can be set to be sufficiently smaller than the voltage.

FIG. 6A is an integrated image of a gallium nitride-based power switching device manufactured by an embodiment of the present invention, and FIG. 6B is a circuit diagram corresponding to the image of FIG. 6A. FIG. 4 is a cross-sectional view of the drive transistor 110 region (Drive AlGaN / GaN) of FIG. 6A. FIG. MOS-HFET) and a power switching transistor 200 region (Switching AlGaN / GaN MOS-HFET) in the A to A direction.

The power switching transistor 200 may have a total channel width Wg of about 20 mm and a source-drain distance of about 20 m and the driving transistor 110 may have a total channel width of about 10 mm and a source- Have a distance. The source-gate distance and the gate length of the power switching transistor 200 and the driving transistor 110 may be formed to be about 3 mu m and 2 mu m, respectively.

The variable resistor 130 may have a variable load resistance structure composed of four series-connected mesa resistors R1, R2, R3, and R4. Here, the active region of each mesa resistor may have a width of about 400 mu m and a length of about 40 mu m.

은 구동 트랜지스터(110)의 턴온 전압이므로, 구동 트랜지스터(110)는 높은 항복 전압을 가질 필요가 없다. 또한, 도 4와 같은 구조로 제작된 저항의 TLM 패턴으로부터 측정한 AlGaN/GaN 활성층의 시트 저항은 340Ω/sq이다.6B

On voltage of the driving transistor 110, the driving transistor 110 need not have a high breakdown voltage. The sheet resistance of the AlGaN / GaN active layer measured from the TLM pattern of the resistor fabricated as shown in Fig. 4 is 340? / Sq.

FIG. 7A is a circuit diagram of a gallium nitride-based power switching device manufactured according to an embodiment of the present invention, connected to a test circuit board. FIG. 7B is an image showing an example of implementing the circuit of FIG. 7A. Respectively.

To investigate the switching characteristics of the gallium nitride based power switching device of the present invention, a gallium nitride based power switching device fabricated in the form of a monolithic integrated chip as shown in Figs. 6A and 6B was tested as shown in Fig. 7B Diced and attached to a printed circuit board (PCB), and a monolithic integrated chip can be connected to a test PCB pad using 1 mil gold wire and a ball bonder.

은 10V로, 전력 스위칭 트랜지스터(200)(AlGaN/GaN MOS-HFET)의 경우

는 200V로 설정될 수 있다. 게이트 전류 부스터(100)에 대한 입력 구동 신호는 10mA 인 전류 소스에 있어서 0/10V이다. 이때, 입력 구동 신호는 1 MHz의 주파수 및 50% 듀티 사이클을 가진다. 전력 스위칭 트랜지스터(200)(AlGaN/GaN MOS-HFET)의 게이트 전하(

)는

=10V,

=330mA 및

= 200V에서 5.6nC이다.As shown in FIG. 7A, in the case of the gallium nitride-based gate current booster 100

Is 10 V, and in the case of the power switching transistor 200 (AlGaN / GaN MOS-HFET)

May be set to 200V. The input drive signal to the gate current booster 100 is 0 / 10V for a current source of 10mA. At this time, the input driving signal has a frequency of 1 MHz and a duty cycle of 50%. The gate charge of power switching transistor 200 (AlGaN / GaN MOS-HFET)

)

= 10V,

= 330 mA and

= 5.6 nC at 200V.

=10V에서 44, 82, 121 및 160Ω이다. 도 8b에서, 4개의 서로 다른 저항을 갖는 부하에 의한 특성 곡선들이 함께 표시된다. 도 8c에 도시된 바와 같은 특성을 가지는 전력 스위칭 트랜지스터(200)(

= 20mm)의 정적 온-저항 값은 1.93Ω이다.The general voltage-current characteristics of a gallium nitride based power switching device fabricated in the form of a monolithic integrated chip as shown in Figs. 6A and 6B are shown in Figs. 8A to 8C. As shown in FIG. 8A, the resistance values of R1, R1 to R2, R1 to R3, and R1 to R4 are

= 44, 82, 121 and 160? At 10V. In Fig. 8B, characteristic curves by loads with four different resistances are shown together. The power switching transistor 200 (FIG. 8C) having characteristics as shown in FIG.

= 20 mm) is 1.93 ?.

As a result of comparing the switching characteristics of the power switching transistor 200 according to the load resistance value of the variable resistor 130 when the gate current booster 100 is not used and when the gate current booster 100 is used Are shown in Table 1 below.

According to Table 1, as the load resistance value of the variable resistor 130 is changed using a dip (DIP) switch, the input current of the gate current booster 100 of 10 mA is 225.7, 121.6, 82.5 That is, boosted, by the gate input current of the power switching transistor 200, which is 62.4 mA.

Also, in the monolithically integrated gate current booster 100, the turn-on and turn-off transition times can be greatly reduced. For example, if 'R1 only' is used as a resistive load, as shown in Table 1, the gate input current of the power switching transistor 200 increases to 225.7 mA at maximum, the turn-on time decreases from 626 to 41.26 ns, Can be shortened from 554 to 42.19 ns. The off-gate voltage of the power switching transistor 200 equal to the on-voltage drop of the driving transistor 110 in the gate current booster 100 is still at 0.58 V, which is still lower than the threshold voltage (= 2 V).

9A and 9B show the turn on (FIG. 9A) and turn off (FIG. 9B) gate drive waveforms of the power switching transistor 200 as the load resistance value of the variable resistor 130 in the gate current booster 100 is changed Respectively.

In order to examine the advantages of the monolithic integration, a graph comparing the switching characteristics of a monolithic integrated device with a device in which a gate current booster of an external circuit type is connected to a power switching transistor is shown in FIGS. 10A and 10B. At this time, the inductance of the external circuit is about 25nH. As shown in Figs. 10A and 10B, overshoot and ringing are remarkably suppressed by monolithic integration. During the turn-on period, the ringing level decreased from 41% to 7.6%, and the ringing level of the turn-off period decreased from 25% to 0%. In addition, the lengths of the turn-on and turn-off times are significantly reduced.

가 200V일 때 단 6.7%에 불과하다.11 is a graph showing dynamic switching characteristics of the gallium nitride based power switching device of the present invention in which the gate current booster 100 is monolithically integrated. That is, FIG. 11 is a result of testing by setting the frequency of the driving signal input to the gate current booster 100 to 1 MHz and measuring the hard switching waveform. As shown in FIG. 11, the power switching transistor 200 exhibited very stable dynamic characteristics. The dynamic on-resistance increase

Is only 6.7% when it is 200V.

FIGS. 12A and 12B are graphs showing the switching characteristics of the gallium nitride based power switching device of the present invention monolithically integrated with the gate current booster 100, FIGS. 12C and 12D are graphs showing the gate current booster 100, And the switching loss during the turn-on and turn-off periods is calculated by integrating the power loss with respect to the switching time as shown in the following Equation 2. " (2) "

는 스위칭 손실,

및

는 각각 턴온 및 턴 오프 시간 기간이며

는 스위칭 주파수이다. 총 스위칭 손실은 하기 표 2에 도시된 바와 같이 5.27에서 0.55W로 크게 감소한다.here

Switching losses,

And

Are turn-on and turn-off time periods, respectively

Is the switching frequency. The total switching loss is greatly reduced from 5.27 to 0.55 W as shown in Table 2 below.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the invention. Accordingly, the technical scope of the present invention should be determined by the appended claims.

100: Gate current booster
110: driving transistor
130: Variable resistance
200: Power switching transistor

Claims (7)

A gallium nitride based power switching device having a monolithic integrated circuit chip structure formed by integrating a power switching transistor and a gate current booster for receiving a driving signal of the power switching transistor and amplifying the driving signal to generate a driving gate current, As a result,
The gate current booster includes:
A source terminal connected to the gate of the power switching transistor, and a drain terminal connected to a gate terminal of the power switching transistor; And
A variable resistor connected at one end to a gate terminal of the power switching transistor and at the other end to a first power supply to provide a variable resistance value,
Wherein the driving transistor is always inactive.
The method according to claim 1,
The driving transistor includes:
Board;
A buffer layer which is a gallium nitride material formed on the substrate;
A barrier layer which is an aluminum gallium nitride-based material formed on the buffer layer;
A gate insulating layer formed on the barrier layer;
A first source electrode and a first drain electrode which are located in contact with the barrier layer through the gate insulating layer; And
And a first gate electrode located between the first source electrode and the first drain electrode and spaced apart from the barrier layer by the gate insulating layer.
The method according to claim 1,
The variable resistor comprises:
Board;
A buffer layer which is a gallium nitride material formed on the substrate;
A barrier layer which is an aluminum gallium nitride-based material formed on the buffer layer;
A gate insulating layer formed on the barrier layer; And
And a first ohmic electrode and a second ohmic electrode disposed in contact with the barrier layer through the gate insulating layer.
The method of claim 2,
The variable resistor comprises:
The substrate;
The buffer layer;
The barrier layer;
The gate insulating layer; And
And a first ohmic electrode and a second ohmic electrode disposed in contact with the barrier layer through the gate insulating layer.
The method according to claim 1,
Wherein the power switching transistor comprises:
Board;
A buffer layer which is a gallium nitride material formed on the substrate;
A barrier layer which is an aluminum gallium nitride-based material formed on the buffer layer;
A gate insulating layer formed on the barrier layer;
A second source electrode and a second drain electrode penetrating the gate insulating layer and located in contact with the barrier layer; And
And a second gate electrode located between the second source electrode and the second drain electrode and spaced apart from the barrier layer by the gate insulating layer.
The method according to claim 2 or 4,
Wherein the power switching transistor comprises:
The substrate;
The buffer layer;
The barrier layer;
The gate insulating layer;
A second source electrode and a second drain electrode penetrating the gate insulating layer and located in contact with the barrier layer; And
And a second gate electrode located between the second source electrode and the second drain electrode and spaced apart from the barrier layer by the gate insulating layer.
The method of claim 6,
Wherein a first distance that is a source-drain distance of the first source electrode and the first drain electrode is equal to a half of a second distance that is a source-drain distance of the second source electrode and the second drain electrode, Power switching device.

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