CN113342733A - EthPMC protocol processor and processing method thereof - Google Patents
EthPMC protocol processor and processing method thereof Download PDFInfo
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- CN113342733A CN113342733A CN202110630004.8A CN202110630004A CN113342733A CN 113342733 A CN113342733 A CN 113342733A CN 202110630004 A CN202110630004 A CN 202110630004A CN 113342733 A CN113342733 A CN 113342733A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
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Abstract
The invention discloses an EthPMC protocol processor and a processing method thereof, comprising a downlink processing unit and an uplink processing unit; the downlink processing unit comprises a write cache module, a downlink frame cache module, a downlink selector module, a verification generation module, a merging module, an RMII sending interface, an RMII receiving interface and a microprocessor write interface; the uplink processing unit comprises a reading buffer module, an uplink frame buffer module, a check and check module, a merging module, an RMII receiving interface, an RMII sending interface and a microprocessor reading interface; the invention uses Ethernet transmission, has the advantage of high communication rate, uses Ethernet verification, has the advantage of high fault tolerance, adds a cache function and has the advantage of low processing delay.
Description
Technical Field
The invention belongs to the technical field of industrial Ethernet, and particularly relates to an EthPMC protocol processor and a processing method thereof.
Background
The industrial Ethernet is a scheme for realizing a field bus based on the Ethernet technology, is applied to an industrial control neighborhood, is compatible with the traditional Ethernet technology standard IEEE802.3/802.3u, follows all or part of communication protocols of an ISO/OSI open system interconnection reference model, and has stronger real-time property, reliability, anti-interference property and interoperability in order to be applied to a harsh industrial environment.
The traditional protocol processor has the defects of low communication rate, low fault tolerance, high processing delay and the like.
Disclosure of Invention
The present invention provides an EthPMC protocol processor and a processing method thereof, which have the advantages of high communication rate, high fault tolerance and low processing delay.
In order to achieve the technical purpose, the technical scheme adopted by the invention is as follows:
an EthPMC protocol processor comprises a downlink processing unit and an uplink processing unit;
the downlink processing unit comprises a write cache module, a downlink frame cache module, a downlink selector module, a verification generation module, a merging module, an RMII sending interface, an RMII receiving interface and a microprocessor write interface; the write cache module is connected with the microprocessor through a microprocessor write interface, the downlink frame cache module is connected with the preceding-stage Ethernet physical chip through an RMII receiving interface, the write cache module and the downlink frame cache module are both connected with the downlink selector module, the downlink selector module is simultaneously connected with the microprocessor write interface, the check generation module and the merging module, the check generation module is connected with the merging module, and the merging module is connected with the succeeding-stage Ethernet physical chip through an RMII sending interface;
the uplink processing unit comprises a reading buffer module, an uplink frame buffer module, a check and check module, a merging module, an RMII receiving interface, an RMII sending interface and a microprocessor reading interface; the uplink frame buffer module is connected with the rear-stage Ethernet physical chip through an RMII receiving interface, the reading buffer module is connected with the microprocessor through a microprocessor reading interface, the uplink frame buffer module is simultaneously connected with the checking and checking module and the merging module, the checking and checking module is simultaneously connected with the merging module and the microprocessor reading interface, and the merging module is connected with the front-stage Ethernet physical chip through an RMII sending interface.
In order to achieve the technical purpose, the invention adopts another technical scheme as follows:
a processing method of an EthPMC protocol processor comprises the following steps:
the processing method of the downlink processing unit comprises the following steps: the preceding-stage Ethernet physical chip sends a downlink frame to an RMII receiving interface, the downlink frame is written into a downlink frame cache module through the RMII receiving interface, and the microprocessor writes data into a write cache module through a microprocessor write interface; the microprocessor writes parameters into a downlink selector module through a microprocessor writing interface, the downlink selector module selects whether data is read from a writing cache module or a downlink frame cache module according to the parameters, the downlink selector module outputs downlink frame data, a check generation module generates a check code according to the downlink frame data, the downlink frame data and the check code are combined through a combination module to obtain a complete EthPMC downlink frame, and the EthPMC downlink frame is output to a rear-stage Ethernet physical chip through an RMII sending interface;
the processing method of the downlink processing unit comprises the following steps: the method comprises the steps that an uplink frame is sent to an RMII receiving interface by a rear-stage Ethernet physical chip, the uplink frame is written into an uplink frame caching module and a reading caching module through the RMII receiving interface, the reading caching module reads data in a microprocessor through a microprocessor reading interface, the uplink frame caching module outputs uplink frame data, the uplink frame data are checked by a checking and checking module to obtain a checking result and a checking code, the checking result is read by the microprocessor through the microprocessor reading interface, the checking code and the uplink frame data are combined through a combining module to obtain a complete EthPMC uplink frame, and the EthPMC uplink frame is output to a front-stage Ethernet physical chip through the RMII sending interface.
As the further improved technical scheme of the invention, the signals processed by the writing interface of the microprocessor comprise writing effective signals, writing address signals and writing data signals; the signals processed by the microprocessor read interface comprise a read valid signal, a read address signal and a read data signal.
The invention has the beneficial effects that:
the invention realizes the protocol processor structure of the data link layer in the definition of the industrial Ethernet EthPMC and also provides a corresponding data processing method. Compared with the traditional bus protocol processor, the Ethernet transmission is used, the advantage of high communication rate is achieved, the Ethernet verification is used, the advantage of high fault tolerance is achieved, the cache function is added, and the advantage of low processing delay is achieved.
Drawings
FIG. 1 is a schematic view of the structure of the present invention.
Fig. 2 is a diagram of a data processing procedure of a downlink processing unit according to the present invention.
Fig. 3 is a data processing process diagram of an uplink processing unit according to the present invention.
Fig. 4 is a schematic diagram of signal transmission between the RMII receiving interface and the ethernet physical chip according to the present invention.
Fig. 5 is a schematic diagram of signal transmission between an RMII transmission interface and an ethernet physical chip according to the present invention.
Fig. 6 is a schematic diagram of signal transmission between an EthPMC protocol processor and a microprocessor according to the present invention.
Detailed Description
The following further description of embodiments of the invention is made with reference to the accompanying drawings:
an EthPMC protocol processor comprises a downlink processing unit and an uplink processing unit.
As shown in fig. 1 and fig. 2, the downlink processing unit includes a write buffer module, a downlink frame buffer module, a downlink selector module, a verification generation module, a merging module, an RMII sending interface, an RMII receiving interface, and a microprocessor write interface; the write cache module is connected with the microprocessor through a microprocessor write interface, the downlink frame cache module is connected with the preceding-stage Ethernet physical chip through an RMII receiving interface, the write cache module and the downlink frame cache module are both connected with the downlink selector module, the downlink selector module is simultaneously connected with the microprocessor write interface, the check generation module and the merging module, the check generation module is connected with the merging module, and the merging module is connected with the subsequent-stage Ethernet physical chip through an RMII sending interface.
The downlink data stream is from left to right as shown in the structure of fig. 2, the downlink frame is written into the downlink frame buffer module through the RMII receiving interface, and the microprocessor writes the data into the write buffer module through the microprocessor writing interface; the microprocessor writes a data offset parameter and a data size parameter into the downlink selector module through the microprocessor write interface, the downlink selector module selects whether data is read from the write cache module or the downlink frame cache module according to the parameters, the downlink selector module outputs downlink frame data and verifies and generates a verification code according to the downlink frame data, the downlink frame data and the verification code are combined to obtain a complete EthPMC downlink frame, and the complete EthPMC downlink frame is output through the RMII sending interface.
As shown in fig. 1 and fig. 3, the uplink processing unit includes a read buffer module, an uplink frame buffer module, a check module, a merge module, an RMII receiving interface, an RMII sending interface, and a microprocessor read interface; the uplink frame buffer module is connected with the rear-stage Ethernet physical chip through an RMII receiving interface, the reading buffer module is connected with the microprocessor through a microprocessor reading interface, the uplink frame buffer module is simultaneously connected with the checking and checking module and the merging module, the checking and checking module is simultaneously connected with the merging module and the microprocessor reading interface, and the merging module is connected with the front-stage Ethernet physical chip through an RMII sending interface.
According to the right-to-left in fig. 3, an uplink data stream is written into an uplink frame buffer module and a read buffer module through an RMII receiving interface, data in the read buffer module can be directly read by a microprocessor through a microprocessor read interface, data in the uplink frame buffer module is output to obtain uplink frame data, a check result and a check code are obtained through check of a check module, the check result is read by the microprocessor through the microprocessor read interface, the check code and the uplink frame data are combined through a combining module to obtain a complete EthPMC uplink frame, and the EthPMC uplink frame is output through an RMII sending interface.
The RMII is collectively referred to as a simplified media independent interface, defined in the IEEE-802.3u standard.
As shown in FIG. 4, the RMII receive interface includes a receive data valid signal CRS _ DV, receive data signals RXD [1:0] and a reference clock signal REF _ CLK. The received data valid signal CRS _ DV and the received data signal RXD [1:0] are output to the EthPMC protocol processor by an Ethernet physical chip (namely a front-stage Ethernet physical chip or a rear-stage Ethernet physical chip, which is called the Ethernet physical chip for short). The reference clock signal REF _ CLK is provided by an external clock source and is output to the EthPMC protocol processor and the Ethernet physical chip, and the frequency of the reference clock signal REF _ CLK is 50 MHz.
As shown in FIG. 5, the RMII transmit interface includes transmit data valid information TX _ EN, transmit data signals TXD [1:0], and a reference clock signal REF _ CLK. The transmission data valid information TX _ EN and the transmission data signal TXD [1:0] are output to an ethernet physical chip (i.e., a front-stage ethernet physical chip or a rear-stage ethernet physical chip, which is referred to as an ethernet physical chip for short) by the EthPMC protocol processor. The reference clock signal REF _ CLK is provided by an external clock source and is output to the EthPMC protocol processor and the Ethernet physical chip, and the frequency of the reference clock signal REF _ CLK is 50 MHz.
The microprocessor interface is an interface between the microprocessor and the EthPMC protocol processor and comprises a microprocessor read interface and a microprocessor write interface.
As shown in fig. 6, the microprocessor write interface includes a write valid signal, a write address signal and a write data signal, and the write interface signals are all output by the microprocessor to the EthPMC protocol processor.
As shown in fig. 6, the microprocessor read interface includes a read valid signal, a read address signal and a read data signal, wherein the read valid signal and the read address signal are output to the EthPMC protocol processor by the microprocessor, and the read data signal is returned to the microprocessor by the EthPMC protocol processor.
The embodiment also provides a processing method of the EthPMC protocol processor, which includes a downlink processing method of the downlink processing unit and an uplink processing method of the uplink processing unit.
The processing method of the downlink processing unit comprises the following steps:
the preceding-stage Ethernet physical chip sends a downlink frame to an RMII receiving interface, the downlink frame is written into a downlink frame cache module through the RMII receiving interface, and the microprocessor writes data into a write cache module through a microprocessor write interface; the microprocessor writes parameters into a downlink selector module through a microprocessor writing interface, the downlink selector module selects whether data is read from a writing cache module or a downlink frame cache module according to the parameters, the downlink selector module outputs downlink frame data, a check generation module generates a check code according to the downlink frame data, the downlink frame data and the check code are combined through a combination module to obtain a complete EthPMC downlink frame, and the EthPMC downlink frame is output to a rear-stage Ethernet physical chip through a RMII sending interface.
The processing method of the downlink processing unit comprises the following steps:
the method comprises the steps that an uplink frame is sent to an RMII receiving interface by a rear-stage Ethernet physical chip, the uplink frame is written into an uplink frame caching module and a reading caching module through the RMII receiving interface, the reading caching module reads data in a microprocessor through a microprocessor reading interface, the uplink frame caching module outputs uplink frame data, the uplink frame data are checked by a checking and checking module to obtain a checking result and a checking code, the checking result is read by the microprocessor through the microprocessor reading interface, the checking code and the uplink frame data are combined through a combining module to obtain a complete EthPMC uplink frame, and the EthPMC uplink frame is output to a front-stage Ethernet physical chip through the RMII sending interface.
The embodiment realizes the protocol processor structure of the data link layer in the industrial Ethernet EthPMC definition and also provides a corresponding data processing method. Compared with the traditional bus protocol processor, the Ethernet transmission is used, the advantage of high communication rate is achieved, the Ethernet verification is used, the advantage of high fault tolerance is achieved, the cache function is added, and the advantage of low processing delay is achieved.
The scope of the present invention includes, but is not limited to, the above embodiments, and the present invention is defined by the appended claims, and any alterations, modifications, and improvements that may occur to those skilled in the art are all within the scope of the present invention.
Claims (3)
1. An EthPMC protocol processor, comprising: comprises a downlink processing unit and an uplink processing unit;
the downlink processing unit comprises a write cache module, a downlink frame cache module, a downlink selector module, a verification generation module, a merging module, an RMII sending interface, an RMII receiving interface and a microprocessor write interface; the write cache module is connected with the microprocessor through a microprocessor write interface, the downlink frame cache module is connected with the preceding-stage Ethernet physical chip through an RMII receiving interface, the write cache module and the downlink frame cache module are both connected with the downlink selector module, the downlink selector module is simultaneously connected with the microprocessor write interface, the check generation module and the merging module, the check generation module is connected with the merging module, and the merging module is connected with the succeeding-stage Ethernet physical chip through an RMII sending interface;
the uplink processing unit comprises a reading buffer module, an uplink frame buffer module, a check and check module, a merging module, an RMII receiving interface, an RMII sending interface and a microprocessor reading interface; the uplink frame buffer module is connected with the rear-stage Ethernet physical chip through an RMII receiving interface, the reading buffer module is connected with the microprocessor through a microprocessor reading interface, the uplink frame buffer module is simultaneously connected with the checking and checking module and the merging module, the checking and checking module is simultaneously connected with the merging module and the microprocessor reading interface, and the merging module is connected with the front-stage Ethernet physical chip through an RMII sending interface.
2. A method of processing an EthPMC protocol processor according to claim 1, comprising:
the processing method of the downlink processing unit comprises the following steps:
the preceding-stage Ethernet physical chip sends a downlink frame to an RMII receiving interface, the downlink frame is written into a downlink frame cache module through the RMII receiving interface, and the microprocessor writes data into a write cache module through a microprocessor write interface; the microprocessor writes parameters into a downlink selector module through a microprocessor writing interface, the downlink selector module selects whether data is read from a writing cache module or a downlink frame cache module according to the parameters, the downlink selector module outputs downlink frame data, a check generation module generates a check code according to the downlink frame data, the downlink frame data and the check code are combined through a combination module to obtain a complete EthPMC downlink frame, and the EthPMC downlink frame is output to a rear-stage Ethernet physical chip through an RMII sending interface;
the processing method of the downlink processing unit comprises the following steps:
the method comprises the steps that an uplink frame is sent to an RMII receiving interface by a rear-stage Ethernet physical chip, the uplink frame is written into an uplink frame caching module and a reading caching module through the RMII receiving interface, the reading caching module reads data in a microprocessor through a microprocessor reading interface, the uplink frame caching module outputs uplink frame data, the uplink frame data are checked by a checking and checking module to obtain a checking result and a checking code, the checking result is read by the microprocessor through the microprocessor reading interface, the checking code and the uplink frame data are combined through a combining module to obtain a complete EthPMC uplink frame, and the EthPMC uplink frame is output to a front-stage Ethernet physical chip through the RMII sending interface.
3. The EthPMC protocol processor processing method according to claim 2, wherein:
the signals processed by the microprocessor writing interface comprise writing effective signals, writing address signals and writing data signals;
the signals processed by the microprocessor read interface comprise a read valid signal, a read address signal and a read data signal.
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Cited By (1)
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