CN101917316A - Communication method and device for high-speed real-time industrial Ethernet - Google Patents

Abstract

The invention discloses a communication method and device of a high-speed real-time Ethernet bus. The method includes: data transmission adopts the general frame mode, and by analyzing the addresses of the data segments of each slave station in the data message, each slave station passes through the pair after the addresses are matched. The corresponding fields in the frame are exchanged to achieve the purpose of non-competition data transmission to meet the real-time performance of the system. The concrete implementation of the present invention is the communication device of the high-speed real-time bus that constitutes by general network card chip and FPGA, and wherein FPGA is mainly to complete the function of data packet receiving, parsing, forwarding according to transmission protocol, and described method and device have data frame and can arrive in time The target device meets the real-time requirements of data transmission; the mechanism of data transmission is receiving, parsing, and forwarding at the same time, without competition and preemption, and real-time performance is achieved. The general Ethernet chip is used as the physical layer. Compared with traditional industrial The bus increases the transfer speed.

Description

Communication method and device for high-speed real-time industrial Ethernet

technical field

The invention relates to the fields of high-speed data transmission application and robot control, in particular to a high-speed real-time bus communication method and device.

Background technique

Internationally advanced CNC machine tools and industrial robot control systems use fieldbus to connect digital servos and IO devices to form a fieldbus computer control system. The performance of the field bus of the CNC system team requires real-time bus transmission, synchronization of command execution and status feedback, and periodicity of command transmission. These characteristics of existing buses (such as CAN bus, Ethernet, etc.) are due to their real-time and communication capabilities. Due to bandwidth and other reasons, it is not suitable for use in numerical control systems.

Traditional Ethernet solutions that provide real-time functions mostly prohibit the CSMA/CD access process through a higher-level protocol layer, and use time slices or polling processes to replace it, or use dedicated switches, and distribute Ethernet with precise time control. network packets. However, the bandwidth utilization of these solutions is very low, and the time required to redirect to the output or drive controller and read data depends mainly on the implementation method, and the delay of communication bus transmission cannot be avoided.

Contents of the invention

The purpose of the present invention is to provide a high-speed real-time industrial Ethernet communication method and device to solve the problems of real-time data transmission and the like.

A high-speed real-time industrial Ethernet communication method described in the present invention uses a self-defined protocol, an accurate clock synchronization method, and a total frame transmission method to fill in the data of each slave station into the corresponding field in the frame. The communication method includes: :

When the data frame arrives, the slave station first addresses, that is, finds the data segment of the station in the total frame;

After the address is matched, the slave station performs corresponding read and write operations according to the commands in the data segment of the station;

During data processing, the slave station receives, parses, and forwards data while transmitting 2 bits per clock tick.

The communication method of a kind of high-speed real-time industrial Ethernet described in the present invention can meet the transmission requirements of oneself by modifying the frame structure of the common Ethernet frame to reach the frame structure of the communication protocol, and can transmit through the common Ethernet chip again; the protocol frame In the structure, the Ethernet type field in the ordinary Ethernet frame structure remains unchanged, the destination address and source address are set as reserved words, and the length, control, and data fields are customized as required. The specific fields mainly include: reserved words, Ethernet type (this field can define two different Ethernet protocols), CASNET header (this field includes the total length of each slave data field and the type of CASNET, and this section combines Ethernet The type field judges whether the data frame is a CASNET frame), sub-message (which is the data field of each slave station), and CRC redundancy check.

In the communication method of a high-speed real-time industrial Ethernet described in the present invention, each slave station first judges whether the data frame is a data packet to be transmitted by the system when the data frame arrives, and if it is judged to be the required data packet, it receives and sends Do follow-up processing, otherwise discard; this process requires besides judging the Ethernet type, mark the fixed bit at the head of the protocol frame mechanism, so the Ethernet type and this mark jointly determine whether the data packet supported by this protocol.

In the communication method of a high-speed real-time industrial Ethernet described in the present invention, each slave station first needs to have parameters such as local address, operation command, internal register offset address, length to be processed, etc. in the process of accessing data;

Addressing, find the data segment of the respective slave station in the frame;

Take the command word, data bit length, and address offset corresponding to the command processing of the data segment of the station, and perform corresponding processing in the station through these main fields.

The communication method of a kind of high-speed real-time industrial ethernet of the present invention, in order to reach this characteristic of real-time, this system selects real-time (as UCOS II) operating system for use, in the data transmission process, system runs under a real-time task always, Real-time data transmission can be realized.

A kind of communication method of high-speed real-time industrial Ethernet described in the present invention, when master station and slave station utilize different clock sources, need a set of complete clock synchronization mechanism, in order to satisfy the clock synchronization requirement of the system, its key steps:

Line delay compensation, the master station reads the time stamp of the data frame passing through the slave station twice in the same cycle, calculates the transmission delay, and sends it to each slave station for delay compensation.

Clock start offset compensation, in the system initialization stage, the master station calculates the clock offset between each slave station and the reference slave station, and sends it to each slave station for offset compensation.

Drift compensation, through the addend registers, accumulators, and counters inside the FPGA, the output clock counters of each station are stabilized at the same frequency. In this method, the value of the addend register is adjusted by sending a synchronous data packet, and the counter adds 1 every time the accumulator value overflows, and the value of the counter is the value of the local clock.

In the communication method of a high-speed real-time industrial Ethernet described in the present invention, the drift compensation should be carried out regularly in the data communication process, that is, the master station should regularly send the synchronization packet for drift compensation in the data packet transmission process, and send The synchronous package makes the FPGA adjust the value in the addend register to adjust the clock output frequency.

A kind of high-speed real-time industrial Ethernet communication device of the present invention, the hardware selects common Ethernet physical chip, the interface selects common Ethernet port RJ45, the physical layer transmission is RMII protocol, and the data link layer is programmed through verilog in FPGA Realized; the modules in the FPGA include:

A receiving module for judging the type of data frame, address query and data processing;

A sending module for forwarding the processed data frame to the next slave station;

An interrupt is generated when a data frame arrives, an interrupt is generated when the receiving FIFO is full, and an interrupt is generated when the sending FIFO is full

interrupt interrupt control module;

Synchronization module unit for completing a series of operations of system clock synchronization;

In addition, there are units such as FIFO and μC interface.

A high-speed real-time industrial Ethernet communication device according to the present invention is characterized in that, by changing the interface of the application layer, it can be applied to a set of independent bus systems in different high-speed data transmission fields, the system master and slave stations They are all boards with ordinary network card chips and FPGA.

The invention mainly improves the data transmission rate in the field of field control by transforming and designing the common Ethernet and making full use of the transmission speed of the Ethernet. Using the total frame method, through the control program in the FPGA, the data transmission without competition mechanism can be achieved, and the data can be guaranteed to reach the target device in real time, thus providing better real-time performance of data transmission. In addition, the present invention adopts a synchronous method combining hardware and software, which provides a precise synchronous clock for the system.

Description of drawings

FIG. 1 is a schematic diagram of a frame structure of a lumped frame in the present invention.

Fig. 2 is a schematic diagram of the structure of each slave station data segment in the frame of the present invention.

Fig. 3 is a schematic diagram of the process of data exchange between the master and slave stations using the lumped frame method in the system of the present invention.

Fig. 4 is a flow chart of system initialization of the present invention.

Fig. 5 is a flow chart of synchronous packet transmission at regular intervals during the data transmission process of the present invention.

Fig. 6 is a block diagram of the slave station FPGA internal module of the present invention.

Fig. 7 is a block diagram of the hardware principle of the present invention.

FIG. 8 is a schematic diagram of field composition of each slave station data segment in the overall frame of FIG. 2 .

Detailed ways

The embodiment of the present invention provides a high-speed real-time bus communication method, which utilizes the transmission physical layer of the common Ethernet to greatly increase the transmission speed of the field bus.

Traditional Ethernet adopts CSMA/CD mode for data transmission. The present invention embeds the data fields of each slave station into a long frame by improving the ordinary Ethernet frame structure, that is, adopts the method of total frame, and there will be no competition in the process of data transmission. For problems such as preemption, during the transmission of data frames, when the entire frame flows through the slave station, the slave station performs operations such as reading and writing the corresponding fields in the frame through address matching and command judgment. As the frame passes through each device, the present invention reads the data corresponding to that device from the station controller. Likewise, device feedback data can be inserted into the message as it passes through.

The synchronization method of this system mainly adopts the combination of software and hardware, so that the synchronization accuracy of the system can reach within 1μs. During the transmission of data frames between stations, the data packets are mainly processed by hardware, with a CRC check process, which ensures that the bit error rate of data is very low during transmission and fully guarantees the reliability of data transmission .

In order to better illustrate the implementation of the method, the method will now be described in detail with reference to the accompanying drawings.

The specific implementation mode of the present invention provides a communication method of a high-speed industrial Ethernet real-time bus, and realizes a fast real-time field bus system through a self-defined transmission protocol and a general frame mode. Figure 1 shows the basic structure of the total frame, and the fields in Figure 1 mainly include:

Ethernet type, this field can define two different Ethernet protocols.

CASNET header, this field includes the total length of each slave data segment and the type of CASNET. Combine this segment with the Ethernet type field to judge whether the data frame is a CASNET frame.

Sub-messages are the command and data fields of each slave station.

CRC redundancy check.

Refer to FIG. 8 for the field composition of each slave station data segment in the total frame in FIG. 2 .

The communication between the master and slave stations is through the general frame method, and each cycle is initiated by the master station. The master station program packs the commands and data that need to be sent according to the above frame structure, and sends them out through the ordinary Ethernet port, that is, the main station of the master station. The job is to pack the data and do corresponding data operations. When the long data frame passes through each slave station, the slave station finds the data field of the station in the long frame by querying the station, fetches the command word, physical address offset, length, etc. in the field, and makes corresponding adjustments to the data segment of the station according to these data. deal with. The processing flow of the whole long frame online linear topology is shown in Fig. 3 .

The topology structure of the system is shown in Figure 4. The data frame transmission process: the data packet is sent by the master station, and then transmitted to each slave station along the linear topology. When it reaches the last slave station, the data frame returns along the original path, and the returned When the data frame passes through each slave station, it does not do any processing, and it is forwarded directly until the data frame returns to the master station.

The system running state mainly includes system initialization state and data communication state. These two states use the same data frame structure to complete the system initialization process and data communication process by filling in different data in the same field.

The flow chart of the system initialization process is shown in Figure 5. During the initialization process of the system, the main operations are: send the position read command frame, count the number of slave stations on the linear topology; assign addresses to each slave station; select the first slave station clock as the reference number clock, calculate and compensate the line transmission delay; The clock of the first slave station is selected as the reference clock, and the compensation clock offset is calculated; the synchronization data packet is sent multiple times, and the frequency drift compensation in the initialization stage is performed.

The data communication phase mainly includes data communication packets and synchronization packets, and synchronization packets should be sent regularly during the communication process of data communication packets. Its operation process is shown in Figure 6.

In order to better describe the method described in the embodiment of the present invention, the specific embodiment of the present invention will be described in detail in conjunction with a specific data frame processing example:

Embodiment 1: A high-speed real-time bus communication method provided by a specific embodiment of the present invention. The technical scenario of this embodiment is a master station board, a slave station board, plus a common Ethernet physical interface and a network cable. Let's take the normal data communication cycle as an example, the system has 5 slave stations.

The main operations of the master station are:

Since this data packet is a data communication packet, the command is an FPRW read and write command, the cmd field is 0x6, the location addressing address of each slave station is 1, 2, 3, 4, 5 in turn, and the physical address offset is 0, which is taken as the application The data to be transmitted by the layer to each slave station is written into the corresponding data segment of each slave station, and the length of each slave station's data segment and the total length of each slave station's data field are filled into the corresponding fields, etc., that is, according to the long frame structure in the protocol Pack it, and then write the packed data packet into the FPGA data sending register of the master station.

Write the length of the entire long frame into the send length register.

After completing the above operations, write ffff into the sending command register, and the data frame will be sent out by the network card of the master station. According to the RMII protocol, two bits are sent every clock cycle.

When there is data to return, the master station FPGA will generate an interrupt, the master station program will respond to the interrupt, and set a semaphore in the interrupt processing function, after the semaphore is set, it will jump to the process of receiving data frames, and analyze the received data package to extract useful data.

into the next cycle.

The slave station data receiving and forwarding process is mainly realized by FPGA. The block diagram of the slave station data processing module is shown in Figure 7. In the process of receiving data frames from the slave station, many state machines are required, and different data segments are correspondingly processed under different state machines. Operation, the main state machine operation of the slave station is divided into several major steps as follows:

Step 1: Idle state, when the signal from the RMII protocol, i_Rx_DV is 0, the system will always work in the Idle state. In state machines such as R_PRE and R_HEADER, after the data is judged and checked by CRC, it is directly forwarded. If the type field is not judged to be a CASNET packet or a CRC check error, it will return to the Idle or R_PRE state, and discard the data packet directly.

Step 2: When the system enters the R_CMD, R_ADDR, R_OFF, R_LEN and other state machines, it stores the data received in this state into the corresponding registers.

Step 3: When the system enters the NOP state machine, it judges whether the CMD is within the range of matching commands. In this example, the value of CMD is 6, which is a read and write command.

Step 4: When the system enters the R_DATA state machine, it stores the received data into the register. The length len of the data field of the station received when the receiving length is in the R_LEN state. At the same time, since the transmission process is receiving, parsing, and forwarding, the commands in this data segment are read and write. During this process, the FPGA will fill in the value stored in the read register by the CPU in advance to the site. data segment and forward it out.

Step 5: When the CRC check passes, the entire frame forwarding is completed, and the FPGA triggers an interrupt to tell the CPU that there is data received at this time, and the data stored in step 4 can be read.

The above transmission process simplifies the relevant steps. The data frame forwarded by the slave station is still the physical transmission medium of ordinary Ethernet, using the RMII protocol, and transmitting two bits per clock cycle. The clock frequency provided by FPGA is the clock adjusted by drift compensation, and the stable output is 40M. Since it is forwarded after receiving, every two bits are only 25ns between two slave stations except for the physical line delay. The transmission cycle of the whole long frame is within 1ms.

Refer to FIG. 7 for the hardware structure of the present invention. In the technical implementation of the present invention, the Ethernet data packet is received without decoding it, and then the process data is copied to each device. The system adopts a master-slave structure. The physical layer adopts standard 100Base-TX or 100Base-FX and standard Ethernet card. The master station is mainly implemented by software, and the slave station is controlled by a dedicated chip. The master station controls the transmission cycle of the system, and the master station sends downlink data frames, and a data frame can contain several sub-messages. The data frame traverses all the slave devices, each slave device addresses the message of the machine when the data frame passes, reads the data or writes the data to the specified position in the message according to the command in the message, and from The station hardware adds 1 to the work counter of the message, indicating that the data sub-message is processed. The whole process will produce a delay of about 25NS. After the data frame visits the last slave station located in the physical location of the entire system, the slave station sends the processed data frame directly to the master station as an uplink data frame. After receiving the uplink data frame, the master station processes the returned data, and a communication ends. The forwarding process is implemented in hardware in the slave controller, so it has nothing to do with the protocol commissioning system or processor performance.

The main equipment includes master and slave hardware boards.

The main station device includes the main hardware modules are:

The sending unit sends out the data packets in the sending register.

The receiving unit responds to the interrupt when the data frame is transmitted back, and receives the data packet.

The interrupt unit interrupts the response when the data frame is transmitted back.

The only modules included in the slave device are:

The receiving module is used for determining the type of the data frame, addressing and data processing, etc.

The sending module is used to forward the processed data frame to the next slave station.

The interrupt module responds to the interrupt when the data frame arrives, and completes the reading and writing of the data segment of the station.

The synchronization module unit is used to complete a series of operations of system clock synchronization.

In addition, there are units such as FIFO and μC interface.

It can be seen from the technical solutions provided above that the present invention mainly improves the data transmission rate in the field control field by modifying and designing the common Ethernet and making full use of the transmission speed of the Ethernet. Using the total frame transmission method, through the control program in the FPGA, the data transmission without competition mechanism is achieved, ensuring that the data reaches the target device in real time, and providing better real-time performance of data transmission. In addition, the present invention adopts a synchronous method combining hardware and software, which provides a precise synchronous clock for the system.

Those skilled in the art can understand that the accompanying drawing is only a schematic diagram of a preferred embodiment.

Those of ordinary skill in the art can understand that all or part of the steps in the methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, One or a combination of steps of the method embodiments are included.

To sum up, with the technical solution provided by the specific embodiments of the present invention, the data can quickly reach the target device, so as to provide the advantage of better real-time data transmission.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone familiar with the technical field can easily think of Changes or substitutions should fall within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (9)

1. the communication means of a high-speed real-time industrial Ethernet adopts and makes agreement, clock synchronizing method, total frame transmission manner accurately by oneself, and the data of each slave station are inserted respective field in the frame, and its communication means comprises:

When Frame arrived, slave station at first carried out addressing, promptly found the data segment of our station in total frame;

After inquiring the our station data segment, slave station is carried out operations such as corresponding reading and writing according to the order in the our station data segment;

From stand in data handling procedure, be that edge joint is received, resolve on the limit, and transmit on the limit, each timeticks transmission 2bit.

2. the communication means of a kind of high-speed real-time industrial Ethernet according to claim 1, the frame structure of communication protocol can satisfy the transmission requirement of oneself, the implementation method that can transmit by common Ethernet chip is again, reaches by revising common ethernet frame structure; Ethernet type field in this protocol frame structure in the common ethernet frame structure remains unchanged, destination address and source address are made as reserved word, with length, control, data field as required, carries out self-defined; Concrete field mainly comprises: reserved word, ethernet type, CASNET head, sub-message, CRC redundancy check.

3. the communication means of a kind of high-speed real-time industrial Ethernet according to claim 1, respectively when standing in Frame and arrive, at first whether the judgment data frame is that native system is wanted data packets for transmission, and being judged as is that needed packet just receives and do subsequent treatment, otherwise abandons; This process just need be except will judging the ethernet type, marks up at the fixed bit of protocol frame structure head, and ethernet type and this indicate the common decision packet whether this agreement is supported thus.

4. the communication means of a kind of high-speed real-time industrial Ethernet according to claim 1 respectively from stand in the access data process, at first needs local address, operational order, internal register offset address, will carry out the parameters such as length of data processing;

Addressing is found the data segment of slave station separately by matching addresses in frame;

Get the corresponding address offset amount of command word, data bit length, command process of our station data segment, do corresponding processing at our station by these main fields.

5. the communication means of a kind of high-speed real-time industrial Ethernet according to claim 1, for reaching this feature of real-time, main website adopts real time operating system, and transfer of data is moved under real-time task, realizes real-time transfer of data.

6. the communication means of a kind of high-speed real-time industrial Ethernet according to claim 1 when main website and each slave station adopt the different clocks source, needs the complete clock synchronization mechanism of a cover, to satisfy the clock synchronization requirement of system, its committed step:

Line delay compensation, main website reads with twice timestamp through slave station of Frame in one-period, calculated transmission delay, and send to each slave station and carry out delay compensation.

The Clock enable deviation compensation, system initialisation phase, the clock skew of each slave station and benchmark slave station is calculated by main website, and issues each slave station and carry out migration.

Drift compensation, addened register, accumulator, the counter by FPGA inside make each station output clock counter be stabilized in same frequency.This method is by the transmission synchronization packets, adjusts the value of addened register, and each accumulator value is overflowed hour counter and added 1, and the value of counter is the value of local clock.

7. the communication means of a kind of high-speed real-time industrial Ethernet according to claim 6, described drift compensation regularly carries out in data communication process, drift-compensated sync packet is carried out in main website timed sending in transmission of data packets, this packet is by reading the output clock value of benchmark slave station, this value is write to other each slave station, adjusted the value of the addened register in the claim 6 by FPGA according to this numerical value.

8. the communicator of a high-speed real-time industrial Ethernet, it is characterized in that hardware is selected common Ethernet phy chip for use, interface is selected common Ethernet interface RJ45 for use, physical layer transmission is the RMII agreement, and data link layer realizes by the verilog programming in FPGA; Module comprises among the FPGA:

Be used for the type judgement to Frame, the receiver module of data parsing;

Be used for the data processed frame is forwarded to the sending module of next slave station;

Generation is interrupted when being used for the Frame arrival, reception FIFO produces at full capacity living interruption, transmission FIFO

Produce at full capacity and give birth to the interruption controls module of interrupting;

Be used to finish the synchronization module unit of the synchronous sequence of operations of system clock;

Also have unit such as FIFO and μ C interface in addition.

9. the communicator of a kind of high-speed real-time industrial Ethernet according to claim 8, it is characterized in that, by change to the application layer interface, can be applied to one of different high speed data transfer field and overlap independently bus system, the master and slave station of this system all is the integrated circuit board with common network card chip and FPGA.

Images