CN113330524B - Device with coil structure and circuit structure - Google Patents

Abstract

An apparatus comprising a substrate and a plurality of coil portions disposed on the substrate. The plurality of coil portions are electrically coupled to form a coil structure.

Description

Device with coil structure and circuit structure

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Patent Application No. 16/693,125, filed on November 22, 2019, and further claims the benefit of U.S. Provisional Application No. 62/774,027, filed on November 30, 2018, the entire contents of each of which are hereby incorporated by reference.

Technical Field

The present invention generally relates to coil structures and processes for making the same.

Background technique

Electroplating processes for fabricating structures such as copper or copper alloy circuit structures such as leads, traces and via interconnects are generally known and disclosed, for example, in US Pat. No. 4,315,985 to Castellani et al., entitled "Fine-Line Circuit Fabrication and Photoresist Application Therefor." These types of processes are used, for example, in conjunction with the manufacture of disk drive head suspensions as disclosed in U.S. Patent 8,885,299, entitled “Low Resistance Ground Joints for Dual Stage Actuation Disk Drive Suspensions,” by Bennin et al.; U.S. Patent 8,169,746, entitled “Integrated Lead Suspension with Multiple Trace Configurations,” by Rice et al.; U.S. Patent 8,144,430, entitled “Multi-Layer Ground Plane Structures for Integrated Lead Suspensions,” by Hentges et al.; U.S. Patent 7,929,252, entitled “Multi-Layer Ground Plane Structures for Integrated Lead Suspensions,” by Hentges et al.; U.S. Patent 7,388,733, entitled “Method for Making Noble Metal Conductive Leads for Suspension Assemblies,” by Swanson et al.; and U.S. Patent 7,388,733, entitled “Plated Ground Features for Integrated Lead Suspensions,” by Peltoma et al. These types of processes are also used in conjunction with the manufacture of camera lens suspensions, such as disclosed in Miller's U.S. Patent 9,366,879, entitled "Camera Lens Suspension with Polymer Bearings."

Superfilling and superconformal plating processes and compositions are also known and disclosed in, for example, the following articles: "The chemistry of additives in damascene copper plating" by Vereecken et al., IBM J. of Res. & Dev., vol. 49, no. 1, January 2005; "Damascene copper electroplating for chip interconnections" by Andricacos et al., IBM J. of Res. & Dev., vol. 42, no. 5, September 1998; and "Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing" by Moffat et al., Electrochimica Acta 53, pp. 145-154, 2007. With these processes, in-groove electroplating (e.g., a photoresist mask trench defines space for the structure to be plated) occurs preferentially at the bottom. Voids in the deposited structure can thereby be avoided. All of the above patents and articles are incorporated herein by reference in their entirety and for all purposes.

There remains a continuing need for enhanced circuit structures. There is also a need for efficient and effective processes, including electroplating processes, for fabricating circuits and other structures.

Summary of the invention

Apparatus including high aspect ratio electroplated structures and methods of forming high aspect ratio electroplated structures are described. A method of making a metal structure comprises: providing a substrate having a metal base, the metal base being characterized by a height to width aspect ratio; and electroplating a metal crown on the base to form the metal structure, the metal structure having a height to width aspect ratio greater than the aspect ratio of the base.

Other features and advantages of embodiments of the present invention will be apparent from the accompanying drawings and the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

By way of example and not limitation, embodiments of the invention are illustrated in the figures of the accompanying drawings in which like reference numerals indicate similar elements and in which:

FIG1 illustrates a coil manufactured using current printed circuit technology;

FIG2 illustrates a high-density precision coil including a high-aspect ratio electroplating structure according to an embodiment;

FIG. 3 illustrates a diagram for representing electromagnetic forces generated by a high-density precision coil including a high-aspect ratio electroplating structure according to an embodiment;

FIG4 illustrates a device configured for linear motor type applications including multiple layers of high aspect ratio plated structures according to an embodiment;

FIG5 illustrates a high aspect ratio electroplated structure according to some embodiments;

FIG. 6 illustrates a high aspect ratio electroplated structure according to some embodiments;

FIG. 7 illustrates a high aspect ratio electroplated structure according to some embodiments;

FIG8 illustrates a device having multiple layers of high aspect ratio plated structures having a high density cross-sectional area according to some embodiments;

9 illustrates a graph indicating SPS coverage during a high current density plating technique and a low current density plating technique according to an embodiment;

10a-f illustrate a process for forming a high aspect ratio electroplated structure according to an embodiment;

FIG. 11 illustrates a high aspect ratio electroplated structure according to some embodiments;

FIG. 12 illustrates a perspective view of a high aspect ratio electroplated structure according to some embodiments;

13a and 13b illustrate a high-density precision coil formed using a high-aspect ratio electroplating structure according to an embodiment;

FIG. 14 illustrates a high aspect ratio electroplated structure including high resolution stacked conductor layers according to an embodiment;

FIG. 15 illustrates a high-density precision coil including a high-aspect ratio electroplating structure according to an embodiment;

16a-c illustrate a process for forming a high aspect ratio electroplated structure according to another embodiment;

FIG. 17 illustrates the selective formation of high aspect ratio electroplated structures according to an embodiment;

FIG. 18 illustrates a perspective view of a high aspect ratio electroplated structure according to an embodiment having a metal crown portion selectively formed on a trace;

FIG. 19 illustrates a hard drive platter suspension flexure including a high aspect ratio plated structure according to an embodiment;

FIG20 illustrates a cross-sectional view of a flexure of the hard disk drive suspension shown in FIG19;

21a, 21b illustrate a process for forming a high aspect ratio electroplated structure according to an embodiment using a photoresist during a conformal plating process;

22 illustrates exemplary chemistries for a process for forming an initial metal layer, a standard/conformal plating process, and a crown plating process according to various embodiments;

23 illustrates a perspective view of a top surface of an inductively coupled coil formed by a high aspect ratio electroplated structure according to an embodiment;

FIG24 illustrates a perspective view of the rear surface of the embodiment of the inductively coupled coil shown in FIG21;

FIG. 25 illustrates a perspective view of a top surface of an inductive coupling coil 2502 according to an embodiment coupled to an RFID chip;

26a-j illustrate a method of forming an inductively coupled coil formed from a high aspect ratio electroplated structure according to an embodiment;

27 illustrates a plan view of a flexure of a suspension for a hard disk drive including a high aspect ratio plating structure according to an embodiment;

FIG28 illustrates a cross section of the gap portion of the bend at the gap portion taken along line A as shown in FIG27;

FIG29 illustrates a gimbal portion with a mass structure according to an embodiment;

30 illustrates a cross-section of a proximal portion of a bend including a high aspect ratio plated structure according to an embodiment taken along line B as shown in FIG. 27 ;

31 illustrates a cross-section of a proximal portion of a curved portion including a high aspect ratio structure according to an embodiment, taken along line C as shown in FIG. 27 ; and

32 illustrates a plan view of a proximal portion of a bend including a high aspect ratio structure according to an embodiment;

FIG. 33 illustrates a process for forming a high aspect ratio electroplated structure according to an embodiment;

FIG. 34 illustrates a more detailed process similar to the type described with respect to FIG. 33 ; and

FIG35 illustrates a coil according to an embodiment manufactured using the process described herein;

Fig. 36 illustrates a cross section of the coil shown in Fig. 37;

FIG37 illustrates a C-shaped coil configuration including multiple coil segments according to an embodiment;

FIG38 illustrates a C-shaped coil configuration according to an embodiment;

FIG39 illustrates a formable/Z-plane forming coil structure according to an embodiment;

FIG40 illustrates a C-shaped coil structure including a bridge according to an embodiment;

FIG41 illustrates a cross section of a bridge member in a C-shaped coil structure according to the embodiment shown in FIG40 ;

42-44 illustrate embodiments of C-shaped coil structures including bridges according to embodiments;

FIG45 illustrates a C-shaped coil structure including a bridge according to an embodiment;

FIG46 illustrates a cross section of a bridge member in a C-shaped coil structure according to the embodiment shown in FIG45;

FIG47 illustrates a coil structure according to an embodiment formed from a plurality of separate parts;

FIG48 illustrates a coil structure according to an embodiment including a plurality of separate parts;

FIG49 illustrates an alternative shape of at least a portion of a coil structure according to an embodiment;

FIG50 illustrates a surface mounted coil used to form a coil structure according to an embodiment;

FIG51 illustrates a surface mount coil configured to be placed on a substrate according to an embodiment;

FIG52 illustrates a top view of a substrate with an attached surface mount coil according to an embodiment;

FIG53 illustrates a surface mount coil including integrated trace jumpers according to an embodiment;

FIG54 illustrates a surface mount coil portion according to an embodiment;

FIG55 illustrates a circuit board configured for mounting coil portions to form a coil structure according to an embodiment;

FIG56 illustrates multiple views of a coil structure according to an embodiment;

FIG57 illustrates multiple views of a coil structure including a surface mounted coil according to an embodiment;

FIG58 illustrates a coil portion according to an embodiment;

FIG59 illustrates a coil structure according to an embodiment including solder joints for attaching one or more surface mount coils;

FIG60 illustrates a top view of a structure including solder joints for mechanically and electrically coupling a surface mount circuit to the structure according to an embodiment;

FIG61 illustrates a bottom view of a structure including solder joints for mechanically and electrically coupling a surface mount circuit to the structure of FIG60;

FIG. 62 illustrates a structure including solder joints according to an embodiment;

FIG. 63 illustrates a solder joint according to an embodiment;

FIG64 illustrates a cross-sectional view of a solder joint according to an embodiment;

FIG. 65 illustrates a flow chart of a manufacturing process using solder joints according to an embodiment;

FIG. 66 illustrates a coil structure according to an embodiment; and

FIG. 67 illustrates a coil structure according to an embodiment.

Detailed ways

The following describes a high aspect ratio electroplating structure and a manufacturing method according to an embodiment of the present invention. The high aspect ratio electroplating structure provides a conductor spacing that is tighter than the current technology. For example, according to various embodiments, the high aspect ratio electroplating structure includes a conductor stack, wherein the cross-sectional area of the conductor stack is greater than 50%. In addition, the high aspect ratio electroplating structure makes it possible to realize a multilayer conductor according to an embodiment. In addition, according to various embodiments, the high aspect ratio electroplating structure makes it possible to realize precise alignment (alignment) between layers. For example, the high aspect ratio electroplating structure can have an alignment of less than 0.030mm between layers. According to various embodiments, the high aspect ratio electroplating structure makes it possible to reduce the total stack height.

According to various embodiments, high aspect ratio plating structures enable thin dielectric materials to be implemented between magnets and coils formed using high aspect ratio plating structures. This enables the coils to generate stronger electromagnetic fields than current printed circuit coils (such as those shown in FIG. 1 ). Therefore, high aspect ratio plating structures are more cost-effective, produce higher performance devices, and reduce the required footprint of the device compared to current technology.

2 illustrates a high density precision coil including high aspect ratio plated structures according to an embodiment. The high aspect ratio plated structures 202 are formed in rows with dielectric material between each row and each high aspect ratio plated structure 204. The high density precision coil can be formed as a spiral coil or other coil type.

FIG3 illustrates a diagram for representing the electromagnetic forces generated by a high density precision coil including a high aspect ratio electroplated structure according to an embodiment. The diagram includes a coil cross section 302 near a magnet 304. The highest electromagnetic force 306 is in the coil layer 308 closer to the magnet 304. The coil layer 310 farther from the magnet 304 exerts a smaller force. The main factor affecting the force comes from the Lorentz equation: because The magnitude of the magnitude decreases with the distance between the coil and the magnet, so is the current flowing through the copper. Any cross-sectional area of the cross section 302 that is not a conductor has a significant effect on the force No contribution.

The main factors that affect the force capability of the coil include the number of turns within the magnetic field (the turns closest to the poles of the magnet provide the greatest force), the distance of the coil from the magnet (layers closer to the magnet will exert greater force), and the total percentage of the copper cross-sectional area within the magnetic field. The use of high aspect ratio plated structures in accordance with various embodiments improves these aspects compared to coils using current coil technology.

For example, a coil having two layers using current technology has a total thickness of approximately 210 microns, a conductor spacing of 38 microns, a cross-sectional percentage of copper of approximately 20%, an estimated resistance of 3.1 ohms, an estimated force ratio of 1.0 (an estimated B ratio of 1.0 and an estimated J ratio of 1.0), and an estimated power ratio of 1.0. In contrast, according to various embodiments, a high-density precision coil including a high-aspect ratio electroplated structure has a total thickness of approximately 116 microns, a conductor spacing of 40 microns, a cross-sectional percentage of copper of approximately 60%, an estimated resistance of 5.5 ohms, an estimated force ratio of 1.2 (an estimated B ratio of 1.5 and an estimated J ratio of 0.8), and an estimated power ratio of 0.71. Therefore, according to various embodiments, a high-density precision coil including a high-aspect ratio electroplated structure is a higher performance device. Therefore, according to some embodiments, such a high-density precision coil provides 20% greater force and 30% less power at half the thickness of a coil using the current state of the art.

FIG4 illustrates a device including multiple layers of a high aspect ratio electroplated structure according to an embodiment configured for a linear motor type application. Due to the size advantage compared to the current technology, each layer 402a-d of the high aspect ratio electroplated structure is more likely to be closer to the magnet 404 than the current technology (such as shown in FIG1). In addition, each layer 402a-d is closer to the magnet 404 by utilizing volume The force capability of a linear motor is improved by increasing the magnetic field (flux density). Therefore, using a multi-layer high aspect ratio electroplated structure for a linear motor will require fewer layers than structures using current technology. In addition, such a structure provides greater flexibility in obtaining electrical properties such as low resistance.

FIG5 illustrates a high aspect ratio electroplated structure at a stage during a manufacturing process according to some embodiments. The layer 602 of the high aspect ratio electroplated structure at this stage during the manufacturing process is formed using a semi-additive technique to create a fine pitch, resist-defined conductor having an initial height to width aspect ratio (A/B) of approximately 1 to 1. For example, the high aspect ratio electroplated structure may have a height of 20 microns and a width of 20 microns. According to some embodiments, the plating process is stopped at this time to remove the seed layer (seed layer) and a defined workpiece such as a photoresist mask using techniques including those known in the art.

FIG6 illustrates a high aspect ratio electroplated structure at another stage during the manufacturing process according to some embodiments. Layer 702 of the high aspect ratio electroplated structure at this stage during the manufacturing process is formed using crown plate technology to convert the semi-additive conductor into a high aspect ratio, high percentage metal conductor circuit. For example, the high aspect ratio electroplated structure has a final height to width ratio (A/S) greater than 1 to 1. According to various embodiments, the final height to width ratio may be in a range including 1.2 to 3.0. Other embodiments include a final height to width ratio greater than 3.0. However, those skilled in the art will appreciate that any final height to width ratio may be obtained using the techniques described herein to meet design and performance criteria. In the formation stage shown in FIG6 formed from the previous stage as shown in FIG5, there is no particular limitation on the final height of the high aspect ratio electroplated structure as disclosed in the various embodiments.

FIG7 illustrates a high aspect ratio electroplated structure at yet another stage during a manufacturing process according to some embodiments. The layers 802a, b of the high aspect ratio electroplated structure at this stage during the manufacturing process are converted using a planarization technique to allow stacking of multiple layers of the high aspect ratio electroplated structure using a semi-additive technique to form subsequent layers. FIG8 illustrates a device having multiple layers of high aspect ratio electroplated structures with a high fractional conductor cross-sectional area 901 according to some embodiments.

The method for forming a high aspect ratio electroplating structure from structures such as those shown in Figure 5 includes the use of a low current density plating technique. This plating technique plates the sidewalls until the desired space is obtained between the high aspect ratio electroplating structures. For various embodiments, if the space between the high aspect ratio electroplating structures is not narrow enough, undesirable extrusion at the top may occur. Extrusion occurs where the top edges of adjacent structures grow together and pinch off the gap, which causes a short circuit. For various embodiments, the low current density plating process is enhanced by enough fluid exchanges so that fresh plating baths can be continuously used for the surface where copper plating occurs. In addition, the method for forming a high aspect ratio electroplating structure includes the use of a high current density plating technique. This high current density plating technique operates under a high percentage of mass transfer limit. This is mainly or only plated on the top of the conductive material forming the high aspect ratio electroplating structure. The high current density plating process is enhanced by precise current density control. 9 illustrates a graph having an upper line 1002 indicating high SPS coverage during a high current density plating technique according to an embodiment and a lower line 1004 indicating low, very uniform catalyst (promoter) coverage during a low current density plating technique according to an embodiment.

Figures 10a-f illustrate a process for forming a high aspect ratio electroplating structure according to an embodiment. Figure 10a illustrates a trace 1102 formed at the thickness limit of the resist capability (corrosion resistance) at time T1 of the process. For some embodiments, a process such as a damascene process is used, or etching and deposition techniques including those known in the art are used to form a pre-plated traditional trace by copper. Figure 10b illustrates the formation of a high aspect ratio electroplating structure at time T2 during a low current density or conformal plating process. According to an embodiment, the conformal plating process grows all surfaces of the trace at approximately the same rate. In addition, the conformal plating process suppresses plating dynamics (low catalyst coverage). The conformal plating process also provides a fairly uniform metal concentration, which has a high, uniform inhibitor coverage to compensate. The effect of suppressing plating dynamics can be enhanced by including a leveler in the plating bath. Obtaining uniform metal concentration and obtaining high, uniform inhibitor coverage requires a lower current density. According to some embodiments, a conformal plating process of 2 amperes per square decimeter is used for plating, such as copper, brightener additives, temperature and fluid mechanics of the plating device. Examples of such conformal plating processes include, but are not limited to, low current density plating processes. At low current density, the plating bath maintains a uniformly suppressed state to provide conformal plating. For another embodiment, a leveler can be added to the plating bath to provide a higher current density and faster plating. For another embodiment, the current density can be further increased by increasing the copper content to a solubility limit close to the copper sulfate in the plating bath. This provides the ability to double or even increase the current density to achieve the same conformal plating quality. For example, the copper content can be as high as 40 grams per liter, with a reduced acid content to prevent common ion effects.

For some embodiments, the low current density plating process deposits a conductive material (such as copper) onto the top and sidewalls of the trace 1102, for example, T2 is approximately five minutes into the process (T1+5 minutes) during the low current density plating process. FIG. 10c illustrates the formation of a high aspect ratio electroplated structure at time T3 into the process during the low current density plating process. For embodiments, the low current density plating process deposits a conductive material (such as copper) onto the top and sidewalls of the trace 1102, for example, T3 is approximately five minutes into the process (T1+15 minutes) during the low current density plating process.

FIG. 10d illustrates the formation of a high aspect ratio electroplated structure at time T4 into the process during a crown plating process, such as a high current anisotropic super plating process. For example, T4 is approximately 15 minutes and 10 seconds into the process (T1 + 15 minutes and 10 seconds). For some embodiments, the high current anisotropic super plating process is crown plating. Crown plating is based on balancing the interaction between the following factors: metal concentration in solution; brightener additives; suppressor additives; mass transfer-fluid exchange rate to the surface; levelers; and current density at the substrate. The metal concentration in solution may include, but is not limited to, copper. Brightener additives may include, but are not limited to, SPS (bis(3-sulfopropyl)-disulfide), DPS (3-N,N-dimethylaminodithiocarbamoyl-1-propanesulfonic acid), and MPS (mercaptopropylsulfonic acid). Inhibitor additives may include, but are not limited to, linear PEGs of various molecular weights (including those known to those skilled in the art), poloxamines, co-block polymers of polyethylene and polypropylene glycol, such as water-soluble poloxamers known under various commercial names, such as BASF pluronic f127, and polypropylene glycol (PEG) ... The UCON series of high performance fluids are random copolymers (again in various proportions of monomers and various molecular weights) and polyvinyl pyrrolidone of various molecular weights.

According to some embodiments, the high current anisotropic super plating process includes a suppressed exchange current of 1% of the accelerating current. In addition, the sidewall of the high aspect ratio electroplating structure formed has almost zero catalyst coverage. Almost zero catalyst coverage is achieved by shifting the Nernst potential for copper deposition to help inhibitor coverage. In addition, high overpotential and copper availability (transmission phenomenon) lead to high catalyst coverage at the top of the structure formed. Copper mixed concentrates can also be adjusted to support almost zero catalyst coverage during this process. For example, the copper mixed concentrate for the high current anisotropic super plating process is 14 grams per liter or lower. For some embodiments, the copper mixed concentrate depends on specific fluid mechanics. Because the various embodiments of the process operate at a high fraction of the mass transfer limit, the small difference in the fluid velocity across the object to be plated will affect the mass transfer limit, and it is difficult to achieve sufficient control of the gap between the plating lines without a high degree of control of the fluid velocity across all regions of the object to be plated. According to some embodiments, the high current anisotropic super plating process includes a leveler additive to disable the catalyst coverage, thereby minimizing or eliminating plating on the sidewalls of the structure being formed. For other embodiments, the plating bath is used without the leveler additive.

According to some embodiments, at elevated current densities (such as those used in high current anisotropic super plating processes), a triple feedback mechanism works. The mass transfer effect depletes the copper in the space between the traces. In addition, the high current density supports a surface dominated by a catalyst (e.g., SPS). In order to maintain the suppressed sidewalls, mass transfer is regulated by the copper mass transfer effect to reduce the Nernst potential. For example, the fluid boundary layer thickness and the spacing between each trace are designed to reduce the Nernst potential.

In addition, according to some embodiments, the high current anisotropic super plating process includes operating with a certain copper concentration, at which these differences can create concentration differences greater than four times. Under such conditions, lower copper concentration and Nernst potential contribute to reducing the plating rate. For example, when the Nernst potential is approximately shifted in the range of 50 millivolts ("mV") to 60mV, this may contribute to 20 times of reduction in the plating rate. Such conditions induce Tafel dynamics, and for copper plating, it is a change of ten times of electric current for every 120mV of applied voltage (not rectifier voltage). Lower sidewall current is fed back to the top surface of the structure being formed, and wherein the diffusion length is short, which promotes the faster transport of metal from the plating bath (solution) to the surface and higher catalyst coverage rather than inhibition, and high Nernst potential. For some embodiments, two additive systems (for example, brightener and inhibitor) are used. Leveler reduces feedback mechanism by blocking the SPS action on the top side of the plating feature.

As the spacing between metal conductors or traces continues to shrink, the aspect ratio of the height to width of the space between metal conductors increases substantially. According to some embodiments, the methods of electroplating processes provided herein achieve plating in the spaces between metal conductors at aspect ratios of 7:1 and greater.

According to some embodiments, a method of forming a high aspect ratio electroplated structure provides selective formation of metal crown plating at selective locations or regions. In one exemplary embodiment, the selective formation of the metal crown is achieved by performing the electroplating process according to the following relationship:

Where C is the concentration of the metal being plated (copper in this case) and C∞ is the volume concentration in the plating bath. This relationship can also be expressed as performing a plating process where Equal to or greater than sixty-seven percent (67%) of the mass transfer limit. According to other embodiments, the selective formation of the metal crown is achieved by performing an electroplating process according to the following relationship:

or in In another aspect, the selective formation of the metal crown is achieved by performing the electroplating process according to the following relationship:

Here i is the current density and i _limit is the current density limit.

Figure 10e illustrates the formation of a high aspect ratio electroplating structure at time T5 during a high current anisotropic super plating process. For example, T5 is approximately 15 minutes and 30 seconds into the process (T1+15 minutes and 30 seconds). For another embodiment, the formation of a high aspect ratio electroplating structure as shown in Figure 10e occurs at time T5=T1+5 minutes. Figure 10f illustrates the formation of a high aspect ratio electroplating structure at time T6 during a high current anisotropic super plating process. This figure shows the end of the crown plating process, which ends the formation of a high aspect ratio electroplating structure according to some embodiments. For example, T6 is approximately 20 minutes into the process (T1+20 minutes). For another embodiment, the formation of a high aspect ratio electroplating structure as shown in Figure 10f occurs at time T6=T1+10 minutes.

For some embodiments, the method for forming a high aspect ratio electroplating structure uses a process including conformal plating and anisotropic plating described herein. According to some embodiments, the conformal plating process uses 2/3 of the total plating time. For other embodiments, the conformal plating process uses 1/3 of the total plating time. In addition, the conformal plating process starts with 2 amperes per square decimeter ("ASD") for low metal plating baths or starts with 4ASD for high metal plating baths. For example, the plating bath includes 12 grams per liter of copper and 1.85 moles (mol/l) of sulfuric acid. Alternatively, the conformal plating process is a process plated at a rate of 0.4 to 1.2 microns per minute. According to an embodiment, the conformal plating process continues until the space between the traces is within the range of 6-8 microns. As the surface area of the structure formed increases, the current density will slowly decrease. However, the process will achieve uniform current density and growth rate on all surfaces formed. For some embodiments, as the surface area of the formed high aspect ratio structures increases, the current may be increased to maintain the current density.

According to some embodiments, anisotropic plating process uses 1/3 of the total plating time to form a high aspect ratio electroplated structure. Anisotropic plating process increases ASD to 7ASD (3.5 times the current of conformal plating process), but on average, it is twice at the top of the formed metal structure. The same fluid flow rate as used in the conformal plating process can be maintained. For example, the plating rate is 3 microns/minute at the top of the formed structure, with a plating rate of almost zero on the sidewall of the structure. As the structure grows, the average current drops by half, but according to an embodiment, the peak current density maintains about 14ASD at the top of the structure. For example, the peak current density just exceeds 50% of the mass transfer limit at the top surface, and even if the sidewall is exposed to about 3 grams/liter of copper, the sidewall is plated at a plating rate of 10% or 5:1 less than the mass transfer limit. At a higher fraction of the mass transfer limit, a higher plating rate ratio can be obtained.

Embodiments of the method for forming a high aspect ratio electroplating structure include variations of those described above to form a high aspect ratio electroplating structure including different characteristics. For example, as described above, the copper content in the plating bath configured as an anisotropic plating bath may be different from 13.5 g/L. Changing the copper content in the flat trace plating bath while using the same current density can be used to control the spacing between the high aspect ratio electroplating structures. Another embodiment of the method described herein includes using a flat trace plating bath having a copper content of 12 g/L to form a high aspect ratio electroplating structure spaced apart by 8 microns. Yet another embodiment of the method described herein includes using a flat trace plating bath having a flat trace plating bath having a copper content of 15 g/L to form a high aspect ratio electroplating structure spaced apart by 4 microns. Therefore, those skilled in the art will appreciate that adjusting other parameters of the method described herein can be used to change the characteristics of the high aspect ratio electroplating structure. Some embodiments of the method described herein include adjusting the current density to match the current plating conditions, such as mass transfer rate, metal contained in the plating bath, fluid velocity, copper concentration, additives used, and temperature.

The method for forming high aspect ratio electroplated structures also includes using a thin dielectric process. According to some embodiments, photosensitive polyimide is used as a dielectric between each high aspect ratio electroplated structure. Liquid photosensitive polyimide enables small via capabilities, good coverage between high aspect ratio conductors, good alignment/edge capabilities, is a high reliability material, and has a coefficient of thermal expansion ("CTE") that closely matches copper. Liquid photosensitive polyimide can easily fill gaps between high aspect ratio electroplated structures. According to some embodiments, liquid photosensitive polyimide is used to create via paths as low as 0.030 mm. Other dielectrics that can be used include, but are not limited to, KMPR and SU-8.

FIG. 11 illustrates a high aspect ratio plated structure formed using methods described herein, according to some embodiments. Each high aspect ratio plated structure 1202 includes a plurality of texture lines 1204, which illustrate how the electroplating process is performed to form the structure. A thin dielectric 1206 is formed between and disposed on the high aspect ratio plated structures 1202. FIG. 12 illustrates a perspective view of a high aspect ratio plated structure 1302 formed using methods described herein, according to some embodiments.

The method described herein can be used to form a high aspect ratio electroplating structure that forms a high-density precision coil. Figure 13a illustrates a high-density precision coil formed using a high aspect ratio electroplating structure according to an embodiment. Coil 1402 is formed by a high aspect ratio electroplating structure such as those described herein. The high-density precision coil also includes a center coil via 1404. The center coil via 1404 reduces the voltage drop across the coil during the manufacturing steps described herein. In addition, the center coil via 1404 enables the following ability to be achieved, that is, the variability of the spacing within the coil is better controlled by better controlling the voltage drop and current during the anisotropic plating process described herein. The center coil via 1404 also enables better control of the voltage drop of the formed high-density precision coil. Figure 13b illustrates a cross-section of the center coil via 1404 as a part of the high-density precision coil as described herein.

FIG. 14 illustrates a high aspect ratio plated structure including a high resolution stacked conductor layer according to an embodiment. A first conductor layer 1502a includes a high aspect ratio plated structure 1504 formed using techniques including those described herein. A first dielectric layer 1508 is formed using a thin dielectric process using techniques including those described herein. The first dielectric layer 1508 fills all spaces between the high aspect ratio plated structures of the first conductor layer 1502a and forms a coating over the high aspect ratio plated structures 1504. The first dielectric layer 1508 is planarized using techniques known in the art. A second conductor layer 1502b includes a high aspect ratio plated structure 1506 formed over the planarized surface of the first dielectric layer 1508. A second dielectric layer 1510 is formed using a thin dielectric process using techniques including those described herein to fill all spaces between the high aspect ratio plated structures 1506 of the second conductor layer 1502b and form a coating over the high aspect ratio plated structures 1506. The second dielectric layer 1510 may also be planarized. Additional layers including high aspect ratio plated structures may be formed using the techniques described herein.

FIG. 15 illustrates a high-density precision coil including a high aspect ratio plating structure according to an embodiment, which includes a high-resolution stacked conductor layer. The first conductor layer 1602a includes a high aspect ratio plating structure formed using techniques including those described herein. The first dielectric layer 1608 is formed using a thin dielectric process using techniques including those described herein. The first dielectric layer 1608 fills all spaces between the high aspect ratio plating structures of the first conductor layer 1602a and forms a coating on the high aspect ratio plating structures. The first dielectric layer 1608 is planarized using techniques known in the art. The second conductor layer 1602b includes a high aspect ratio plating structure formed on the planarized surface of the first dielectric layer 1608. The second dielectric layer 1610 is formed using a thin dielectric process using techniques including those described herein to fill all spaces between the high aspect ratio plating structures of the second conductor layer 1602b and form a coating on the high aspect ratio plating structures. The second dielectric layer 1610 may also be planarized. Additional layers including high aspect ratio plated structures may be formed using the techniques described herein.

The high density precision coil is formed to have a first distance 1614 between the high aspect ratio plated structures of the first conductor layer 1602a and the high aspect ratio plated structures of the second conductor layer 1602b. For various embodiments, the first distance 1614 is less than 0.020 mm. For another embodiment, the first distance 1614 is 0.010 mm. The high density precision coil is formed to have a second distance 1616 between the surface 1618 of the second dielectric layer 1610 and the high aspect ratio plated structures of the first conductor layer 1602a. For various embodiments, the second distance 1616 is less than 0.010 mm. For some embodiments, the second distance 1616 is 0.005 mm. For some embodiments, the second distance 1616 can be the starting gap minus the final desired gap divided by 2. The high density precision coil is formed to have a third distance 1620 between the high aspect ratio plated structures of the first conductor layer 1602a and the surface of the first dielectric layer 1622. For various embodiments, the third distance 1620 is less than 0.020 mm. For some embodiments, the third distance 1620 is less than 0.015 mm. For another embodiment, the third distance 1620 is 0.010 mm. For various embodiments, a first dielectric layer is formed on a substrate 1624 using techniques including those described herein. For some embodiments, the substrate 1624 is a stainless steel layer. Those skilled in the art will appreciate that the substrate 1624 can be formed of other materials, including but not limited to steel alloys, copper alloys such as bronze, pure copper, nickel alloys, beryllium copper alloys, and other metals, including those known in the art.

Other advantages of using high aspect ratio electroplating structures as described herein to form devices include devices with high structural strength, high reliability, and high heat dissipation capabilities. High structural strength is provided by the ability to form very dense concentrations of metal high aspect ratio electroplating structures on all layers of the device. In addition, the process for forming the metal high aspect ratio electroplating structure described herein provides lateral alignment of the structure between layers, thereby increasing the high structural strength. The high structural strength of the device formed using the process for forming the metal high aspect ratio electroplating structure described herein is also the result of the good adhesion of the dielectric layer material (such as a photosensitive polyimide layer) to the structure. For some embodiments, the high aspect ratio electroplating structure formed using the technology described herein is coated with a non-magnetic nickel layer to increase the adhesion of the dielectric layer. This will further increase the high structural strength of the final device formed using the high aspect ratio electroplating structure described herein.

The reliability of devices formed using the high aspect ratio electroplating structures described herein is also high because high reliability materials such as photosensitive polyimide for the dielectric layer are used, which provides robust electrical performance. Using the techniques described herein, the ability to form devices with less dielectric material is provided and the overall thickness of the formed device is reduced. Therefore, heat dissipation is increased by increased thermal conductivity compared to devices using current process technologies.

Figures 16a-c illustrate a process for forming a high aspect ratio electroplated structure according to another embodiment. Figure 16a illustrates a trace 1802 formed on a substrate 1804 using subtractive etching. According to some embodiments, a metal layer is formed over the substrate 1804. A photoresist layer is formed over the metal layer using techniques including those known in the art. For some embodiments, the photoresist layer is a photosensitive polyimide deposited over the metal layer in liquid form. The photoresist is patterned and developed using techniques including those known in the art. The metal layer is then etched using techniques including those known in the art. After the etching process, trace 1802 is formed.

FIG. 16b illustrates the formation of a high aspect ratio plated structure using a conformal plating process such as those described herein. FIG. 16c illustrates the formation of a high aspect ratio plated structure using a crown plating process such as those described herein. For various embodiments, the high aspect ratio plated structure is formed without using a conformal plating process such as the process described with reference to FIG. 16b. Instead, a crown plating process such as the process described with reference to FIG. 16c is used after forming the trace 1802 as shown in FIG. 16a.

FIG. 17 illustrates the selective formation of a high aspect ratio electroplated structure according to an embodiment. Once the traces 1902 are formed using techniques including those described herein, a photoresist layer 1904 is formed over portions of one or more of the formed traces 1902. The photoresist layer 1904 may be a photosensitive polyimide and is deposited and formed using techniques including those described herein. A metal crown 1906 is formed on the trace 1902 using one or both of a conformal plating process and a crown plating process as described herein. FIG. 18 illustrates a perspective view of a high aspect ratio electroplated structure according to an embodiment formed with a metal crown portion selectively formed on the trace. According to some embodiments, selectively forming a metal crown portion on a trace is used to improve the structural properties of a high aspect ratio electroplated structure, improve the electrical performance of a high aspect ratio electroplated structure, improve heat transfer characteristics, and meet custom size requirements of a device formed using a high aspect ratio electroplated structure. Examples of electrical performance improvements include, but are not limited to, capacitance, inductance, and resistance properties of a high aspect ratio electroplated structure. Additionally, selectively forming metal crown portions on traces may be used to tune the mechanical or electrical properties of circuits formed using high aspect ratio plated structures.

FIG. 19 illustrates a hard drive disk suspension flexure 2102 including a high aspect ratio electroplated structure according to an embodiment formed using selective forming as described herein. FIG. 20 illustrates a cross-sectional view of the hard drive suspension flexure shown in FIG. 19 taken along line A-A. The cross section of the flexure 2102 includes a high aspect ratio electroplated structure 2104 and a trace 2106. The high aspect ratio electroplated structure 2104 is formed using a selective forming technique as described herein. Forming the high aspect ratio electroplated structure 2104 to serve as a conductor in a predetermined area of the flexure can achieve a reduction in DC resistance. This allows fine lines and spaces to be formed where needed on the flexure while meeting the design requirements for DC resistance and improving the electrical performance of the flexure.

Figures 21a, b illustrate a process for forming a high aspect ratio electroplated structure according to an embodiment using a photoresist during a conformal plating process. Figure 21a illustrates a trace 2302 formed on a substrate 2304 using techniques including those described herein. Figure 21b illustrates the formation of a high aspect ratio electroplated structure using a plating process as described herein. A photoresist portion 2306 is formed over the substrate 2304 using deposition and patterning techniques including those described herein. Once the photoresist portion 2306 is formed, one or both of a conformal plating process and a crown plating process are performed to form a metal portion 2308 on the trace 2302. The photoresist portion 2306 can be used to better define the spacing between the high aspect ratio electroplated structures.

22 illustrates exemplary chemistries for a process for forming an initial metal layer, a standard/conformal plating process, and a crown plating process according to various embodiments.

23 illustrates a perspective view of a top surface 2501 of an inductively coupled coil 2502 with an integrated tuning capacitor formed by a high aspect ratio electroplating structure 2504 according to an embodiment. Using a high aspect ratio electroplating structure to form the inductively coupled coil reduces the footprint of the inductively coupled coil compared to an inductively coupled coil formed using current techniques to form the coil. This enables the inductively coupled coil 2502 to be used in applications where space is limited. In addition, using a capacitor integrated into the inductively coupled coil further reduces the footprint of the inductively coupled coil because no additional space requirements are required to accommodate discrete capacitors, such as surface mount technology (“SMT”) capacitors.

Figure 24 illustrates a perspective view of the back surface 2604 of the embodiment of the inductive coupling coil 2502 shown in Figure 23. Figure 25 illustrates a perspective view of the top surface of the inductive coupling coil 2502 coupled with a radio frequency identification ("RFID") chip 2704 according to an embodiment.

Figures 26a-j illustrate a method of forming an inductively coupled coil 2502 formed of a high aspect ratio electroplated structure 2504 according to an embodiment. According to various embodiments, the inductively coupled coil includes an integrated tuning capacitor. Figure 26a illustrates a substrate 2802 formed using techniques including those known in the art. For some embodiments, the substrate 2802 is formed of stainless steel. Other materials that can be used for the substrate include, but are not limited to, steel alloys, copper, copper alloys, aluminum, non-conductive materials that can be metallized using techniques including plasma vapor deposition, chemical vapor deposition, and electroless chemical deposition. A shadow mask 2804 is formed over the substrate 2802. According to some embodiments, the shadow mask 2804 is a high-K dielectric. Examples of high-K dielectrics that can be used include, but are not limited to, titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, SU-8, KMPR, and other high dielectric constant dielectric materials. According to some embodiments, the shadow mask 2804 is formed using a sputtering process using techniques including those known in the art. For some embodiments, the shadow mask 2804 is formed to have a thickness included in the range of 500 to 1000 angstroms. For other embodiments, the shadow mask 2804 is formed using screen printing of a high dielectric constant ink. Examples of high dielectric constant inks include inks that include an epoxy loaded with particles made of one or more of titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, and other high dielectric constant dielectric materials. For still other embodiments, the shadow mask 2804 is formed using a slot die application of a photoimageable dielectric doped with a high-K filler. Examples of high-K fillers include zirconium dioxide (ZrO2).

FIG. 26 b illustrates a metal capacitor plate 2806 formed on top of the shadow mask 2804. The metal capacitor plate 2806 and the substrate 2802 form two capacitor plates of the integrated capacitor. The thickness of the shadow mask 2804 can be used to set the effective capacitance of the integrated capacitor. In addition, the purity of the high-K dielectric used to form the shadow mask 2804 can be used to set the effective capacitance of the integrated capacitor. The surface area of the metal capacitor plate 2806 can also be used to set the effective capacitance of the integrated capacitor.

FIG. 26c illustrates a base dielectric layer 2808 formed over shadow mask 2804, metal capacitor plate 2806, and at least a portion of substrate 2802. According to some embodiments, base dielectric layer 2808 is formed by depositing dielectric material, patterning dielectric material, and curing dielectric material using techniques including those known in the art. Examples of dielectric materials that may be used include, but are not limited to, polyimide, SU-8, KMPR, and hard-baked photoresists (such as those made of The base dielectric layer 2808 may also be patterned or etched to form vias. For example, a jumper via 2812 and a shunt capacitor via 2810 are formed in the base dielectric layer 2808. The shunt capacitor via 2810 is formed to interconnect the integrated capacitor with the rest of the circuit to be formed. Similarly, the jumper via 2812 is used to interconnect the circuit element to be formed with the substrate 2802.

FIG. 26d illustrates a coil 2814 formed on a base dielectric layer 2808 using a high aspect ratio plating structure for forming a coil using techniques including those described herein. For some embodiments, the coil 2814 is a single layer coil. The coil 2814 includes a central connection portion 2816 connected to one of the shunt capacitor vias 2810 and one of the crossover vias 2812 that are in electrical contact with the metal capacitor plate 2806 of the integrated capacitor. The coil 2814 also includes a capacitor connection portion 2818 to connect the coil 2814 to another of the shunt capacitor vias 2810, which is in electrical contact with the substrate 2802 configured as the lower plate of the integrated capacitor. According to various embodiments, the terminal pad 2820 is formed by a high aspect ratio plating structure using techniques including those described herein. The terminal pad 2820 can be formed during the same process as used to form the coil 2814.

FIG. 26e illustrates a cover coating 2822 formed over the coil 2814, the terminal pad 2820, and the base dielectric layer 2808 to wrap the coil side of the inductive coupling coil. The cover coating 2822 is formed using deposition, etching, and patterning steps including those known in the art. For example, the cover coating 2822 can be formed of a polyimide solder mask, SU-8, KMPR, or epoxy resin.

FIG. 26f illustrates the back side of an inductively coupled coil formed in accordance with an embodiment. At least a first pad 2824 and a second pad 2826 are formed on a side of the substrate 2802 opposite to the coil 2814. According to some embodiments, the first pad 2824 and the second pad 2826 are formed of gold using deposition and patterning techniques including those known in the art. The first pad 2824 and the second pad 2826 are formed to provide electrical contact for attaching an integrated circuit chip (such as an RFID chip) to the substrate 2802.

FIG. 26g illustrates a backside dielectric layer 2828 formed on the backside of an inductively coupled coil formed in accordance with an embodiment. The method of forming an inductively coupled coil may optionally include forming a backside dielectric layer 2828 on a substrate 2802. The backside dielectric layer 2828 is formed using techniques similar to those used to form the base dielectric layer 2808. According to some embodiments, the backside dielectric layer 2828 is patterned to prevent short circuits between the substrate 2802 and an attached integrated circuit chip. According to various embodiments, the backside dielectric layer 2828 is patterned to provide a jumper pattern 2830 for the substrate 2802 to be etched to form a jumper path in a subsequent step. Other patterns in the backside dielectric may be formed so as to also etch other portions of the substrate 2802.

FIG. 26h illustrates an inductively coupled coil 2834 formed into its final shape according to an embodiment. Portions of the substrate 2802 not covered by the backside dielectric layer 2828 are etched. The etched portion includes a crossover pattern 2830 to form a crossover path 2832. The etching is performed using techniques including those known in the art. Those skilled in the art will appreciate that other portions of the substrate 2802 may be etched to form other conductive paths similar to the crossover path 2832. FIG. 26i illustrates a coil side of an inductively coupled coil 2834 including a crossover path 2832 according to an embodiment.

26j illustrates the coil side of an inductive coupling coil 2834 including an integrated chip 2836 attached to the back side of the inductive coil according to an embodiment. The method for forming the inductive coupling coil 2834 may optionally include the step of attaching an integrated chip 2836 (such as an RFID chip) to the inductive coupling coil 2834 using techniques including those known in the art. Such an integrated chip 2836 is attached using an adhesive including, but not limited to, conductive epoxy, solder, and other materials for achieving electrical connections.

The integration of capacitors into devices including high aspect ratio electroplated structures provides the ability to take advantage of the small footprint requirements that can be achieved by using high aspect ratio electroplated structures. Other embodiments of the inductively coupled coil include an inductively coupled coil with multiple integrated capacitors. As is known in the art, the integrated capacitors can be connected in parallel or in series. Other devices including high aspect ratio electroplated structures that may also include integrated capacitors include, but are not limited to, step-down transformers, signal conditioning devices, tuning devices, and other devices including one or more inductors and one or more capacitors.

High aspect ratio electroplated structures according to embodiments described herein can be used to form devices or form part of devices to optimize performance and achieve a small footprint. Such devices include, but are not limited to, power converters (e.g., step-down transformers, voltage dividers, AC transformers), actuators (e.g., linear, VCM), antennas (e.g., RFID, wireless power transfer for battery charging, and security chips), wireless passive coils, rechargeable cell phone and medical device batteries, proximity sensors, pressure sensors, contactless connectors, micromotors, microfluidics, cooling/heat sinks on packages, long narrow flexible circuits with air core capacitors and inductors (e.g., for catheters), interdigitated acoustic wave transducers, tactile vibrators, implants (e.g., pacemakers, stimulators, bone growth devices), Magnetic resonance imaging ("MRI") devices for surgery (e.g., esophageal, colonoscopy), beyond tactile (e.g., clothing, gloves), coated surfaces for detection/filter release, security systems, high energy density batteries, induction heating devices (for small local areas), magnetic fields for fluid/drug distribution and dose delivery achieved by channel pulses, tracking and information devices (e.g., agriculture, food, valuables), credit card security, audio systems (e.g., speaker coils, recharging mechanisms in headphones, earplugs), heat transfer, mechanical thermally conductive seals, energy harvesters, and interlocking shapes (similar to hook and loop fasteners). In addition, high aspect ratio electroplating structures as described herein can be used to form high bandwidth, low impedance interconnects. The use of high aspect ratio electroplating structures in interconnect applications can be used to improve electrical properties (e.g., resistance, inductance, capacitance), improve heat transfer properties, and customize dimensional requirements (thickness control). Interconnect applications including high aspect ratio electroplating structures as described herein can be used to adjust the bandwidth of one or more circuits for a given frequency range. Other interconnect applications including high aspect ratio electroplating structures can integrate one or more circuits that change current (e.g., signals and power). The use of high aspect ratio plated structures allows circuits with different cross-sections to be implemented, allowing some circuits to have greater current carrying capacity to be manufactured closely together to maintain a dense overall package size. High aspect ratio plated structures can also be used in interconnect applications for mechanical purposes. For example, it may be desirable to have some areas of the circuit protrude above other areas to serve as mechanical stops, supports, electrical contact areas, or for added rigidity.

27 illustrates a plan view of a flexure for a suspension of a hard disk drive including a high aspect ratio electroplated structure according to an embodiment. Flexure 2900 includes a distal portion 2901, a gimbal portion 2902, an intermediate portion 2904, a gap portion 2906, and a proximal portion 2908. Proximal portion 2908 is configured to be attached to a base plate so that distal portion 2901 extends above the rotating disk media. According to some embodiments, gimbal portion 2902 is configured to include: one or more motors, such as piezoelectric motors; and one or more electrical components, such as a head slider for reading or writing disk media; and components for heat assisted magnetic recording ("HAMR")/heat assisted magnetic recording ("TAMR") or microwave assisted magnetic recording ("MAMR"). The one or more motors and the one or more electrical components are electrically connected to other circuits through one or more traces formed on the conductor layer of the flexure, which extends from the distal portion 2901 of the flexure 2900 through the middle portion 2904 to over the gap portion 2906 and beyond the proximal portion 2908. The gap portion 2906 is a portion of the flexure where a base layer (such as a stainless steel layer) is partially or completely removed. Thus, one or more traces in the conductor layer of the flexure extend over the gap portion 2906 without any support. Those skilled in the art will appreciate that the flexure may have one or more gap portions 2906 at any location along the flexure.

FIG28 illustrates a cross section of a gap portion of a bend at the gap portion taken along line A as shown in FIG27 . Gap portion 2906 includes a trace 3002 disposed on a dielectric layer 3004. A dielectric layer, such as a polyimide layer, is disposed on a substrate 3006, such as a stainless steel layer. The substrate 3006 and the dielectric layer 3004 define a void 3008 such that the trace 3002 extends over the void 3008. The trace 3002 includes a metal crown portion to form a high aspect ratio structure. The metal crown portion is selectively formed on the trace 3002 using the techniques described herein. The metal crown portion is formed on the trace 3002 to provide additional strength across the void 3008 and is electrically coupled to an interconnect application at the region of the void 3008 when in use.

FIG. 29 illustrates a gimbal portion 2902 with a mass structure 3102 according to an embodiment. The mass structure 3102 is formed using the techniques described herein using a high aspect ratio electroplated structure. For some embodiments, the mass structure 3102 acts as a counterweight to adjust the resonance of the gimbal portion 2902. Thus, the shape, size, and position of the mass structure 3102 can be determined to adjust the resonance of the gimbal portion 2902, thereby enhancing the performance of the hard drive suspension. The process described herein for forming the high aspect ratio structure can be used to maintain the size of the high aspect ratio structure so that the resonance can be finely tuned. In addition, the process is capable of forming high aspect ratio structures at sizes beyond the capabilities of current photolithography processes, thereby enabling better control over the final structure formed.

The mass structure 3102 can also be configured to act as a mechanical stop. For example, one or more mechanical stops can be formed in any shape to act as a backstop and/or to align components mounted on the gimbal portion 2902 or other portions of the flexure.

FIG30 illustrates a cross section taken along line B as shown in FIG27 of a proximal portion of a bend including a high aspect ratio electroplating structure according to an embodiment. The middle portion 2904 includes: a conductor layer including traces 3002a, b, c, d disposed on a dielectric layer 3004. The dielectric layer 3004 is disposed on a substrate 3006. The cover layer 3001 is disposed on the conductor layer and the dielectric layer. The conductor layer includes conventional traces 3002a, b and traces 3002c, d, which are formed such that at least a portion of the traces include metal crown portions 3202a, b to form high aspect ratio electroplating structures using the techniques described herein. One or more portions of the traces 3002a, b, c, d can be formed to include metal crown portions 3202a, b to adjust the impedance of each trace. For example, the resistance of the traces can be adjusted as needed to meet the desired performance characteristics. Another example includes using a metal crown portion to adjust the impedance by closing the distance between adjacent traces 3002a, b, c, d.

FIG31 illustrates a cross section taken along line C as shown in FIG27 of a proximal portion of a bend including a high aspect ratio structure according to an embodiment. The proximal portion of the bend includes a conductor layer including at least a trace 3002 disposed on a dielectric layer 3004. The dielectric layer 3004 is disposed on a substrate 3006. In addition, a cover layer 3001 is disposed on the formed to include a metal crown portion to form a high aspect ratio plated structure using the techniques described herein. The trace 3002 is configured as a high aspect ratio structure to match the impedance of the trace to a terminal connector and to provide strength for the joint that electrically couples the trace 3002 to the connector. FIG32 illustrates a plan view of a proximal portion 2908 of a bend including a high aspect ratio structure according to an embodiment. The use of high aspect ratio structures as described with reference to use with a bend is also applicable to other circuit board technologies, such as for microcircuits and radio frequency ("RF") circuits.

FIG. 33 illustrates a process for forming a high aspect ratio electroplating structure according to an embodiment. As shown, a copper layer 3318 is used as a substrate. However, other conductive materials may also be used as a substrate. At 3301, a dielectric layer 3320 is disposed on the copper layer 3318, such as those described herein, and is marked and perforated. The dielectric layer 3320 may be formed using materials including, but not limited to, photoimageable or non-photoimageable materials, polymers, ceramics, and other insulating materials. For some embodiments, the copper layer 3318 is a copper alloy layer such as those described herein. For some embodiments, one or more through holes or vias 3322 are marked and perforated in the dielectric layer to expose the copper layer 3318. According to some embodiments, the dielectric layer 3320 is a photoimageable dielectric material, and one or more through holes or vias 3322 are created using patterning and development techniques including those described herein. Other embodiments include using a laser, drilling, or etching the dielectric layer 3320 to create one or more through holes or vias 3322. For some embodiments, the copper alloy layer has a thickness in the range of 15 microns to 40 microns. At 3302, traces 3324 or other conductive features are disposed on the dielectric layer 3320 on the side of the dielectric layer opposite the copper layer 3318. For some embodiments, a seed layer is sputtered using techniques including those described herein to form a pattern on the dielectric layer 3320. Other embodiments include using electroless plating to form the seed layer. Using techniques including those described herein, one or more traces 3324 and conductive features are formed to a desired thickness using a plating process such as those described herein.

At 3304, a conformal plating process, such as those described herein, is used to build up one or more traces and conductive features using techniques including those described herein to increase the thickness or further enhance the shape of one or more traces and conductive features on the side of dielectric layer 3320 opposite copper layer 3318. For some embodiments, a crown plating process, such as those described herein, is used in addition to the conformal plating process at 3304 on the side of dielectric layer 3320 opposite copper layer 3318. For some embodiments, the crown plating process is used instead of the conformal plating process.

At 3306, a dielectric layer 3326 (such as a covercoat) is disposed over the one or more traces 3324 and conductive features on the side of the dielectric layer opposite the copper layer 3318 using techniques including those described herein. For some embodiments, a covercoat is not included. For example, the formed one or more traces 3324 and conductive features may be plated with a gold layer. At 3308, the copper layer 3318 is etched using techniques including those described herein to form a pattern. For some embodiments, the copper layer 3318 is etched to form one or more traces 3328 and/or one or more conductive features.

At 3310, one or more traces 3328 and conductive features are constructed using a conformal plating process, such as those described herein, using techniques including those described herein, to increase the thickness or further enhance the shape of one or more traces 3328 and conductive features formed in copper layer 3318. For some embodiments, at 3310, a crown plating process, such as those described herein, is used in addition to the conformal plating process on copper layer 3318. For some embodiments, the crown plating process is used instead of the conformal plating process.

At 3312, a dielectric layer 3330 (such as a cover coating) is disposed on one or more traces 3328 and conductive features formed by the copper layer 3318 using techniques including those described herein. For some embodiments, a cover coating is not included. For example, the one or more traces 3328 and conductive features formed may be plated with a gold layer. For some embodiments, the process is used to manufacture multiple circuits or devices on a single substrate. At 3316, for such embodiments, the circuits or devices are separated (single) and may optionally be packaged using techniques including those known in the art. For some embodiments, circuits and/or devices are separated using techniques including, but not limited to, laser ablation, cracking, cutting, etching, etc. For some embodiments, the cover coating described herein may be patterned using the patterning techniques described herein. For example, the cover coating is applied in a blanket layer. According to some embodiments, the cover coating is applied using a slot die coating to apply a photoimageable dielectric material. Other techniques may be used, such as roller coating, spray coating, dry film lamination, or other known methods for applying photoimageable or non-photoimageable materials. If the material is not photoimageable, other methods may be used to pattern it (e.g., laser or etching). For some embodiments, one or both of the dielectric layer/cover coating may be formed with a surface finish, for example, to aid in adhesion to other structures or substrates. For some embodiments, the surface finish is formed on the dielectric layer/cover coating by texturing or patterning the dielectric layer/cover coating.

At 3314, for some embodiments, terminal pads 3332 (such as nickel terminals plated with a gold layer) may be formed on copper layer 3318 using electroless plating and solder may be provided thereto. According to some embodiments, the surface treatment formed on the exposed copper layer disposed on the top and/or bottom side is plated using electroless or electrolytic plating of nickel, gold or other industry standard surface treatments. Additionally, solder may be applied to these areas.

FIG. 34 illustrates a more detailed process similar to that described with reference to FIG. 33 for forming a high aspect ratio electroplated structure of the type in accordance with some embodiments.

FIG35 illustrates a coil manufactured using the process described herein. Coil 3501 includes multiple (e.g., three or more) coil segments electrically coupled to form coil 3501. For some embodiments, such as the embodiment shown in FIG35, the number of turns in the outer coil segment 3504 is the same as the inner coil segment 3502 between two outer coil segments 3504. For some embodiments, the inner coil segment 3502 includes more turns than the outer coil segment 3504. Other embodiments include multiple coil segments, wherein a subset of the multiple coil segments are electrically coupled, for example, referring to FIG35, two of the multiple coil segments are electrically coupled, and the remaining coil segments are not electrically coupled with the other two coil segments. Therefore, any combination of any number of coil segments can be included in any number of coil segments electrically coupled with any coil segment in the other coil segments.

Multiple layers including any one or more of the traces and conductive features fabricated using the techniques described herein may be formed by stacking each layer, and connections between each layer may be made through vias passing through the layers filled with a conductive material, such as a conductive adhesive.

According to some embodiments, the processes described herein are used to form coils in conjunction with other circuit components, such as resistance temperature detectors (RTDs), strain gauges, and other sensors.

FIG. 36 illustrates a cross-section of the coil shown in FIG. 37 , which includes a first dielectric layer/covering layer 3602, a first copper layer 3604, a second dielectric layer 3606, a second copper layer 3608, and a third dielectric layer 3610. FIG. 37 illustrates a C-shaped coil structure 3701 including a plurality of coil segments 3702 according to an embodiment. For some embodiments, a plurality of components are connected at a corner. For some embodiments, the C-shaped coil structure 3701 is formed using techniques including those described herein. The C-shaped coil structure 3701 enables manufacturing efficiency to be higher than current coil geometries. FIG. 38 illustrates an arrangement of a C-shaped coil structure 3701 according to an embodiment that achieves manufacturing efficiency. Compared to the coil structure of the prior art level, the staggered configuration enables more coil structures to be manufactured during the manufacturing process.

FIG39 illustrates a formable/Z-plane formed (e.g., offset formed) coil structure 3901 according to an embodiment. The coil structure 3901 is configured such that at least one portion or segment 3902 can be moved after circuit fabrication to form the portion, thereby providing a coil or other features, such as a bonding pad, in a substantially different plane (e.g., in the Z plane rather than the X, Y plane) from the other segments 3902 of the coil structure. For example, the segment 3902 can be mechanically formed along the dashed line 3904 to present the coil to the left of the portion in the Z plane.

FIG. 40 illustrates a C-shaped coil structure 4001 including a bridge according to an embodiment. The bridge 4002 is configured to increase the structural strength of the structure to reduce damage, for example, during processing or post-manufacturing processes. FIG. 41 illustrates a cross-section of a bridge 4002 in a C-shaped coil structure 4001 according to the embodiment shown in FIG. 40. Other embodiments of the bridge include structures formed in any free (empty) space between parts of the C-shaped coil structure. For some embodiments, the bridge may be an extension formed on at least one side of the C-shape of the coil structure, and connected by a joint, and then bent at the joint to span the opening in the C-shaped coil structure and attached to the other side to form a bridge. FIG. 42-44 illustrates an embodiment of a C-shaped coil structure 4201 including a bridge 4202 formed as an extension on at least one side of the C-shaped coil. For some embodiments, the thickness of the bridge may be thinner than the rest. For some embodiments, the bridge is configured to be flush with one or more surfaces of the coil structure, for example, flush with the mounting surface of the coil structure. For other embodiments, the bridge is configured to be recessed or below one or more surfaces of the coil structure.For some embodiments, the bridge is attached to the coil structure using an adhesive.

FIG. 45 illustrates a C-shaped coil structure 4501 including a bridge 4502 according to an embodiment. The bridge 4502 is an adhesive arranged to create a rigid structure in the gap between the portions 4504 of the coil. The adhesive can be any adhesive material that can be dispensed and cured. For some embodiments, the portion of the adhesive arranged on the coil is thinner than that in the gap. FIG. 46 illustrates a cross-section of a bridge 4502 in a C-shaped coil structure 4501 according to the embodiment shown in FIG. 45 .

FIG. 47 illustrates a coil structure 4701 according to an embodiment formed by a plurality of individual parts 4702. For some embodiments, each part includes an assembly tab 4704 for mating with a corresponding part of the coil structure. For some embodiments, the assembly tab 4704 is configured to include solder paste or other adhesive for attachment to the corresponding part. Such a coil structure 4701 will further optimize the number of coil structures that can be manufactured at a given time, thereby further contributing to reducing costs and improving other manufacturing efficiencies.

FIG48 illustrates a coil structure 4801 according to an embodiment comprising a plurality of individual parts 4802 assembled into a coil. FIG49 illustrates an alternative shape of at least a portion 4902 of a coil structure 4901 according to an embodiment. Thus, each portion may be constructed of any shape and configured to cooperate with other corresponding portions to form a coil structure.

FIG. 50 illustrates a surface mount coil used to form a coil structure according to an embodiment. For some embodiments, the surface mount coil 5002 is configured to be disposed on a substrate 5104, for example, such as shown in FIG. 51, which illustrates a top view of such a substrate 5104 including a reinforcement 5106 before attaching the surface mount coil. FIG. 52 illustrates a top view of a substrate 5202 with an attached surface mount coil 5204 according to an embodiment. For some embodiments, the substrate includes one or more traces 5206 and optional trace jumpers 5208 located on the substrate 5202. According to some embodiments, the substrate includes one or more trace jumpers 5208 to electrically couple the surface mount coil 5204 with another one or more surface mount coils 5204. The trace jumpers 5208 can also be used to electrically couple one or more surface mount coils 5204 to other components. Alternatively, the trace jumpers 5208 can be integrated with the surface mount coil 5204, for example, as shown in FIG. 53. In this configuration, according to some embodiments, the integrated trace jumpers 5302 do not increase the z-height or footprint of the final assembly and eliminate the need to add jumpers in later steps. According to some embodiments, reinforcements (such as those described herein) can be copper or other materials, such as solder mask or polyimide disposed on the substrate. According to some embodiments, the substrate includes connector pads for electrically coupling the surface mount coil to other portions of the coil and/or other circuits. The individual coils can generally be surface mount structures that are attached to: planar surfaces that can be later formed into a three-dimensional shape or are already a formed three-dimensional shape (the three-dimensional shape can be curved). In addition, for some embodiments, the surface mount structures can wrap around fillets and conform to shapes, be combined with or mounted to other structures (NFC, RFID, transformers, etc.), and/or can be stacked.

One or more surface mount coils may be attached to the substrate by connection means including, but not limited to, ACF-structures and electrical connections, ultrasonic gold ball bonding, and solder (plating, hot bar reflow, etc.). Forming the surface mount coil separate from the substrate further enables the formation of coil structures having any number of shapes or sizes. In addition, forming the surface mount coil, for example, using techniques including those described herein, enables the formation of a greater number of coils simultaneously, thereby reducing the cost of the coils to achieve manufacturing efficiencies. In addition, the manufacture of the surface mount coils enables a higher copper plating density, thereby helping to reduce the cost of forming the coil structure without negatively affecting the performance of the coil.

FIG. 54 illustrates a surface mounted coil portion 5402 according to an embodiment. Similar to other embodiments of the surface mounted coil portion described herein, such a coil portion 5402 is capable of directly attaching (one or more) high density coils to a substrate, such as a circuit board (e.g., FPC). For example, some coil portions may include internal electrical connector pads 5404 and/or external electrical connector pads 5406. FIG. 55 illustrates a circuit board 5501 configured for mounting a coil portion (such as a surface mounted coil as described herein) to form a coil structure according to an embodiment. In addition, the assembly of the coil structure, for example, mounting the surface mounted coil on a substrate, may include using a pick-and-place assembly process as used in current manufacturing processes. Therefore, the manufacturing cost of the combined coil structure is reduced. In addition, the surface mounted coil forms a coil structure without the need for an additional substrate (directly designed into the circuit and support structure of the FPC).

Figure 56 illustrates multiple views of a coil structure 5601 according to an embodiment. Figure 57 illustrates multiple views 5701 of a coil structure including a surface mount coil according to an embodiment.

Figure 58 illustrates a coil portion according to an embodiment. Coil portion 5801 includes a coil 5802 that is substantially trapezoidal in shape using the technology including those described herein. One or more coil portions 5801 with a coil 5802 that is substantially formed in a trapezoidal shape can be used with a coil structure (such as those described herein). Such a coil portion 5801 with a coil 5802 that is substantially formed in a trapezoidal shape can be used with one or more other coil portions with a coil that is formed in other shapes. In addition, other embodiments of the coil portion include a coil that is substantially formed in a shape other than a trapezoid.

FIG. 59 illustrates a coil structure according to an embodiment including solder points for attaching one or more surface mount coils. Coil structure 5901 includes one or more surface mount coils 5902. One or more surface mount coils 5902 are formed using techniques including those described herein. Coil structure 5901 includes solder points 5904 for mechanically and electrically coupling one or more surface mount coils 5902 to one or more traces 5906 and/or one or more trace jumpers 5908, such as those described herein. For some embodiments, surface mount coils 5902 are attached to the coil structure before soldering the surface mount coils 5902 to solder points 5904. According to some embodiments, surface mount coils 5902 are attached to the coil structure using an adhesive. For some embodiments, a spacer is provided between the surface mount coils 5902 and the coil structure 5901. For some embodiments, the spacer is configured to have a height that places the surface mount coils 5902 at a desired distance from another component.

FIG60 illustrates a top view of a structure including solder joints for mechanically and electrically coupling a surface mount circuit to a structure according to an embodiment. Structure 6001 includes a surface mount circuit 6002. Surface mount circuit 6002 can be any circuit and is not limited to surface mount coils, such as those described herein. Surface mount circuit 6002 is mechanically and electrically coupled to the structure using solder joints (such as those described herein). According to some embodiments, surface mount circuit 6002 is attached to structure 6001 using an adhesive before soldering surface mount circuit 6002 to the solder joints of the structure using techniques including those described herein.

FIG61 illustrates a bottom view of a structure including solder joints for mechanically and electrically coupling a surface mount circuit to the structure of FIG60. For some embodiments, the solder joints are formed to touch on a surface (e.g., bottom surface) of the structure 6001 opposite to the surface (e.g., top surface) on which the surface mount circuit is disposed. Once the surface mount circuit is disposed on the structure using techniques including those described herein, solder is disposed in the solder joints 6004. Solder may be disposed in the solder joints 6004 using techniques including, but not limited to, using solder jet application, solder paste, and manual application. For other embodiments, a surface mount circuit including a surface mount coil is coupled to the solder joints using a conductive adhesive or resistive welding.

FIG. 62 illustrates a structure including solder joints according to an embodiment. A first solder joint 6204a includes a substrate pad 6206a and a surface mount circuit pad 6208a. The substrate pad 6206a is formed by creating a void 6214 in the substrate 6212 of the structure to expose a portion of the conductive layer 6210. For some embodiments, the void 6214 may be formed in the substrate 6212 using etching techniques (including those known in the art). For other embodiments, the void 6214 is formed in the substrate 6212 using drilling or laser ablation to expose a portion of the conductive layer 6210. The conductive layer 6210 is disposed on the substrate using techniques including those described herein. The portion of the conductive layer 6210 exposed by the creation of the void 6214 is the substrate pad 6206. For some embodiments, the solder joint 6204 includes a reference point. For some embodiments, the reference point is a via, void, conductive layer, reference or other reference point for alignment. The reference point is used to align the surface mount pad with the substrate pad. For example, optical inspection techniques (such as those known in the art) may be used to detect fiducials within void 6214 to ensure that the surface mount circuit is properly aligned before solder is applied to solder joint 6204.

FIG. 63 illustrates a solder joint according to an embodiment. A solder joint 6304 includes a substrate pad 6306 exposed by a void 6314 in a substrate 6312, such as those described herein. The void 6314 is formed using techniques including those described herein. The solder joint 6304 also includes a circuit pad 6308. The circuit pad 6308 includes pads such as those described herein. The circuit pad 6308 can be formed on any substrate, including but not limited to the substrate of a surface mounted coil, a surface mounted circuit or other component.

Figure 64 illustrates a cross-sectional view of a solder joint according to an embodiment. Solder joint 6404 includes a substrate pad 6406 exposed by a void 6414 in substrate 6412, such as those described herein. Void 6414 is formed using techniques including those described herein. Solder joint 6404 also includes circuit pad 6408. Circuit pad 6408 includes pads such as those described herein. Circuit pad 6408 can be formed on any substrate, including but not limited to the substrate of a surface mounted coil, the substrate of a surface mounted circuit 6420, or the substrate of any type of component. According to some embodiments, solder 6416 is disposed in void 6414 to mechanically and electrically couple substrate pad 6406 with circuit pad 6408. Solder 6416 is disposed in the void using techniques including those described herein. For other embodiments, an adhesive such as a conductive adhesive is disposed in void 6414.

Solder joints according to the embodiments described herein enable electrical connections that reduce or eliminate short circuits by including solder or a conductive adhesive in the void area. Solder joints also enable surface mount circuits, surface mount coils, or other components to be attached to a substrate before adding solder to the solder joints, because the voids of the solder joints are formed in the surface opposite to the surface to which the surface mount circuits, surface mount coils, or other components are attached. This also enables the distance between the substrate and the surface mount circuits, surface mount coils, or other components to be minimized, thereby improving flatness and eliminating voids, for example, the voids between the surface mount coils and the substrate. The improved flatness of the surface mount circuits, surface mount coils, or other components disposed on the substrate enables the use of components with a large thickness (i.e., the height above the substrate). According to some embodiments, the flatness of the surface mount circuits, surface mount coils, or other components is 100 microns or less.

In addition, the gap enables visual inspection of the solder joint after solder is added to the solder joint. This helps verify the electrical connection. The gap allows access to the solder joint, and also enables rework of the solder joint after it is manufactured, such as reapplying solder or adhesive. In addition, by modifying the size of the solder joint to accommodate the required solder volume and gap height changes, the solder joint can be configured to be compatible with industry standard soldering processes. The solder joint also enables a robust substrate trace, thereby improving the yield of the manufacturing process.

Figure 65 illustrates a flow chart of a manufacturing process using solder joints according to an embodiment. The process includes dispensing an adhesive (6502) on a substrate, such as those described herein. The adhesive is disposed on the substrate to attach surface mount components (e.g., surface mount coils, surface mount circuits, or other components) to the substrate. For example, the surface mount components are disposed on the adhesive (6504) using a pick-and-place technique known in the art. The adhesive is cured (6506) using techniques including those known in the art to attach one or more surface mount components to the substrate. According to embodiments described herein, solder is disposed in a void in a solder joint using techniques including those described herein (6508). Alternatively, according to embodiments described herein, a conductive adhesive is disposed in a void in a solder joint using techniques including those described herein. Optionally, the manufacturing process includes testing surface mount components (6510). Such testing may include, but is not limited to, visual inspection of solder joints, electrical verification of surface mount components or circuits created by adding surface mount components, and other manufacturing tests.

FIG. 66 illustrates a coil structure according to an embodiment. The coil structure is formed using techniques including those described herein. The coil structure 6601 includes a surface mount coil 6602. The surface mount coil 6602 is attached to the coil structure 6601 using techniques including those described herein. The surface mount coil 6602 is disposed on a central portion 6610 of the coil structure 6601. The central portion 6610 is attached to an outer portion 6606 via one or more connecting portions 6608. For some embodiments, one or more traces are disposed on a substrate including at least one of the central portion 6610, the outer portion 6606, and the connecting portion 6608 to electrically couple the surface mount coil 6602 to one or more terminal pads 6604 formed on the outer portion 6606.

Figure 67 illustrates a coil structure according to an embodiment. Coil structure 6701 is formed using technologies including those described herein. Coil structure 6701 includes in-plane and out-of-plane parts. In-plane part 6702 is arranged so that they are substantially located in the same plane. In-plane and out-of-plane parts are both configured to have surface mounted components, such as surface mounted coils arranged thereon. Out-of-plane part 6704 is substantially located in a separate plane different from in-plane part 6702. Such a configuration enables the coil structure to have a non-planar configuration so that one or more parts of the substrate are substantially not located in the same plane as other parts of the substrate. This enables the configuration to meet space and design requirements while still being able to use the coil structure. Some embodiments include more than one non-planar part.

All of the coil structures, surface mount coils, surface mount circuits, and coil portions described herein may be manufactured using techniques including those described herein.

According to some embodiments, the processes described herein are used to form any one or more of mechanical structures and electromechanical structures.

Although described with reference to these embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.

Claims (16)

1. A device having a coil structure, comprising: a substrate having a first surface and a second surface opposite to each other and including a plurality of solder joints, each solder joint having a void formed in the first surface of the substrate, the substrate having a substrate pad exposed in each void; and a plurality of coil sections disposed on the substrate, each coil section being disposed on the second surface of the substrate and having a circuit pad exposed in each gap, Each solder joint includes solder applied from the first surface of the substrate into the void to mechanically and electrically couple the substrate pad and the circuit pad, such that the plurality of coil portions are electrically coupled to each other through the plurality of solder joints to form a coil structure. 2 . The device having a coil structure according to claim 1 , wherein the coil structure forms a C-shaped coil structure. 3. The device having a coil structure according to claim 1, wherein the coil portion is a surface mount coil. 4. The device having a coil structure according to claim 3, wherein the coil portion is electrically coupled to a trace on the substrate through a solder joint. The device having a coil structure according to claim 1 , wherein the substrate is a circuit board. 6. The device having a coil structure according to claim 2, comprising a bridge. 7. The device having a coil structure according to claim 6, wherein the bridge is formed of an adhesive. 8. The device having a coil structure of claim 1, wherein at least one of the plurality of coil sections comprises a trace jumper integrated with the coil section. 9. The device having a coil structure according to claim 1, wherein the substrate is formed of multiple parts. 10. The device having a coil structure of claim 9, wherein at least one of the plurality of sections comprises an assembly tab. 11. A circuit structure comprising: a substrate having a first surface and a second surface opposite to each other and including a plurality of solder joints, each solder joint having a void formed in the first surface of the substrate, the substrate having a substrate pad exposed in each void; and a plurality of surface mount circuits, each surface mount circuit being disposed on the second surface of the substrate and having a circuit pad exposed in each void, Each solder joint includes solder applied from the first surface of the substrate into the void to mechanically and electrically couple the substrate pad and the circuit pad, such that the plurality of surface mount circuits are electrically coupled to each other through the plurality of solder joints. 12. The circuit structure of claim 11, wherein at least one of the plurality of surface mount circuits is a surface mount coil. 13. The circuit structure of claim 11, wherein the substrate includes a central portion coupled to an external portion through one or more connecting portions, at least one of the plurality of surface mount circuits being disposed on the central portion. 14. A circuit structure according to claim 13, wherein one or more terminal pads are arranged on the outer portion, and the one or more terminal pads are coupled to at least one of the plurality of surface mount circuits arranged on the central portion via one or more traces partially arranged on at least one of the one or more connecting portions. 15. The circuit structure of claim 11, wherein the substrate includes at least one out-of-plane portion such that the substrate is non-planar. 16. The circuit structure of claim 15, wherein at least one of the plurality of surface mount circuits is disposed on the out-of-plane portion.