CN113330524A - High Density Coil Design and Process - Google Patents

Abstract

An apparatus includes a substrate and a plurality of coil sections disposed on the substrate. The plurality of coil portions are electrically coupled to form a coil structure.

Description

High density coil design and process

Cross reference to related applications

This application claims priority from U.S. patent application No. 16/693,125 filed on 22.11.2019 and further claims benefit from U.S. provisional application No. 62/774,027 filed on 30.11.2018, each of which is incorporated herein by reference in its entirety.

Technical Field

The present invention generally relates to coil structures and processes for making the same.

Background

Electroplating processes for fabricating structures such as copper or copper alloy Circuit structures (such as leads, traces and via interconnects) are generally known and are disclosed, for example, in U.S. patent 4,315,985 entitled "Fine-Line Circuit Fabric and Photoresist Application for" by Castellani et al. These types of processes are used, for example, in connection with the manufacture of disk drive head suspensions as disclosed in the following patents: U.S. Pat. No. 8,885,299 entitled "Low Resistance group Joints for Dual Stage Actuation Disk Drive Suspensions" to Bennin et al; U.S. Pat. No. 8,169,746 entitled "Integrated Lead Suspension with Multiple Trace Configurations" to Rice et al; U.S. Pat. No. 8,144,430 entitled "Multi-Layer group Plane Structures for Integrated Lead subsitions" by Hentges et al; U.S. Pat. No. 7,929,252 entitled "Multi-Layer group Plane Structures for Integrated Lead subsitions" by Hentges et al; swanson et al, U.S. Pat. No.5, 7,388,733 entitled "Method for Making Metal Conductive Leads for subsension Assemblies"; and U.S. Pat. No. 7,384,531 entitled "Plated group Features for Integrated Lead subsitions" by Peltoma et al. These types of processes are also used in connection with the manufacture of Camera Lens suspensions, such as disclosed in U.S. patent 9,366,879 to Miller, entitled "Camera Lens Suspension with Polymer Bearings".

Superfill and super conformal plating processes and compositions are also known and disclosed, for example, in the following articles: "The chemistry of additives in damascone coater plating", IBM J.of Res. & Dev., vol.49, No.1, month 1 2005, Vereecken et al; andricacos et al, "Damascone linkage for chip interconnections", IBM J.of Res. & Dev., vol.42, No.5, 9 months 1998; and "Curvature enhanced and adsorbed substrate conversion for bottom-up and bump control in damascone processing" by Moffat et al, Electrochimica Acta 53, pp.145-154, 2007. With these processes, in-trench plating (e.g., photoresist mask trenches define spaces for structures to be plated) occurs preferentially at the bottom. Voids in the deposited structure may thereby be avoided. All of the above patents and articles are incorporated herein by reference in their entirety and for all purposes.

There is still a continuing need for enhanced circuit structures. There is also a need for efficient and effective processes, including electroplating processes, for fabricating circuits and other structures.

Disclosure of Invention

Apparatus including high aspect ratio plated structures and methods of forming high aspect ratio plated structures are described. A method of fabricating a metal structure, comprising: providing a substrate having a metal base characterized by a height to width aspect ratio; and electroplating a metal crown on the base to form the metal structure, the metal structure having a height to width aspect ratio greater than an aspect ratio of the base.

Other features and advantages of embodiments of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.

Drawings

Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 illustrates a coil manufactured using current printed circuit technology;

fig. 2 illustrates a high density precision coil including a high aspect ratio plated structure according to an embodiment;

fig. 3 illustrates a diagram representing an electromagnetic force generated by a high-density precision coil including a high-aspect-ratio plated structure according to an embodiment;

fig. 4 illustrates an apparatus configured for linear motor type applications including multiple layers of high aspect ratio plated structures in accordance with an embodiment;

fig. 5 illustrates a high aspect ratio plated structure according to some embodiments;

fig. 6 illustrates a high aspect ratio plated structure according to some embodiments;

fig. 7 illustrates a high aspect ratio plated structure according to some embodiments;

fig. 8 illustrates a device having multiple layers of high aspect ratio plated structures having a high density cross-sectional area according to some embodiments;

fig. 9 illustrates a graph indicating SPS coverage during a high current density plating technique and a low current density plating technique in accordance with an embodiment;

fig. 10a-f illustrate a process for forming a high aspect ratio plated structure according to an embodiment;

fig. 11 illustrates a high aspect ratio plated structure according to some embodiments;

fig. 12 illustrates a perspective view of a high aspect ratio plated structure, in accordance with some embodiments;

13a, 13b illustrate a high density precision coil formed using a high aspect ratio plated structure according to an embodiment;

fig. 14 illustrates a high aspect ratio plated structure including a high resolution stacked conductor layer, in accordance with an embodiment;

fig. 15 illustrates a high density precision coil including a high aspect ratio plated structure according to an embodiment;

16a-c illustrate a process for forming a high aspect ratio plated structure according to another embodiment;

fig. 17 illustrates the selective formation of a high aspect ratio plated structure according to an embodiment;

fig. 18 illustrates a perspective view of a high aspect ratio plated structure according to an embodiment forming a metal crown portion selectively formed on a trace;

FIG. 19 illustrates a hard drive disk suspension flexure including a high aspect ratio plated structure according to an embodiment;

FIG. 20 illustrates a cross-sectional view of the hard disk drive suspension flexure shown in FIG. 19;

21a, 21b illustrate a process for forming a high aspect ratio plated structure according to an embodiment using a photoresist during a conformal plating process;

fig. 22 illustrates an exemplary chemistry of a process for forming an initial metal layer, a standard/conformal plating process, and a crown plating process, in accordance with various embodiments;

fig. 23 illustrates a perspective view of a top surface of an inductive coupling coil formed from a high aspect ratio plated structure in accordance with an embodiment;

FIG. 24 illustrates a perspective view of a back surface of the embodiment of the inductive coupling coil shown in FIG. 21;

FIG. 25 illustrates a perspective view of a top surface of an inductive coupling coil 2502 according to an embodiment coupled with a radio frequency identification chip;

26a-j illustrate a method of forming an inductive coupling coil formed from a high aspect ratio plated structure in accordance with an embodiment;

fig. 27 illustrates a plan view of a flexure for a suspension of a hard disk drive including a high aspect ratio plated structure according to an embodiment;

FIG. 28 illustrates a cross-section of a gap portion of a bend at the gap portion taken along line A as shown in FIG. 27;

FIG. 29 illustrates a gimbal portion with a mass structure according to an embodiment;

fig. 30 illustrates a cross-section of a proximal portion of a bend including a high aspect ratio plated structure according to an embodiment taken along line B as shown in fig. 27;

fig. 31 illustrates a cross-section of a proximal portion including a bend of a high aspect ratio structure according to an embodiment taken along line C as shown in fig. 27; and

fig. 32 illustrates a plan view of a proximal portion including a bend of a high aspect ratio structure in accordance with an embodiment;

fig. 33 illustrates a process for forming a high aspect ratio plated structure according to an embodiment;

FIG. 34 illustrates a more detailed process similar to the type described with respect to FIG. 33; and

FIG. 35 illustrates a coil according to an embodiment manufactured using the process described herein;

FIG. 36 illustrates a cross-section of the coil shown in FIG. 37;

fig. 37 illustrates a C-shaped coil configuration including a plurality of coil segments, in accordance with an embodiment;

fig. 38 illustrates a C-shaped coil configuration according to an embodiment;

FIG. 39 illustrates a formable/Z-plane forming coil structure according to an embodiment;

fig. 40 illustrates a C-shaped coil structure including a bridge according to an embodiment;

42-44 illustrate an embodiment of a C-shaped coil structure including a bridge according to an embodiment;

fig. 45 illustrates a C-shaped coil structure including a bridge according to an embodiment;

FIG. 46 illustrates a cross-section of a bridge in the C-shaped coil structure according to the embodiment shown in FIG. 45;

FIG. 47 illustrates a coil structure according to an embodiment formed from a plurality of separate portions;

fig. 48 illustrates a coil structure according to an embodiment comprising a plurality of separate parts;

FIG. 49 illustrates an alternative shape of at least a portion of a coil structure according to an embodiment;

fig. 50 illustrates a surface-mounted coil to form a coil structure according to an embodiment;

FIG. 51 illustrates a surface mount coil configured to be placed on a substrate, in accordance with an embodiment;

FIG. 52 illustrates a top view of a substrate with an attached surface mount coil according to an embodiment;

fig. 53 illustrates a surface mount coil including an integrated trace crossover according to an embodiment;

FIG. 54 illustrates a surface mount coil portion in accordance with an embodiment;

fig. 55 illustrates a circuit board configured for mounting a coil portion to form a coil structure according to an embodiment;

FIG. 56 illustrates multiple views of a coil structure according to an embodiment;

fig. 57 illustrates a plurality of views of a coil structure including a surface-mounted coil according to an embodiment;

fig. 58 illustrates a coil portion according to an embodiment;

FIG. 59 illustrates a coil structure according to an embodiment including solder bumps for attaching one or more surface mount coils;

FIG. 60 illustrates a top view of a structure including solder joints for mechanically and electrically coupling a surface mount circuit to a structure according to an embodiment;

FIG. 61 illustrates a bottom view of a structure including solder joints for mechanically and electrically coupling a surface mount circuit to the structure of FIG. 60;

FIG. 62 illustrates a structure including a solder joint according to an embodiment;

FIG. 63 illustrates a solder joint according to an embodiment;

FIG. 64 illustrates a cross-sectional view of a weld point according to an embodiment;

FIG. 65 illustrates a flow diagram of a manufacturing process using a solder joint according to an embodiment;

fig. 66 illustrates a coil structure according to an embodiment; and

fig. 67 illustrates a coil structure according to an embodiment.

Detailed Description

High aspect ratio plated structures and fabrication methods according to embodiments of the invention are described below. High aspect ratio plated structures provide tighter conductor spacing than current techniques. For example, according to various embodiments, a high aspect ratio plated structure comprises a conductor stack, wherein a cross-sectional area of the conductor stack is greater than 50%. In addition, the high aspect ratio plated structure makes it possible to realize a multilayer conductor according to the embodiment. Furthermore, according to various embodiments, the high aspect ratio plated structures enable precise alignment (registration) between layers. For example, a high aspect ratio plated structure may have an alignment of less than 0.030mm from layer to layer. According to various embodiments, the high aspect ratio plated structure enables a reduction in the overall stack height.

According to various embodiments, the high aspect ratio plating structure enables a thin dielectric material to be achieved between the magnet and the coil formed using the high aspect ratio plating structure. This enables the coil to generate a stronger electromagnetic field than current printed circuit coils (such as those shown in fig. 1). Thus, high aspect ratio plated structures are more cost effective, result in higher performance devices, and reduce the required footprint (footprint) of the device as compared to current technologies.

Fig. 2 illustrates a high density precision coil including a high aspect ratio plated structure according to an embodiment. The high aspect ratio plated structures 202 are formed in rows with a dielectric material between each row and each high aspect ratio plated structure 204. The high-density precision coil may be formed as a spiral coil or other coil type.

Fig. 3 illustrates a diagram representing electromagnetic forces generated by a high-density precision coil including a high-aspect-ratio plated structure according to an embodiment. The illustration includes a coil cross-section 302 near a magnet 304. The highest electromagnetic force 306 is in the coil layer 308 that is closer to the magnet 304. The coil layer 310 farther from the magnet 304 applies less force. The main factors influencing the forceSelf-lorentz equation:

because of the fact that

Is reduced with the distance between the coil and the magnet, so

Is the current flowing through the copper. Any cross-sectional area of cross-section 302 that is not a conductor versus force

There is no contribution.

The main factors that affect the force capability of the coil include the number of turns in the magnetic field (the turn closest to the pole of the magnet provides the greatest force), the coil-to-magnet distance (layers closer to the magnet will exert more force), and the total percentage of copper cross-sectional area in the magnetic field. The use of high aspect ratio plated structures according to various embodiments improves these aspects over coils using current coil technology.

For example, a coil having two layers using current technology has a total thickness of about 210 microns, a conductor pitch of 38 microns, a cross-sectional percentage of copper of about 20%, an estimated resistance of 3.1 ohms, an estimated force ratio of 1.0 (an estimated B ratio of 1.0 and an estimated J ratio of 1.0), and an estimated power ratio of 1.0. In contrast, according to various embodiments, a high density precision coil comprising a high aspect ratio plated structure has an overall thickness of about 116 microns, a conductor pitch of 40 microns, a cross-sectional percentage of copper of about 60%, an estimated resistance of 5.5 ohms, an estimated force ratio of 1.2 (an estimated B ratio of 1.5 and an estimated J ratio of 0.8), and an estimated power ratio of 0.71. Thus, according to various embodiments, high density precision coils comprising high aspect ratio plated structures are higher performance devices. Thus, according to some embodiments, such high density precision coils provide 20% more force and 30% less power at half the thickness of the coils using the current state of the art.

Fig. 4 illustrates an apparatus configured for linear motor type applications including multiple layers of high aspect ratio plated structures according to an embodiment. Each layer 402a-d of the high aspect ratio plated structure is more likely to be closer to the magnet 404 than the current technology (such as shown in fig. 1) due to the size advantages over the current technology. Further, each layer 402a-d is closer to the magnet 404 by utilizing volume

The field (flux density) improves the force capability of the linear motor. Thus, using a multi-layer high aspect ratio plated structure for a linear motor would require fewer layers than structures using current technology. Furthermore, such a structure provides greater flexibility in obtaining electrical characteristics such as low resistance.

Fig. 5 illustrates a high aspect ratio plated structure at a stage during a fabrication process according to some embodiments. The layer 602 of high aspect ratio plated structures at this stage during the manufacturing process is formed using a semi-additive technique to create fine pitch, resist defined conductors with an initial height to width aspect ratio (a/B) of approximately 1 to 1. For example, a high aspect ratio plated structure may have a height of 20 microns and a width of 20 microns. According to some embodiments, the plating process is then stopped to remove the seed layer (seed layer) and defined workpiece, such as a photoresist mask, using techniques including those known in the art.

Fig. 6 illustrates a high aspect ratio plated structure at another stage during a fabrication process according to some embodiments. The layer 702 of the high aspect ratio electroplated structure at this stage during the manufacturing process is formed using crown plate technology (crown plate technology) to convert the semi-additive conductor into a high aspect ratio, high percentage metal conductor circuit. For example, high aspect ratio plated structures have a final height to width ratio (a/S) greater than 1 to 1. According to various embodiments, the final height to width ratio may be in a range including 1.2 to 3.0. Other embodiments include a final height to width ratio greater than 3.0. However, one skilled in the art will appreciate that any final height to width ratio can be achieved using the techniques described herein to meet design and performance criteria. The final height of the high aspect ratio plated structure as disclosed in the various embodiments is not particularly limited at the stage of formation as shown in fig. 6, which is formed from a previous stage as shown in fig. 5.

Fig. 7 illustrates a high aspect ratio plated structure at yet another stage during a fabrication process according to some embodiments. The layers 802a, b of the high aspect ratio plated structure at this stage during the manufacturing process are formed using a planarization technique conversion to allow stacking of multiple layers of the high aspect ratio plated structure using a semi-additive technique to form subsequent layers. Figure 8 illustrates a device having a multi-layer high aspect ratio plated structure with a high fraction of conductor cross-sectional area 901 according to some embodiments.

Methods for forming high aspect ratio plated structures from structures such as those shown in fig. 5 include the use of low current density plating techniques. The plating technique plates the sidewalls until the desired space is obtained between the high aspect ratio plated structures. For various embodiments, undesirable squeezing of the top may occur if the spaces between the high aspect ratio plated structures are not sufficiently narrow. Extrusion occurs where the top edges of adjacent structures grow together and pinch off the gap, which results in a short circuit. For the various embodiments, the low current density plating process is enhanced by sufficient fluid exchange to make fresh plating bath continuously available to the surface where copper plating occurs. Further, methods for forming high aspect ratio plated structures include using high current density plating techniques. This high current density plating technique operates at a high percentage of the mass transfer limit. This is primarily or only plated on top of the conductive material forming the high aspect ratio plated structures. The high current density plating process is enhanced by precise current density control. Fig. 9 illustrates a graph having an upper line 1002 and a lower line 1004, the upper line 1002 indicating high SPS coverage during a high current density plating technique according to an embodiment, and the lower line 1004 indicating low, very uniform catalyst (promoter) coverage during a low current density plating technique according to an embodiment.

Fig. 10a-f illustrate a process for forming a high aspect ratio plated structure according to an embodiment. Fig. 10a illustrates a trace 1102 formed at the thickness limit of resist capability (etch resistance) at time T1 of the process. For some embodiments, the pre-plated conventional traces are formed from copper using processes such as damascene processes, or using etching and deposition techniques including those known in the art. Fig. 10b illustrates the formation of a high aspect ratio plated structure at time T2 during a low current density or conformal plating process. According to an embodiment, the conformal plating process grows all surfaces of the trace at approximately the same rate. In addition, conformal plating processes suppress plating kinetics (low catalyst coverage). The conformal plating process also provides a fairly uniform metal concentration with a high, uniform inhibitor coverage to compensate. This effect of suppressing plating kinetics can be enhanced by including a leveler in the plating bath. Lower current densities are required to achieve uniform metal concentrations and to achieve high, uniform inhibitor coverage. According to some embodiments, a conformal plating process of 2 amps per square decimeter is used for plating, such as copper, brightener additives, temperature and hydrodynamics of the plater. Examples of such conformal plating processes include, but are not limited to, low current density plating processes. At low current densities, the plating bath maintains a uniformly contained state to provide conformal plating. For another embodiment, a leveler may be added to the plating bath to provide higher current density and faster plating. For yet another embodiment, increasing the copper content to near the solubility limit of copper sulfate in the plating bath may be used to further increase the current density. This provides the ability to double the current density or even larger to achieve the same conformal plating quality. For example, the copper content can be as high as 40 grams per liter with a reduced acid content to prevent the common ionic effects.

For some embodiments, a low current density plating process deposits a conductive material (such as copper) onto the top and sidewalls of the traces 1102, e.g., T2 enters the process for about five minutes (T1+5 minutes) during the low current density plating process. Figure 10c illustrates the formation of a high aspect ratio plated structure during the low current density plating process at time T3 into the process. For an embodiment, a low current density plating process deposits a conductive material (such as copper) onto the top and sidewalls of the traces 1102, e.g., T3 enters the process for about five minutes (T1+15 minutes) during the low current density plating process.

Fig. 10d illustrates the formation of a high aspect ratio plated structure at time T4 entering the process during a crown plating process, such as a high current anisotropic overplate process. For example, T4 entered the process for approximately 15 minutes 10 seconds (T1+15 minutes 10 seconds). For some embodiments, the high current anisotropic overplate process is crown plating. Crown plating is based on balancing the interactions between: the concentration of metal in the solution; a brightener additive; an inhibitor additive; mass transfer to surface-fluid exchange rate; leveling agent; and the current density at the substrate. The metal concentration in the solution may include, but is not limited to, copper. Brightener additives may include, but are not limited to, SPS (bis (3-sulfopropyl) -disulfide), DPS (3-N, N-dimethylaminodithiocarbamoyl-1-propanesulfonic acid), and MPS (mercaptopropylsulfonic acid). Inhibitor additives may include, but are not limited to, straight PEGs of various molecular weights (including those known to those skilled in the art), poloxamine, co-block polymers of polyethylene and polypropylene glycol, such as the water-soluble poloxamers known under various commercial names, such as the addition polymer of BASF pluronic (r) f127 of BASF polypropylene glycol and ethylene oxide, and such as

Random copolymers of UCON series high performance fluids (again in various proportions of monomers and various molecular weights), polyvinylpyrrolidones of various molecular weights.

According to some embodiments, the high current anisotropic overplate process includes a suppressed exchange current that is 1% of the accelerating current. In addition, the sidewalls of the high aspect ratio plated structures are formed with almost zero catalyst coverage. Almost zero catalyst coverage is achieved by shifting the Nernst potential for copper deposition to facilitate inhibitor coverage. In addition, high overpotentials and copper availability (transport phenomena) result in high catalyst coverage on top of the formed structures. The copper mix concentrate (copper bulk concentrate) may also be adjusted to support almost zero catalyst coverage during the process. For example, the copper mixed concentrate for the high current anisotropic overplating process is 14 grams/liter or less. For some embodiments, the copper mix concentrate depends on the specific hydrodynamics. Because various embodiments of the process operate at a high fraction of the mass transfer limit, small differences in fluid velocity across the articles to be coated will affect the mass transfer limit, making it difficult to achieve adequate control of the gap between the coating lines without high control of fluid velocity across all areas of the articles to be coated. According to some embodiments, the high current anisotropic overplating process includes a leveler additive to disable catalyst coverage to minimize or eliminate plating on the sidewalls of the structure being formed. For other examples, the plating bath was used without leveler additives.

According to some embodiments, at elevated current densities (such as those used in high current anisotropic overplate processes), a triple feedback mechanism works. The mass transfer effect depletes the copper in the space between the traces. In addition, the high current density supports a catalyst (e.g., SPS) dominated surface. To maintain the suppressed sidewalls, mass transfer is adjusted by the copper mass transfer effect to reduce the nernst potential. For example, the fluid boundary layer thickness and the spacing between each trace are designed to reduce the Nernst potential.

Further, according to some embodiments, the high current anisotropic overplate process includes operating at a copper concentration at which these differences may create a concentration difference greater than four times. Under such conditions, the lower copper concentration and nernst potential help to reduce the plating rate. For example, this may contribute to a 20-fold reduction in plating rate when the nernst potential shifts approximately in the range of 50 millivolts ("mV") to 60 mV. Such conditions induce Tafel kinetics which are ten times the change in current for every 120mV change in applied voltage (not rectifier voltage) for copper plating. Lower sidewall current is fed back to the top surface of the structure being formed, where the diffusion length is short, which promotes faster transport of metal from the plating bath (solution) to the surface and higher catalyst coverage rather than suppression, as well as the gaussian potential. For some embodiments, a two additive system (e.g., brightener and suppressor) is used. The leveler reduces the feedback mechanism by blocking SPS activity on the top side of the plated feature.

As the spacing between metal conductors or traces continues to shrink, the aspect ratio of the height to the width of the spaces between the metal conductors substantially increases. According to some embodiments, the method of electroplating process provided herein includes electroplating a metal conductor in a space between metal conductors at 7: aspect ratios of 1 and greater achieve plating.

According to some embodiments, a method of forming a high aspect ratio plated structure provides selective formation of a metal crown plating at selective locations or areas. In one exemplary embodiment, the selective formation of the metal crown is achieved by performing an electroplating process according to the following relationship:

where C is the concentration of the metal (in this case copper) at which plating occurs and C ∞ is the volume concentration in the plating bath. This relationship may also be expressed as performing a plating process, wherein

Equal to or greater than 67 percent (67%) of the mass transfer limit. According to other embodiments, the selective formation of the metal crown is achieved by performing an electroplating process according to the following relationship:

or at

Equal to or greater than 80% of the mass transfer limit. On the other hand, by following the following relationshipAn electroplating process is performed to achieve selective formation of a metal crown:

where i is the current density, i_limitIs the current density limit.

Fig. 10e illustrates the formation of a high aspect ratio plated structure at time T5 during a high current anisotropic overplate process. For example, T5 entered the process for approximately 15 minutes 30 seconds (T1+15 minutes 30 seconds). For another embodiment, the formation of the high aspect ratio plated structure as shown in fig. 10e occurs at time T5-T1 +5 minutes. Fig. 10f illustrates the formation of a high aspect ratio plated structure at time T6 during a high current anisotropic overplate process. This figure illustrates the end of the crown plating process, which ends the formation of the high aspect ratio plated structure according to some embodiments. For example, T6 entered the process for approximately 20 minutes (T1+20 minutes). For another embodiment, the formation of the high aspect ratio plated structure as shown in fig. 10f occurs at time T6-T1 +10 minutes.

For some embodiments, the methods for forming high aspect ratio electroplated structures use processes including conformal plating and anisotropic plating described herein. According to some embodiments, the conformal plating process uses 2/3 of the total plating time. For other embodiments, the conformal plating process uses 1/3 of the total plating time. Further, the conformal plating process starts at 2 amps per square decimeter ("ASD") for low metal plating baths or at 4ASD for high metal plating baths. For example, the plating bath includes 12 grams/liter copper and 1.85 moles (moles/liter) sulfuric acid. Alternatively, the conformal plating process is a process that plates at a rate of 0.4 to 1.2 microns/minute. According to an embodiment, the conformal plating process continues until the spaces between the traces are in a range including 6-8 microns. As the surface area of the formed structure increases, the current density will slowly decrease. However, this process will achieve a uniform current density and growth rate for all surfaces formed. For some embodiments, as the surface area of the high aspect ratio structures formed increases, the current may be increased to maintain the current density.

According to some embodiments, the anisotropic plating process uses 1/3 total plating time to form high aspect ratio plated structures. The anisotropic plating process increased the ASD to 7ASD (3.5 times the current of the conformal plating process), but on average twice as high at the top of the metal structures formed. The same fluid flow rate as used in the conformal plating process may be maintained. For example, the plating rate is 3 microns/min at the top of the formed structure with almost zero plating rate on the sidewalls of the structure. As the structure grows, the average current drops by half, but according to an embodiment, the peak current density is maintained at about 14ASD at the top of the structure. For example, the peak current density is just over 50% of the mass transfer limit at the top surface, and even if the sidewalls are exposed to about 3 grams/liter of copper, the sidewalls are exposed to a current flow rate of less than 10% or 5: 1 plating rate plating. At higher fractions of the mass transfer limit, higher plating rate ratios can be obtained.

Embodiments of methods for forming high aspect ratio plated structures include variations of those described above to form high aspect ratio plated structures comprising different characteristics. For example, as described above, the copper content in the plating bath configured as an anisotropic bath may be different from 13.5 grams/liter. Altering the copper content in the flat trace plating solution while using the same current density can be used to control the spacing between high aspect ratio plated structures. Another embodiment of the method described herein includes using a flat trace plating solution having a flat trace plating solution with a copper content of 12 grams/liter to form high aspect ratio plated structures spaced 8 microns apart. Yet another embodiment of the method described herein includes using a flat trace plating solution having a flat trace plating solution therein of 15 grams/liter to form high aspect ratio plated structures spaced apart by 4 microns. Accordingly, one skilled in the art will appreciate that other parameters for adjusting the methods described herein may be used to alter the characteristics of a high aspect ratio plated structure. Some embodiments of the methods described herein include adjusting the current density to match current plating conditions, such as mass transfer rate, metals contained in the plating bath, fluid velocity, copper concentration, additives used, and temperature.

The method for forming a high aspect ratio plated structure further includes using a thin dielectric process. According to some embodiments, a photosensitive polyimide is used as a dielectric between each high aspect ratio plated structure. Liquid photosensitive polyimide enables small via capability, good coverage between high aspect ratio conductors, good alignment/edge capability, is a high reliability material, and has a coefficient of thermal expansion ("CTE") that is closely matched to copper. The liquid photosensitive polyimide can easily fill the gaps between the high aspect ratio plated structures. According to some embodiments, liquid photosensitive polyimide is used to create vias as low as 0.030 millimeters. Other dielectrics that may be used include, but are not limited to, KMPR and SU-8.

Fig. 11 illustrates a high aspect ratio plated structure formed using the methods described herein, in accordance with some embodiments. Each high aspect ratio plated structure 1202 includes a plurality of textured lines 1204 that illustrate how the plating process proceeds to form the structure. A thin dielectric 1206 is formed between the high aspect ratio plated structures 1202 and is disposed over the high aspect ratio plated structures 1202. Fig. 12 illustrates a perspective view of a high aspect ratio plated structure 1302 formed using methods described herein, in accordance with some embodiments.

The methods described herein can be used to form high aspect ratio plated structures that form high density precision coils. Figure 13a illustrates a high density precision coil formed using a high aspect ratio plated structure according to an embodiment. The coils 1402 are formed from high aspect ratio plated structures such as those described herein. The high-density precision coil also includes a center coil via 1404. The central coil via 1404 reduces the voltage drop across the coil during the manufacturing steps described herein. Further, the central coil via 1404 enables the ability to better control the variability of spacing within the coil by better controlling the voltage drop and current during the anisotropic plating process described herein. The central coil via 1404 also enables better control of the voltage drop of the high density precision coil formed. Fig. 13b illustrates a cross-section of a center coil via 1404 as part of a high density precision coil as described herein.

Fig. 14 illustrates a high aspect ratio plated structure including a high resolution stacked conductor layer, in accordance with an embodiment. The first conductor layer 1502a includes a high aspect ratio plated structure 1504 formed using techniques including those described herein. First dielectric layer 1508 is formed using a thin dielectric process using techniques including those described herein. The first dielectric layer 1508 fills all spaces between the high aspect ratio plated structures of the first conductor layer 1502a and forms a coating over the high aspect ratio plated structures 1504. The first dielectric layer 1508 is planarized using techniques known in the art. The second conductor layer 1502b includes a high aspect ratio plated structure 1506 formed over the planarized surface of the first dielectric layer 1508. The second dielectric layer 1510 is formed using a thin dielectric process using techniques including those described herein to fill all spaces between the high aspect ratio plated structures 1506 of the second conductor layer 1502b and form a coating over the high aspect ratio plated structures 1506. The second dielectric layer 1510 may also be planarized. Additional layers including high aspect ratio plated structures may be formed using the techniques described herein.

Fig. 15 illustrates a high density precision coil including a high aspect ratio plated structure according to an embodiment, including a high resolution stacked conductor layer. The first conductor layer 1602a includes high aspect ratio plated structures formed using techniques including those described herein. The first dielectric layer 1608 is formed using a thin dielectric process using techniques including those described herein. First dielectric layer 1608 fills all spaces between the high aspect ratio plated structures of first conductor layer 1602a and forms a coating over the high aspect ratio plated structures. The first dielectric layer 1608 is planarized using techniques known in the art. Second conductor layer 1602b includes a high aspect ratio plated structure formed over a planarized surface of first dielectric layer 1608. The second dielectric layer 1610 is formed using a thin dielectric process using techniques including those described herein to fill all spaces between the high aspect ratio plated structures of the second conductor layer 1602b and form a coating over the high aspect ratio plated structures. The second dielectric layer 1610 may also be planarized. Additional layers including high aspect ratio plated structures may be formed using the techniques described herein.

The high-density precision coil is formed with a first distance 1614 between the high aspect ratio plated structures of the first conductor layer 1602a and the high aspect ratio plated structures of the second conductor layer 1602 b. For various embodiments, the first distance 1614 is less than 0.020 millimeters. For another embodiment, the first distance 1614 is 0.010 millimeters. The high-density precision coil is formed with a second distance 1616 between the surface 1618 of the second dielectric layer 1610 and the high-aspect-ratio plated structures of the first conductor layer 1602 a. For various embodiments, the second distance 1616 is less than 0.010 millimeters. For some embodiments, the second distance 1616 is 0.005 millimeters. For some embodiments, the second distance 1616 may be the starting gap minus the final desired gap divided by 2. The high-density precision coil is formed with a third distance 1620 between the high aspect ratio plated structure of the first conductor layer 1602a and the surface of the first dielectric layer 1622. For various embodiments, third distance 1620 is less than 0.020 millimeters. For some embodiments, the third distance 1620 is less than 0.015 millimeters. For another embodiment, the third distance 1620 is 0.010 millimeters. For the various embodiments, a first dielectric layer is formed on substrate 1624 using techniques including those described herein. For some embodiments, substrate 1624 is a stainless steel layer. One skilled in the art will appreciate that substrate 1624 may be formed from other materials, including but not limited to steel alloys, copper alloys such as bronze, pure copper, nickel alloys, beryllium copper alloys, and other metals, including those known in the art.

Other advantages of forming devices using high aspect ratio plated structures as described herein include devices having high structural strength, high reliability, and high heat dissipation capabilities. High structural strength is provided by the ability to form very dense concentrations of metal high aspect ratio plated structures on all layers of the device. In addition, the processes used to form the metal high aspect ratio plated structures described herein provide lateral alignment of the structures from layer to layer, thereby increasing high structural strength. The high structural strength of devices formed using the processes for forming the metal high aspect ratio plated structures described herein is also a result of the good adhesion of the dielectric layer material (such as a photosensitive polyimide layer) to the structure. For some embodiments, the high aspect ratio plated structures formed using the techniques described herein are coated with a non-magnetic nickel layer to increase adhesion of the dielectric layer. This will further increase the high structural strength of the final device formed using the high aspect ratio plated structures described herein.

The reliability of devices formed using the high aspect ratio plated structures described herein is also high because highly reliable materials are used, such as photosensitive polyimide for the dielectric layer, which provides robust electrical performance. Using the techniques described herein, the ability to form devices with less dielectric material is provided and the overall thickness of the formed devices is reduced. Thus, heat dissipation is increased by increased thermal conductivity compared to devices using current process technology.

Fig. 16a-c illustrate a process for forming a high aspect ratio plated structure according to another embodiment. FIG. 16a illustrates a trace 1802 formed on a substrate 1804 using subtractive etching. According to some embodiments, a metal layer is formed over substrate 1804. A photoresist layer is formed over the metal layer using techniques including those known in the art. For some embodiments, the photoresist layer is a photosensitive polyimide deposited in liquid form over the metal layer. The photoresist is patterned and developed using techniques including those known in the art. The metal layer is then etched using techniques including those known in the art. After the etching process, traces 1802 are formed.

Fig. 16b illustrates the formation of a high aspect ratio plated structure using a conformal plating process, such as those described herein. Fig. 16c illustrates the formation of a high aspect ratio plated structure using a crown plating process, such as those described herein. For various embodiments, the high aspect ratio plated structures are formed without using a conformal plating process (such as the process described with reference to fig. 16 b). Instead, a crown plating process (such as the process described with reference to fig. 16 c) is used after forming the traces 1802 as shown in fig. 16 a.

Figure 17 illustrates selective formation of a high aspect ratio plated structure according to an embodiment. Once the traces 1902 have been formed using techniques including those described herein, a photoresist layer 1904 is formed over portions of one or more of the formed traces 1902. Photoresist layer 1904 can be a photosensitive polyimide and deposited and formed using techniques including those described herein. A metal crown 1906 is formed on the trace 1902 using one or both of a conformal plating process and a crown plating process as described herein. Fig. 18 illustrates a perspective view of a high aspect ratio plated structure according to an embodiment forming a metal crown portion selectively formed over a trace. According to some embodiments, selectively forming metal crown portions on the traces serves to improve structural properties of the high aspect ratio plated structures, improve electrical performance of the high aspect ratio plated structures, improve heat transfer characteristics, and meet custom size requirements of devices formed using the high aspect ratio plated structures. Examples of electrical performance improvements include, but are not limited to, capacitive, inductive, and resistive properties of high aspect ratio plated structures. In addition, selectively forming metal crown portions on the traces can be used to adjust mechanical or electrical properties of circuits formed using high aspect ratio plated structures.

FIG. 19 illustrates a hard drive disk suspension flexure 2102 that includes a high aspect ratio plated structure according to embodiments formed using selective formation as described herein. FIG. 20 illustrates a cross-sectional view of the hard disk drive suspension flexure shown in FIG. 19 taken along line A-A. The cross-section of the bend 2102 includes high aspect ratio plated structures 2104 and traces 2106. The high aspect ratio electroplated structures 2104 are formed using selective formation techniques as described herein. Forming the high aspect ratio plated structure 2104 to serve as a conductor in a predetermined region of the bend may achieve a reduction in DC resistance. This allows for the formation of fine lines and spaces where needed on the bend while meeting the design requirements for DC resistance and improving the electrical performance of the bend.

Fig. 21a, b illustrate a process for forming a high aspect ratio plated structure according to an embodiment using a photoresist during a conformal plating process. Fig. 21a illustrates traces 2302 formed on a substrate 2304 using techniques including those described herein. Fig. 21b illustrates the formation of a high aspect ratio plated structure using a plating process as described herein. Photoresist portions 2306 are formed over substrate 2304 using deposition and patterning techniques including those described herein. Once photoresist portions 2306 are formed, one or both of a conformal plating process and a crown plating process are performed to form metal portions 2308 on traces 2302. Photoresist portions 2306 can be used to better define the spacing between high aspect ratio plated structures.

Fig. 22 illustrates exemplary chemistries of a process for forming an initial metal layer, a standard/conformal plating process, and a crown plating process, in accordance with various embodiments.

Fig. 23 illustrates a perspective view of a top surface 2501 of an inductive coupling coil 2502 with an integrated tuning capacitor formed from a high aspect ratio plated structure 2504 in accordance with an embodiment. Forming the inductive coupling coil using the high aspect ratio plating structure reduces the footprint of the inductive coupling coil as compared to inductive coupling coils formed using current techniques. This enables the inductive coupling coil 2502 to be used in space-limited applications. In addition, using a capacitor integrated in the inductive coupling coil further reduces the footprint of the inductive coupling coil because no additional space requirements are required to accommodate discrete capacitors, such as surface mount technology ("SMT") capacitors.

Fig. 24 illustrates a perspective view of the back surface 2604 of the embodiment of the inductive coupling coil 2502 shown in fig. 23. Fig. 25 illustrates a perspective view of a top surface of an inductive coupling coil 2502 according to an embodiment coupled with a radio frequency identification ("RFID") chip 2704.

Fig. 26a-j illustrate a method of forming an inductive coupling coil 2502 formed of a high aspect ratio plated structure 2504 in accordance with an embodiment. According to various embodiments, the inductive coupling coil includes an integrated tuning capacitor. Fig. 26a illustrates a substrate 2802 formed using techniques including those known in the art. For some embodiments, substrate 2802 is formed from stainless steel. Other materials that may be used for the substrate include, but are not limited to, steel alloys, copper alloys, aluminum, non-conductive materials that may be metallized using techniques including plasma vapor deposition, chemical vapor deposition, and electroless chemical deposition. A shadow mask 2804 is formed over the substrate 2802. Shadow mask 2804 is a high K dielectric according to some embodiments. Examples of high-K dielectrics that may be used include, but are not limited to, titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, SU-8, KMPR, and other high-dielectric constant dielectric materials. The shadow mask 2804 is formed using a sputtering process using techniques including those known in the art, according to some embodiments. For some embodiments, shadow mask 2804 is formed to have a thickness included in the range of 500 to 1000 angstroms. For other embodiments, shadow mask 2804 is formed using screen printing of a high dielectric constant ink. Examples of high dielectric constant inks include inks comprising epoxy loaded with particles made from one or more of titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, and other high dielectric constant dielectric materials. For still other embodiments, shadow mask 2804 is formed using a slot die application (slot die application) of a photoimageable dielectric doped with a high K filler. Examples of high K fillers include zirconium dioxide (ZrO 2).

Fig. 26b illustrates a metal capacitor plate 2806 formed over a shadow mask 2804. Metal capacitor plate 2806 and substrate 2802 form the two capacitor plates of an integrated capacitor. The thickness of the shadow mask 2804 can be used to set the effective capacitance of the integrated capacitor. Furthermore, the purity of the high-K dielectric used to form shadow mask 2804 can be used to set the effective capacitance of the integrated capacitor. The surface area of metal capacitor plate 2806 may also be used to set the effective capacitance of the integrated capacitor.

Fig. 26c illustrates base dielectric layer 2808 formed over shadow mask 2804, metal capacitor plate 2806, and at least a portion of substrate 2802. According to some embodiments, base dielectric layer 2808 is formed by depositing a dielectric material, patterning the dielectric material, and curing the dielectric material using techniques including those known in the artThereby forming the composite material. Examples of dielectric materials that may be used include, but are not limited to, polyimide, SU-8, KMPR, and hard-baked photoresist (such as polyimide film made of polyimide, or a combination of two or more of these materials)

Those sold). Base dielectric layer 2808 may also be patterned or etched to form vias. For example, a crossover via 2812 and a shunt capacitor via 2810 are formed in the base dielectric layer 2808. A shunt capacitor via 2810 is formed to interconnect the integrated capacitor with the rest of the circuit to be formed. Similarly, the crossover via 2812 is used to interconnect a circuit element to be formed with the substrate 2802.

Fig. 26d illustrates a coil 2814 formed over a base dielectric layer 2808 using high aspect ratio plated structures for forming coils using techniques including those described herein. For some embodiments, coil 2814 is a single layer coil. The coil 2814 includes a center connection portion 2816 that is connected to one of the shunt capacitor vias 2810 and one of the crossover vias 2812 that is in electrical contact with the metal capacitor plate 2806 of the integrated capacitor. The coil 2814 also includes a capacitor connection portion 2818 to connect the coil 2814 to another of the shunt capacitor vias 2810, the other shunt capacitor via 2810 being in electrical contact with the substrate 2802 configured as a lower plate of the integrated capacitor. According to various embodiments, terminal pads 2820 are formed from high aspect ratio plated structures using techniques including those described herein. The terminal pad 2820 may be formed during the same process as used to form the coil 2814.

Fig. 26e illustrates a cover coating 2822 formed over the coil 2814, terminal pads 2820, and base dielectric layer 2808 to encapsulate the coil side of the inductive coupling coil. The overcoat 2822 is formed using deposition, etching, and patterning steps including those known in the art. For example, the covercoat 2822 may be formed of a polyimide solder mask, SU-8, KMPR, or epoxy.

Fig. 26f illustrates a backside of an inductive coupling coil formed in accordance with an embodiment. At least a first pad 2824 and a second pad 2826 are formed on a side of the substrate 2802 opposite the coil 2814. According to some embodiments, first bond pad 2824 and second bond pad 2826 are formed from gold using deposition and patterning techniques, including those known in the art. First bond pad 2824 and second bond pad 2826 are formed to provide electrical contacts for attaching an integrated circuit chip (such as an RFID chip) to substrate 2802.

Fig. 26g illustrates a backside dielectric layer 2828 formed on the backside of an inductive coupling coil formed in accordance with an embodiment. The method of forming the inductive coupling coil may optionally include forming a backside dielectric layer 2828 on the substrate 2802. Backside dielectric layer 2828 is formed using techniques similar to those used to form base dielectric layer 2808. According to some embodiments, the backside dielectric layer 2828 is patterned to prevent shorting between the substrate 2802 and an attached integrated circuit chip. According to various embodiments, the backside dielectric layer 2828 is patterned to provide a strapping pattern 2830 for the substrate 2802 to be etched to form strapping paths in subsequent steps. Other patterns in the backside dielectric may be formed to also etch other portions of the substrate 2802.

Fig. 26h illustrates the inductive coupling coil 2834 formed into its final shape, in accordance with an embodiment. The portion of the substrate 2802 not covered by the backside dielectric layer 2828 is etched. The etched portion includes a crossover pattern 2830 to form a crossover path 2832. The etching is performed using techniques including those known in the art. Those skilled in the art will appreciate that other portions of substrate 2802 may be etched to form other conductive paths similar to crossover path 2832. Fig. 26i illustrates the coil side of an inductive coupling coil 2834 including a crossover path 2832, according to an embodiment.

Fig. 26j illustrates the coil side of an inductive coupling coil 2834 including an integrated chip 2836 attached to the backside of the inductive coil, according to an embodiment. The method for forming the inductive coupler coil 2834 may optionally include the step of attaching an integrated chip 2836 (such as an RFID chip) to the inductive coupler coil 2834 using techniques including those known in the art. Such integrated chips 2836 are attached using adhesives including, but not limited to, conductive epoxies, solders, and other materials used to make electrical connections.

Integration of capacitors into devices including high aspect ratio plated structures provides the ability to take advantage of the small footprint requirements that can be achieved by using high aspect ratio plated structures. Other embodiments of the inductive coupling coil include an inductive coupling coil with a plurality of integrated capacitors. The integrated capacitors may be connected in parallel or in series, as is known in the art. Other devices that include high aspect ratio plated structures that may also include integrated capacitors include, but are not limited to, step-down transformers, signal conditioning devices, tuning devices, and other devices that include one or more inductors and one or more capacitors.

High aspect ratio plated structures according to embodiments described herein may be used to form devices or to form portions of devices to optimize performance and achieve small footprints. Such devices include, but are not limited to, power converters (e.g., step-down transformers, voltage dividers, AC transformers), actuators (e.g., linear, VCM), antennas (e.g., RFID, wireless power transfer for battery charging, and security chips), wireless passive coils, rechargeable cell phone and medical device batteries, proximity sensors, pressure sensors, contactless connectors, micro-machines, micro-fluidics, cooling/heat sinks on packaging, long and narrow flexible circuits with air-cored capacitance and inductance (e.g., for catheters), interdigital acoustic wave transducers, tactile vibrators, implants (e.g., pacemakers, stimulators, bone growth devices), magnetic resonance imaging ("MRI") devices for surgery (e.g., esophagus, colonoscopy), beyond tactile (e.g., clothing, gloves), coated surfaces for detection/filter release, coated surfaces for electrical signal detection/signal detection, electrical signal detection, and signal detection, Security systems, high energy density batteries, induction heating devices (for small local areas), magnetic fields for fluid/drug dispensing and dose delivery by channel pulsing, tracking and information devices (e.g., agriculture, food, valuables), credit card security, sound systems (e.g., speaker coils, recharging mechanisms in headphones, earplugs), heat transfer, mechanical heat conducting seals, energy harvesters, and interlocking shapes (similar to hook and loop fasteners). Furthermore, high aspect ratio plated structures as described herein can be used to form high bandwidth, low impedance interconnects. The use of high aspect ratio plated structures in interconnect applications can be used to improve electrical characteristics (e.g., resistance, inductance, capacitance), improve heat transfer properties, and customize dimensional requirements (thickness control). Interconnect applications including high aspect ratio plated structures as described herein may be used to tune the bandwidth of one or more circuits for a given frequency range. Other interconnect applications that include high aspect ratio plated structures may integrate one or more circuits that vary current (e.g., signal and power). The use of high aspect ratio plated structures allows for the implementation of circuits with different cross sections, allowing some circuits to have greater current carrying capacity in order to be fabricated closely together to maintain a dense overall package size. High aspect ratio plated structures may also be used for interconnect applications for mechanical purposes. For example, it may be desirable to have some areas of the circuit protrude above other areas to serve as mechanical stops, supports, electrical contact areas, or to increase rigidity.

Fig. 27 illustrates a plan view of a flexure for a suspension for a hard disk drive including a high aspect ratio plated structure according to an embodiment. Bend portion 2900 includes a distal portion 2901, a gimbal portion 2902, an intermediate portion 2904, a gap portion 2906, and a proximal portion 2908. Proximal portion 2908 is configured to attach to a backplane such that distal portion 2901 extends above the rotating disk media. According to some embodiments, gimbal portion 2902 is configured to include: one or more motors, such as piezoelectric motors; and one or more electrical components, such as a head slider for reading or writing to a disk medium; and components for heat assisted magnetic recording ("HAMR")/heat assisted magnetic recording ("TAMR") or microwave assisted magnetic recording ("MAMR"). The one or more motors and one or more electrical components are electrically connected to other circuitry through one or more traces formed on a conductor layer of the bend portion that extends from the distal portion 2901 of the bend portion 2900, through the intermediate portion 2904, and over the gap portion 2906 and beyond the proximal portion 2908. The gap portion 2906 is a portion of the bend where the base layer (such as a stainless steel layer) is partially or completely removed. Thus, one or more traces in the conductor layer of the bend extend over the gap portion 2906 without any support. One skilled in the art will appreciate that the bend may have one or more gap portions 2906 at any location along the bend.

Fig. 28 illustrates a cross section of a gap portion of a bend at the gap portion taken along line a shown in fig. 27. The gap portion 2906 includes traces 3002 disposed over the dielectric layer 3004. A dielectric layer, such as a polyimide layer, is disposed over a substrate 3006, such as a stainless steel layer. Substrate 3006 and dielectric layer 3004 define voids 3008 such that traces 3002 extend above voids 3008. Trace 3002 includes a metal crown portion to form a high aspect ratio structure. A metal crown portion is selectively formed on trace 3002 using techniques described herein. A metal crown portion is formed on trace 3002 to provide additional strength across void 3008 and, in use, to electrically couple with an interconnect application at the area of void 3008.

FIG. 29 illustrates a gimbal portion 2902 having a mass structure 3102, according to an embodiment. The quality structure 3102 is formed using high aspect ratio plated structures using techniques described herein. For some embodiments, the mass structure 3102 serves as a counterweight that adjusts the resonance of the gimbal portion 2902. Thus, the mass structure 3102 can be shaped, sized, and positioned to tune the resonance of the gimbal portion 2902 to enhance the performance of the hard drive suspension. The processes described herein for forming high aspect ratio structures can be used to maintain the size of the high aspect ratio structures so that resonances can be fine tuned. In addition, the process enables the formation of high aspect ratio structures at dimensions beyond the capabilities of current lithographic processes, thereby enabling better control over the final structures formed.

The mass structure 3102 may also be configured to act as a mechanical stop. For example, the one or more mechanical stops may be formed in any shape to serve as a backstop and/or to align the mounting of components on the gimbal portion 2902 or other portion of the flexure.

Fig. 30 illustrates a cross-section of a proximal portion of a bend including a high aspect ratio plated structure according to an embodiment taken along line B as shown in fig. 27. Proximal portion 2904 includes: a conductor layer including traces 3002a, b, c, d disposed over the dielectric layer 3004. A dielectric layer 3004 is disposed over substrate 3006. The cover layer 3001 is disposed over the conductor layer and the dielectric layer. The conductor layer includes conventional traces 3002a, b and traces 3002c, d formed such that at least a portion of the traces include metal crown portions 3202a, b to form high aspect ratio plated structures using the techniques described herein. One or more of the traces 3002a, b, c, d may be formed to include a metal crown portion 3202a, b to adjust the impedance of each trace. For example, the resistance of the traces may be adjusted as needed to meet desired performance characteristics. Another example includes using a metal crown portion to adjust the impedance by closing the distance between adjacent traces 3002a, b, c, d.

Fig. 31 illustrates a cross-section of a proximal portion including a bend of a high aspect ratio structure according to an embodiment taken along line C as shown in fig. 27. The proximal portion of the bend includes a conductor layer that includes at least trace 3002 disposed over dielectric layer 3004. Dielectric layer 3004 is disposed on substrate 3008. In addition, a capping layer 3001 is disposed over the formation to include a metal crown portion to form a high aspect ratio plated structure using the techniques described herein. The traces 3002 are configured as high aspect ratio structures to match the impedance of the traces to the terminating connector and provide strength to the joint that electrically couples the traces 3002 to the connector. Fig. 32 illustrates a plan view of a proximal portion 2908 including a bend of a high aspect ratio structure according to an embodiment. The use of high aspect ratio structures as described with reference to use with flexures is also applicable to other circuit board technologies, for example, for microcircuits and radio frequency ("RF") circuits.

Figure 33 illustrates a process for forming a high aspect ratio plated structure according to an embodiment. As shown, copper layer 3318 serves as the substrate. However, other conductive materials may also be used as the substrate. At 3301, a dielectric layer 3320 is disposed on copper layer 3318, such as those described herein, and marking and perforating are performed. Dielectric layer 3320 may be formed using materials including, but not limited to, photoimageable or non-photoimageable materials, polymers, ceramics, and other insulating materials. For some embodiments, the copper layer 3318 is a copper alloy layer such as those described herein. For some embodiments, one or more vias or vias 3322 are marked and punched in the dielectric layer to expose the copper layer 3318. According to some embodiments, dielectric layer 3320 is a photoimageable dielectric material and one or more vias or vias 3322 are created using patterning and developing techniques including those described herein. Other embodiments include using a laser, drilling, or etching dielectric layer 3320 to create one or more vias or vias 3322. For some embodiments, the copper alloy layer has a thickness in a range including 15 microns to 40 microns. At 3302, traces 3324 or other conductive features are disposed on dielectric layer 3320 on a side of the dielectric layer opposite copper layer 3318. For some embodiments, a seed layer is sputtered using techniques including those described herein to form a pattern on dielectric layer 3320. Other embodiments include forming the seed layer using electroless plating. The one or more traces 3324 and conductive features are formed to a desired thickness using a plating process, such as those described herein, using techniques including those described herein.

At 3304, one or more traces and conductive features are built using a conformal plating process (such as those described herein) using techniques including those described herein to increase the thickness or further enhance the shape of the one or more traces and conductive features on the side of dielectric layer 3320 opposite copper layer 3318. For some embodiments, a crown plating process, such as those described herein, is used in addition to the conformal plating process, at 3304, on the side of dielectric layer 3320 opposite copper layer 3318. For some embodiments, a crown plating process is used instead of a conformal plating process.

At 3306, a dielectric layer 3326 (such as an overcoat) is disposed over the one or more traces 3324 and conductive features on a side of the dielectric layer opposite the copper layer 3318 using techniques including those described herein. For some embodiments, no overcoat is included. For example, the one or more traces 3324 and conductive features formed may be plated with a layer of gold. At 3308, the copper layer 3318 is etched to form a pattern using techniques including those described herein. For some embodiments, the copper layer 3318 is etched to form one or more traces 3328 and/or one or more conductive features.

At 3310, one or more traces 3328 and conductive features are built using a conformal plating process (such as those described herein) using techniques including those described herein to increase the thickness or further enhance the shape of the one or more traces 3328 and conductive features formed in the copper layer 3318. For some embodiments, at 3310, a crown plating process, such as those described herein, is used in addition to the conformal plating process on the copper layer 3318. For some embodiments, a crown plating process is used instead of a conformal plating process.

At 3312, a dielectric layer 3330 (such as an overcoat) is disposed over the one or more traces 3328 and conductive features formed from the copper layer 3318 using techniques including those described herein. For some embodiments, no overcoat is included. For example, the one or more traces 3328 and conductive features formed may be plated with a layer of gold. For some embodiments, the process is used to fabricate multiple circuits or devices on a single substrate. At 3316, for such embodiments, the circuits or devices are separate (unitary), and optionally may be packaged using techniques including those known in the art. For some embodiments, the circuits and/or devices are separated using techniques including, but not limited to, laser ablation, fracturing, cutting, etching, and the like. For some embodiments, the covercoats described herein may be patterned using the patterning techniques described herein. For example, the cover coat is applied in a blanket layer. According to some embodiments, the slot die coating is used to apply a covercoat to apply the photoimageable dielectric material. Other techniques may be used, such as roll coating, spray coating, dry film lamination, or other known methods for applying photoimageable or non-photoimageable materials. If the material is non-photoimageable, it may be patterned using other methods (e.g., laser or etching). For some embodiments, one or both of the dielectric layer/overcoat layer may be formed with a surface finish (surface finish), for example, to aid in adhesion to other structures or substrates. For some embodiments, the surface treatment is formed on the dielectric layer/overcoat by texturing or patterning the dielectric layer/overcoat.

At 3314, for some embodiments, terminal pads 3332 (such as gold-plated nickel terminals) may be formed on the substrate 3318 using electroless plating and may be provided with solder. According to some embodiments, the surface treatment formed on the bare copper layer provided on the top and/or bottom side is plated or other industry standard surface treatment is performed using electroless or electrolytic plating of nickel, gold. In addition, solder may be applied to these areas.

Figure 34 illustrates a more detailed process of the type used to form high aspect ratio plated structures according to some embodiments, similar to that described with reference to figure 33.

Fig. 35 illustrates a coil manufactured using the process described herein. The coil 3501 includes a plurality of (e.g., three or more) coil segments that are electrically coupled to form the coil 3501. For some embodiments, such as the embodiment shown in fig. 35, the number of turns in the outer coil segment 3504 is the same as the inner coil segment 3502 between the two outer coil segments 3504. For some embodiments, the inner coil section 3402 includes more turns than the outer coil section 3504. Other embodiments include a plurality of coil segments, wherein a subset of the plurality of coil segments are electrically coupled, e.g., referring to fig. 35, two of the plurality of coil segments are electrically coupled, and the remaining coil segments are not electrically coupled with the other two coil segments. Thus, any combination of any number of coil segments may be included in any number of coil segments electrically coupled with any of the other coil segments.

Multiple layers including any one or more of traces and conductive features fabricated using the techniques described herein may be formed by stacking each layer, and connections between each layer may be made through vias through the layers filled with conductive material (such as a conductive adhesive).

According to some embodiments, the processes described herein are used to form coils in conjunction with other circuit components, such as Resistance Temperature Detectors (RTDs), strain gauges, and other sensors.

Fig. 36 illustrates a cross-section of the coil shown in fig. 37 including a first dielectric/capping layer 3602, a first copper layer 3604, a second dielectric layer 3606, a second copper layer 3608, and a third dielectric layer 3610. Fig. 37 illustrates a C-shaped coil structure 3701 including a plurality of coil segments 3702, according to an embodiment. For some embodiments, multiple components are connected at the corners. For some embodiments, the C-shaped coil structure 3701 is formed using techniques including those described herein. The C-shaped coil structure 3701 enables higher manufacturing efficiencies than current coil geometries. Fig. 38 illustrates an arrangement of a C-shaped coil structure 3701 that achieves manufacturing efficiency, according to an embodiment. The staggered configuration enables more coil structures to be manufactured in the manufacturing process than state of the art coil structures.

Fig. 39 illustrates a shapeable/Z-plane shaped (e.g., offset formed) coil structure 3901 according to an embodiment. The coil structure 3901 is configured such that at least one portion or segment 3902 can be moved after circuit fabrication to form the portion to provide coils or other features, such as bond pads, in a substantially different plane (e.g., in the Z-plane rather than the X, Y plane) than other segments 3902 of the coil structure. For example, the segment 3902 can be mechanically formed along the dashed line 3904 to present the coil to the left of the portion in the Z-plane.

Fig. 40 illustrates a C-shaped coil structure 4001 including a bridge according to an embodiment. Bridge 4002 is configured to increase the structural strength of the structure to reduce damage, e.g., during processing or post-fabrication processes. Fig. 41 illustrates a cross-section of a bridge 4002 in a C-shaped coil structure 4001 according to the embodiment illustrated in fig. 40. Other embodiments of the bridge include structures formed in any free (empty) space between portions of the C-shaped coil structure. For some embodiments, the bridge may be an extension formed on at least one side of the C-shape of the coil structure and connected by a joint, then bent at the joint to span the opening in the C-shaped coil structure and attached to the other side to form the bridge. Fig. 42-44 illustrate an embodiment of a C-shaped coil structure 4201 including a bridge 4202 formed as an extension on at least one side of the C-shaped coil. For some embodiments, the thickness of the bridge may be thinner than the rest. For some embodiments, the bridge is configured to be flush with one or more surfaces of the coil structure, e.g., flush with a mounting surface of the coil structure. For other embodiments, the bridge is configured to be recessed or below one or more surfaces of the coil structure. For some embodiments, the bridge is attached to the coil structure using an adhesive.

Fig. 45 illustrates a C-shaped coil structure 4501 including a bridge 4502, according to an embodiment. Bridge 4502 is an adhesive that is disposed to create a rigid structure in the gap between portions 4504 of the coil. The adhesive may be any attachment material that can be dispensed and cured. For some embodiments, the portion of adhesive disposed on the coil is thinner than in the gap. Fig. 46 illustrates a cross-section of a bridge 4502 in a C-shaped coil structure 4501 in accordance with the embodiment illustrated in fig. 45.

Fig. 47 illustrates a coil structure 4701 according to an embodiment formed from a plurality of individual portions 4702. For some embodiments, each portion includes an assembly tab 4704 for mating with a corresponding portion of the coil structure. For some embodiments, the assembly tabs 4704 are configured to include solder paste or other adhesive for attachment to a corresponding portion. Such a coil structure 4701 would further optimize the number of coil structures that can be fabricated at a given time, thereby further contributing to reduced costs and improved other manufacturing efficiencies.

Fig. 48 illustrates a coil structure 4801 according to an embodiment comprising a plurality of individual portions 4802 assembled into a coil. Fig. 49 illustrates an alternative shape of at least a portion 4902 of a coil structure 4901 in accordance with an embodiment. Thus, each portion may be constructed of any shape and configured to cooperate with other corresponding portions to form a coil structure.

Fig. 50 illustrates a surface-mounted coil to form a coil structure according to an embodiment. For some embodiments, the surface mount coil 5002 is configured to be disposed on a substrate 5104, for example, such as shown in fig. 51, which illustrates a top view of such a substrate 5104 including a stiffener 5106 prior to attachment of the surface mount coil. Fig. 52 illustrates a top view of a substrate 5202 with an attached surface mounted coil 5204 in accordance with an embodiment. For some embodiments, the substrate includes one or more traces 5206 and an optional stiffener 5208 on the substrate 5202. According to some embodiments, the substrate includes one or more trace crossovers 5208 to electrically couple the surface mounted coil 5204 with another one or more surface mounted coils 5204. Trace crossovers 5208 may also be used to electrically couple one or more surface mount coils 5204 to other components. Alternatively, the trace jumper 5208 may be integrated with the surface mount coil 5204, for example, as shown in fig. 53. In this configuration, the integrated trace crossover 5302 does not increase the z-height or footprint of the final assembly and eliminates the need for a crossover that is added in a later step, according to some embodiments. According to some embodiments, the stiffener (such as those described herein) may be copper or other material, such as a solder mask or polyimide disposed on the substrate. According to some embodiments, the substrate comprises connector pads for electrically coupling the surface mount coil to other parts of the coil and/or other circuitry. The individual coils may generally be surface mount structures that are attached to: planar surfaces that may later form a three-dimensional shape or that may already be formed (the three-dimensional shape may be curved). Further, for some embodiments, the surface mount structures may wrap around corners and conform to shape, bond with or mount to other structures (NFC, RFID, transformers, etc.), and/or may be stacked.

The one or more surface mount coils may be attached to the substrate by connection means including, but not limited to, ACF-structures and electrical connections, ultrasonic gold ball bonding, and solder (plating, hot bar reflow, etc.). Forming the surface-mounted coil separate from the substrate further enables formation of coil structures having any number of shapes or sizes. Further, forming the surface-mount coils, for example, using techniques including those described herein, enables a greater number of coils to be formed simultaneously, thereby reducing coil cost to achieve manufacturing efficiencies. In addition, the manufacture of surface mount coils enables higher copper plating densities, thereby helping to reduce the cost of forming the coil structure without adversely affecting coil performance.

Fig. 54 illustrates a surface mount coil portion 5402 according to an embodiment. Similar to other embodiments of surface-mounted coil portions described herein, such coil portions 5402 can attach high-density coil(s) directly to a substrate, such as a circuit board (e.g., FPC). For example, some coil portions may include inner electrical connector pads 5404 and/or outer electrical connector pads 5406. Fig. 55 illustrates a circuit board 5501 configured for mounting coil portions (such as surface mount coils as described herein) to form a coil structure according to an embodiment. Further, assembly of the coil structure, e.g., mounting the coil on a base mounting surface, may include using a pick and place assembly process as used in current manufacturing processes. Therefore, the manufacturing cost of the combined coil structure is reduced. Furthermore, the surface mount coil-forming coil structure does not require an additional substrate (directly designed as a circuit and support structure for the FPC).

Fig. 56 illustrates multiple views of a coil structure 5601, in accordance with an embodiment. Fig. 57 illustrates a number of views 5701 of a coil structure including a surface mount coil according to an embodiment.

Fig. 58 illustrates a coil portion according to an embodiment. Coil portion 5801 includes a substantially trapezoidal shape of coil 5802 formed using techniques including those described herein. One or more coil portions 5801 having coils 5802 formed substantially in a trapezoidal shape may be used with coil structures such as those described herein. Such a coil portion 5801 having a coil 5802 formed in a substantially trapezoidal shape may be used with one or more other coil portions having coils formed in other shapes. Further, other embodiments of the coil portion include a coil having a shape substantially other than a trapezoid.

FIG. 59 illustrates a coil structure according to an embodiment including solder bumps for attaching one or more surface mount coils. The coil structure 5901 includes one or more surface mount coils 5902. The one or more surface mount coils 5902 are formed using techniques including those described herein. The coil structure 5901 includes weld spots 5904 for mechanically and electrically coupling one or more surface mount coils 5902 to one or more traces 5906 and/or one or more trace crossovers 5908, such as those described herein. For some embodiments, the surface mount coil 5902 is affixed to the coil structure prior to welding the surface mount coil 5902 to the weld spot 5904. According to some embodiments, the surface mount coil 5902 is affixed to the coil structure using an adhesive. For some embodiments, a spacer is disposed between the surface mount coil 5902 and the coil structure 5901. For some embodiments, the spacer is configured to have a height that places the surface mount coil 5902 at a desired distance from another component.

Fig. 60 illustrates a top view of a structure including solder joints for mechanically and electrically coupling a surface mount circuit to a structure according to an embodiment. The structure 6001 includes a surface mount circuit 6002. The surface mount circuit 6002 may be any circuit and is not limited to surface mount coils, such as those described herein. The surface mount circuitry 6002 is mechanically and electrically coupled to the structure using solder joints, such as those described herein. According to some embodiments, the surface mount circuitry 6002 is attached to the structure 6001 using an adhesive prior to soldering the surface mount circuitry 6002 to the pads of the structure using techniques including those described herein.

Fig. 61 illustrates a bottom view of a structure including solder joints for mechanically and electrically coupling a surface mount circuit to the structure of fig. 60. For some embodiments, the solder bumps are formed to touch on a surface (e.g., bottom surface) of structure 6001 opposite the surface on which the surface mount circuitry is disposed (e.g., top surface). Once the surface mount circuits are provided on the structure using techniques including those described herein, solder is provided in the solder joints 6004. Solder may be disposed in the solder joints 6004 using techniques including, but not limited to, using solder spray application, solder paste, and manual application. For other embodiments, the surface mount circuitry including the surface mount coil is coupled to the solder joints using a conductive adhesive or resistance welding.

FIG. 62 illustrates a structure including a solder joint according to an embodiment. The first pad 6204a includes a substrate pad 6206a and a surface-mounted circuit pad 6208 a. The substrate pad 6206a is formed by creating a void 6214 in the substrate 6212 of the structure to expose a portion of the conductive layer 6210. For some embodiments, the voids 6214 can be formed in the substrate 6210 using etching techniques (including those known in the art). For other embodiments, voids 6214 are formed in the substrate 6210 using drilling or laser ablation to expose a portion of the conductive layer 6210. The conductive layer 6210 can be disposed on the substrate using techniques including those described herein. The portion of conductive layer 6210 exposed by the creation of void 6214 is substrate pad 6206. For some embodiments, weld 6204 comprises fiducial 6210. For some embodiments, the reference point is a via, void, conductive layer, fiducial, or other reference point for alignment. The fiducials are used to align the surface mount pads with the substrate pads. For example, optical inspection techniques (such as those known in the art) can be used to detect fiducial points 6210 within the voids 6214 to ensure that the surface mount circuits are properly aligned prior to applying solder to the solder joints 6204.

FIG. 63 illustrates a solder joint according to an embodiment. Solder joint 6304 includes substrate pad 6306 exposed through void 6314 in substrate 6312, such as those described herein. Voids 6314 are formed using techniques including those described herein. Pad 6304 also includes circuit pad 6308. Circuit pads 6308 include pads such as those described herein. The circuit pads 6308 may be formed on any substrate including, but not limited to, a substrate on which coils, surface mount circuits, or other components are mounted.

FIG. 64 illustrates a cross-sectional view of a weld point according to an embodiment. Solder joint 6404 includes substrate pad 6406 exposed through void 6414 in substrate 6412, such as those described herein. The voids 6414 are formed using techniques including those described herein. Pad 6404 also includes circuit pad 6408. Circuit pads 6408 include pads such as those described herein. The circuit pads 6408 may be formed on any substrate, including but not limited to a substrate for surface mounting coils, a substrate for surface mounting circuitry 6420, or a substrate for any type of component. According to some embodiments, solder 6416 is disposed in voids 6414 to mechanically and electrically couple substrate pads 6406 with circuit pads 6408. The solder 6416 is disposed in the voids using techniques including those described herein. For other embodiments, an adhesive, such as a conductive adhesive, is disposed in the void 6414.

Solder joints according to embodiments described herein enable electrical connections that reduce or eliminate shorts by including solder or conductive adhesive within the void area. Solder joints also enable surface mount circuits, surface mount coils, or other components to be attached to a substrate prior to adding solder to the solder joints because the voids of the solder joints are formed in the surface opposite the surface to which the surface mount circuits, surface mount coils, or other components are attached. This also enables the distance between the substrate and the surface mount circuit, surface mount coil, or other component to be minimized, thereby improving flatness and eliminating voids, for example, between the surface mount coil and the substrate. The improved flatness of surface mount circuits, surface mount coils, or other components disposed on a substrate enables the use of components having a large thickness (i.e., height above the substrate). According to some embodiments, the flatness of the surface mount circuit, surface mount coil, or other component is 100 microns or less.

Furthermore, the voids enable visual inspection of the solder joint after solder is added to the solder joint. This helps to verify the electrical connection. Access to the solder joint is enabled by the void, and rework, e.g., reapplication of solder or adhesive, of the solder joint after the solder joint is manufactured. In addition, the solder joint can be configured to be compatible with industry standard soldering processes by modifying the dimensions of the solder joint to accommodate the required solder volume and gap height variations. Solder joints also enable robust substrate traces, thereby improving the yield of the manufacturing process.

FIG. 65 illustrates a flow diagram of a manufacturing process using a solder joint according to an embodiment. The process includes dispensing an adhesive (6502) on a substrate, such as those described herein. An adhesive is disposed on the substrate to affix a surface mount component (e.g., a surface mount coil, surface mount circuit, or other component) to the substrate. The surface mount component is disposed on the adhesive (6504), for example, by using pick and place techniques known in the art. The adhesive is cured (6506) using techniques including those known in the art to affix the one or more surface mount components to the substrate. According to embodiments described herein, solder is disposed in the voids of the solder joint using techniques including those described herein (6508). Alternatively, according to embodiments described herein, the conductive adhesive is disposed in the interstices of the solder joint using techniques including those described herein. Optionally, the manufacturing process includes testing the surface mount component (6510). Such tests may include, but are not limited to, visual inspection of solder joints, electrical verification of surface mount components or circuits created by the addition of surface mount components, and other manufacturing tests.

Fig. 66 illustrates a coil structure according to an embodiment. The coil structures are formed using techniques including those described herein. Coil structure 6601 includes surface mount coil 6602. Surface-mounted coil 6602 is affixed to coil structure 6601 using techniques including those described herein. The surface-mounted coil 6602 is disposed on a central portion 6604 of the coil structure 6601. The central portion 6610 is attached to the outer portion 6606 by one or more connecting portions 6608. For some embodiments, one or more traces are disposed on the substrate including at least one of the central portion 6610, the outer portion 6606, and the connection portion 6608 to electrically couple the surface mount coil 6602 to one or more terminal pads 6604 formed on the outer portion 6606.

Fig. 67 illustrates a coil structure according to an embodiment. Coil structure 6701 is formed using techniques including those described herein. The coil structure 6701 includes portions that are in-plane and out-of-plane. The in-plane portions 6702 are arranged such that they are located substantially in the same plane. The in-plane and out-of-plane portions are each configured to have surface mount components, such as surface mount coils disposed thereon. The out-of-plane portions 6704 lie substantially in a separate plane than the in-plane portions 6702. Such a configuration enables the coil structure to have a non-planar configuration such that one or more portions of the substrate are not substantially in the same plane as other portions of the substrate. This enables the arrangement to meet space and design requirements while still enabling the use of a coil structure. Some embodiments include more than one non-planar portion.

All of the coil structures, surface mount coils, surface mount circuits, and coil portions described herein can be fabricated using techniques including those described herein.

According to some embodiments, the processes described herein are used to form any one or more of a mechanical structure and an electromechanical structure.

Although described in connection with these embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.

Claims (20)

1. An apparatus, comprising:

a substrate; and

a plurality of coil portions disposed on the substrate, the plurality of coil portions being electrically coupled to form a coil structure.

2. The apparatus of claim 1, wherein the coil structure forms a C-shaped coil structure.

3. The apparatus of claim 1, wherein the coil portion is a surface mount coil.

4. The apparatus of claim 3, wherein the coil portion is electrically coupled to a trace on the substrate by a solder joint.

5. The apparatus of claim 1, wherein the substrate is a circuit board.

6. The device of claim 2, comprising a bridge.

7. The device of claim 6, wherein the bridge is formed of an adhesive.

8. The apparatus of claim 1, wherein at least one of the one or more coil portions comprises a trace jumper integrated with the coil portion.

9. The device of claim 1, wherein the substrate is formed from a plurality of portions.

10. The apparatus of claim 9, wherein at least one of the plurality of portions comprises an assembly tab.

11. A structure, comprising:

a substrate; and

a plurality of surface mount circuits disposed on the substrate and electrically coupled to each other.

12. The coil structure of claim 11 wherein at least one of the plurality of surface mount circuits is a surface mount coil.

13. The coil structure of claim 11 wherein at least one of the plurality of surface mount circuits includes a circuit pad.

14. The coil structure of claim 13, wherein the substrate comprises solder bumps.

15. The coil structure of claim 14 wherein the solder joint comprises a substrate pad and the circuit pad exposed in a void formed in the substrate.

16. The coil structure of claim 15 wherein the solder joint further comprises solder disposed on the circuit pad and the substrate pad.

17. The coil structure of claim 11, wherein the substrate comprises a central portion coupled to an outer portion by one or more connection portions, at least one of the plurality of surface mount circuits being disposed on the central portion.

18. The coil structure of claim 11, wherein one or more terminal pads are disposed on the outer portion and the one or more terminal pads are coupled with at least one of the plurality of surface mount circuits disposed on the central portion by one or more traces partially disposed on at least one of the one or more connection portions.

19. The structure of claim 11, wherein the substrate includes at least one out-of-plane portion such that the substrate is non-planar.

20. The structure of claim 11, wherein at least one of the plurality of surface mount circuits is disposed on the planar outer portion.

Images