CN113325225B - Zero-crossing detection circuit with self-adaptive delay compensation and control method - Google Patents
Zero-crossing detection circuit with self-adaptive delay compensation and control method Download PDFInfo
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
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- H—ELECTRICITY
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- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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Abstract
The invention provides a zero-crossing detection circuit with self-adaptive delay compensation and a control method thereof. The invention relates the compensation current of zero crossing, which can be called as the lead of zero crossing, to the slope of the inductance current, when the falling slope of the inductance current is larger, the lead of the compensation current is larger, and the zero crossing detected by the zero crossing comparator is more accurate under different slopes of the inductance current.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a zero-crossing detection circuit.
Background
With the rapid development of integrated circuit technology, handheld devices in life are becoming more and more widely used, and mobile power devices are becoming indispensable. The input and output voltage range is wide, and the control of the buck-boost DCDC structure is needed. In order to ensure the efficiency of the circuit in the light load mode, the DCM mode needs to be introduced into the circuit, so that the accuracy of zero-crossing detection becomes very important to the performance influence of the circuit in the light load mode.
Although the existing zero-crossing detection circuit has many advantages, the zero-crossing detection circuit of the DCDC buck-boost circuit applied to the mobile power supply device has many disadvantages, in the mobile power supply application, the input and output voltages of the DCDC buck-boost circuit can be greatly changed according to different conditions, so that the gradient change range of the inductance current is very wide under different conditions, and the traditional zero-crossing detection method for setting the fixed advance is not applicable any more.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a zero-crossing detection circuit with self-adaptive delay compensation and a control method.
The technical scheme adopted for solving the technical problems is as follows:
a zero-crossing detection circuit with self-adaptive delay compensation comprises a power level DCDC circuit, a current sampling circuit, a compensation module with self-adaptive delay compensation and a zero-crossing comparator; the current sampling circuit samples the output V of the power stage DCDC circuit OUT End sampling resistor R 0 The compensation circuit samples the voltage at two ends and the power level DCDC circuit inductance L 0 Two-terminal voltage SW 1 、SW 2 The final current sampling circuit and the compensation circuit convert the sampled voltage into current and then convert the current into voltage, and then output the voltage to the in-phase end and the anti-phase end of the zero-crossing comparator respectively, and the zero-crossing comparator outputs a comparison result.
The power stage DCDC circuit comprises power switch MOS transistors MN0-MN3 and an inductor L 0 Sampling resistor R 0 And a load capacitance C 0 The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the power switch MOS tube MN0 is connected with the internal port SW 1 Grid connection V of power switch MOS tube MN0 0 Terminal, power switch MOS tube MN0 drain electrode connects input port V IN The source electrode of the power switch MOS tube MN1 is connected to the power ground, and the grid electrode of the power switch MOS tube MN1 is connected with the V 1 Terminal, power switch MOS tube MN0 drain electrode connects internal port SW 1 The source electrode of the power switch MOS tube MN2 is connected to the power ground, and the grid electrode of the power switch MOS tube MN2 is connected with the V 2 Terminal, power switch MOS tube MN0 drain electrode connects internal port SW 2 Source electrode of power switch MOS tube MN3 is connected with internal port SW 2 Grid connection V of power switch MOS tube MN3 3 End, output port V is connected to power switch MOS pipe MN3 drain OUT The method comprises the steps of carrying out a first treatment on the surface of the The inductance L 0 Is connected to the internal port SW 1 The other end is connected with the internal port SW 2 The load capacitance C 0 The upper polar plate is connected with the output port V OUT The lower polar plate is grounded, and the sampling resistor R 0 Is connected with the switching resistor R 3 One end of (a) is connected with the output port V OUT Andconversion resistor R 4 Is provided.
The current sampling circuit comprises P-channel enhancement type MOS transistors MP2-MP4 and a conversion resistor R 3 、R 4 、R 6 Current sources IB1 and IB2; the drain electrode and the grid electrode of the P-channel enhancement type MOS tube MP2 are connected with the current inflow end of the current source IB1 and the grid electrode of the P-channel enhancement type MOS tube MP3, and the source electrode is connected with the conversion resistor R 3 One end and the source electrode of the P channel enhancement type MOS tube MP 4; the drain electrode of the P-channel enhancement type MOS tube MP3 is connected with the grid electrode of the P-channel enhancement type MOS tube MP4 and the current inflow end of the current source IB2, the grid electrode is connected with the grid electrode and the drain electrode of the P-channel enhancement type MOS tube MP2 and the current inflow end, and the source electrode is connected with the conversion resistor R 4 One end; the drain electrode of the P-channel enhanced MOS tube MP4 is connected with a conversion resistor R 6 The grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube MP3 and the current inflow end of the current source IB2, and the source electrode is connected with the conversion resistor R 3 A source electrode of the P channel enhancement MOS tube MP2 and one end of the P channel enhancement MOS tube; the switching resistor R 3 One end is connected with a sampling resistor R 0 One end is connected with the source electrode of the P-channel enhancement type MOS tube MP4 and the source electrode of the P-channel enhancement type MOS tube MP 2; the switching resistor R 4 One end of (a) is connected with the output port V OUT Sampling resistor R 0 The other end of the transistor is connected with the source electrode of the P-channel enhancement type MOS tube MP 3; the switching resistor R 6 One end of the zero-crossing comparator is connected with the same-phase end of the zero-crossing comparator and the drain electrode of the P-channel enhancement type MOS tube MP4, and the other end of the zero-crossing comparator is connected with the power supply ground; the current inflow end of the current source IB1 is connected with the drain electrode and the grid electrode of the P-channel enhancement type MOS tube MP2 and the grid electrode of the P-channel enhancement type MOS tube MP3, and the current outflow end is connected with the power supply ground; the current inflow end of the current source IB2 is connected with the grid electrode of the P-channel enhancement type MOS tube MP4 and the drain electrode of the P-channel enhancement type MOS tube MP3, and the current outflow end is connected with the power ground.
The non-inverting terminal of the zero-crossing comparator is connected with a switching resistor R 6 One end of the P channel enhancement type MOS tube MP4 and the drain electrode, the reverse phase end is connected with the conversion resistor R 5 The current outflow end of the current source IB0 and the drain electrode of the P-channel enhancement type MOS tube MP1 are connected with the output port ZC of the zero-crossing detection circuit。
The compensation circuit is composed of N-channel enhancement type MOS tubes MN4-MN7, P-channel enhancement type MOS tubes MP0 and MP1 and a conversion resistor R 1 、R 2 、R 5 A current source IB 0; the grid electrode and the drain electrode of the N-channel enhanced MOS tube MN4 are connected with a conversion resistor R 1 The source electrode of the N-channel enhancement MOS tube MP5 is connected with the power supply ground; the drain electrode of the N-channel enhanced MOS tube MN5 is connected with a conversion resistor R 2 Gate and drain of N-channel enhancement type MOS transistor MN6 and gate of N-channel enhancement type MOS transistor MN7, gate connected to gate and drain of N-channel enhancement type MOS transistor MN4 and switching resistor R 1 The source electrode is connected with the power ground; the drain electrode and the grid electrode of the N-channel enhanced MOS tube MN6 are connected with the conversion resistor R together 2 The source electrode of the N channel enhancement type MOS tube MN7 is connected with the power supply ground; the drain electrode of the N-channel enhancement type MOS tube MN7 is connected with the grid electrode and the drain electrode of the P-channel enhancement type MOS tube MP0 and the grid electrode of the P-channel enhancement type MOS tube MP1, and the grid electrode is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube MN6 and the conversion resistor R 2 The source electrode is connected with the power ground; the drain electrode and the grid electrode of the P-channel enhancement type MOS tube MP0 are connected with the drain electrode of the N-channel enhancement type MOS tube MN7 and the grid electrode of the P-channel enhancement type MOS tube MP1 together, and the source electrode is connected with the VCC port; the drain electrode of the P-channel enhanced MOS tube MP1 is connected with a conversion resistor R 5 The grid electrode is connected with the grid electrode and the drain electrode of the P-channel enhancement type MOS tube MP0 and the drain electrode of the N-channel enhancement type MOS tube MN7, and the source electrode is connected with the internal power supply port VCC of the DCDC circuit; the switching resistor R 1 Is connected to the internal port SW 1 The other end is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube MN4 and the grid electrode of the N-channel enhancement type MOS tube MN 5; the switching resistor R 2 Is connected to the internal port SW 2 The other end is connected with the drain electrode of the N-channel enhancement type MOS tube MN5, the grid electrode and the source electrode of the N-channel enhancement type MOS tube MN6 and the grid electrode of the N-channel enhancement type MOS tube NM 7; the switching resistor R 5 One end of the zero crossing comparator is connected with the drain electrode of the P-channel enhancement type MOS tube MP1, the current outflow end of the current source IB0 and the inverting end of the zero crossing comparatorA power supply ground; the current inflow end of the current source IB0 is connected with the internal power supply end VCC of the DCDC circuit, and the current outflow end is connected with the drain electrode of the P-channel enhancement type MOS tube MP1 and the switching resistor R 5 And the opposite end of the zero-crossing comparator.
The invention also provides a control method related to the zero-crossing detection circuit with the self-adaptive delay compensation, which comprises the following steps:
sampling resistor R 0 Voltage V at both ends CS And V OUT Respectively connected with a conversion resistor R 3 、R 4 Wherein R is one end of 3 ＝R 4 If output port V OUT A current flows through the sampling resistor R 0 Voltage V at two ends CS And V OUT When there is a voltage difference, the current of the current source IB1 and the current source IB2 are equal, the current flowing through the P-channel enhancement type MOS tube MP2 and the current flowing through the P-channel enhancement type MOS tube MP3 are equal, and the current flowing through the P-channel enhancement type MOS tube MP4 is equal to the sampling resistor R 0 The voltage difference across the two ends divided by the switching resistance R 3 Or a switching resistor R 4 Let inductor current be I L The expression is as follows:
wherein V is CS And V OUT For sampling resistor R 0 Voltage across R 0 For sampling resistance value of resistor R 3 、R 6 Respectively the switching resistors R in the circuit 3 、R 6 Resistance value V of (V) ZC The current obtained by sampling the current sampling resistor is input into the resistor R 6 The resulting voltage;
the following formula can be obtained by combining the formula (1) and the formula (2):
i.e. internal node voltage V ZC And inductance L 0 Is a positive correlation of the current of (c).
The conventional zero-crossing detection circuit is connected to a fixed reference voltage at the inverting terminal of the zero-crossing comparator, and is used for detecting the internal node voltage V ZC Below this bias voltage the comparator toggles and the circuit internally considers the inductor current to be zero crossing at this time. However, in an actual circuit, there is a delay in both the current sampling circuit and the zero-crossing comparator, and this delay is related to the circuit structure and can be regarded as a fixed delay. In order to compensate the influence of the time delay on the zero crossing point, the conventional zero crossing detection circuit adds a fixed voltage to the fixed reference voltage connected with the inverting terminal of the zero crossing comparator so as to lead the zero crossing point to be advanced, thereby compensating the influence of the time delay on the zero crossing point. However, in the application of the buck-boost DCDC circuit, the gradient change range of the inductor current is very wide, and the compensation fixed voltage cannot be suitable for all application conditions, so that a voltage which changes along with the gradient change of the inductor current needs to be compensated, and the zero crossing point is better compensated when the gradient of the inductor current is at different values.
The invention considers the problem that the inductance L 0 The voltages at both ends, i.e. the internal node SW 1 、SW 2 The voltage is introduced into the zero-crossing detection circuit, so that the zero-crossing accuracy of the zero-crossing detection circuit is improved.
Internal node SW 1 、SW 2 Connected to the compensation circuit, the internal node SW 1 At the switching resistor R 1 Current is generated and mirrored to the N-channel enhancement MOS tube MN5 through the N-channel enhancement MOS tube MN4, and at the moment, the current and the switching resistor R of the N-channel enhancement MOS tube MN5 1 Is equal to the current of the internal node SW 2 At the switching resistor R 2 The current is generated on the N-channel enhancement MOS tube MN6, and the current flowing on the N-channel enhancement MOS tube MN6 is equal to the switching resistor R 2 The current flowing through the N-channel enhancement MOS transistor MN5 is subtracted from the current flowing through the N-channel enhancement MOS transistor, namely an internal node SW 2 At the switching resistor R 2 Subtracting the internal node SW from the generated current 1 At the switching resistor R 1 The generated current is mirrored to the P-channel enhancement type MOS tube MP1 tube through the N-channel enhancement type MOS tube MN7 and the P-channel enhancement type MOS tube MP0, and the current is the mostFinal inflow switching resistor R 5 Applying; when the inductance L 0 When the voltage across the inductor is large, the inductor current I L Changes rapidly, when the internal node SW 1 、SW 2 Respectively at the switching resistor R 1 、R 2 The difference between the currents generated is also large, and the large current finally mirrors to the P-channel enhancement MOS tube MP1 to flow into the conversion resistor R 5 Internal voltage node V is improved REF The zero-crossing comparator turns over before the zero-crossing point, and the hysteresis phenomenon of the turning-over point of the zero-crossing comparator caused by circuit delay is compensated; when the inductance L 0 When the voltage between the two ends is smaller, the inductance current I L The conversion is slower, the influence of the internal delay of the circuit on the zero crossing point is smaller, the compensation current flowing through the P-channel enhancement type MOS tube MP1 is smaller, and the overcompensation phenomenon is avoided;
flow-through switching resistor R 1 The current of (2) is I R1 Through the conversion resistor R 2 The current of (2) is I R2 The expression is as follows:
let N channel enhancement type MOS tube MN6 flow current I MN6 ，R 1 ＝R 2 Then:
and inductor current I L The slope of (c) is given by equation (7):
simultaneous equations (6) and (7) can be obtained:
the equation (8) can obtain that the compensation current slope is in direct proportion to the inductance current slope, when the inductance current slope is increased, the internal fixed delay influence duty ratio of the circuit is increased, and at the moment, the compensation current is increased, and the zero crossing hysteresis caused by delay is compensated;
in practical application, it is assumed that the delay of the current sampling circuit plus the delay of the zero comparator is T d The mirror proportion of the P-channel enhancement type MOS tube MP0 mirror image to the P-channel enhancement type MOS tube MP1 tube is 1: n; the channel current of the P-channel enhancement type MOS tube MP1 tube is I MP1 The voltage of the change of the non-inverting terminal of the zero-crossing comparator caused by time delay is V Td The voltage of the change of the inverting terminal of the zero-crossing comparator caused by the compensation circuit is V C ；
Combining equation (3) and equation (7) yields:
combining equation (6), we get:
let V C ＝V Td And R is 5 ＝R 6 The method comprises the following steps of:
delay T within the circuit according to equation (11) d When determining, the mirror image proportion N of the P-channel enhancement type MOS tube MP0 to the P-channel enhancement type MOS tube MP1 is adjusted to ensure that the voltage change V of the same-phase end of the zero-crossing comparator caused by delay Td Voltage change V at inverting terminal of zero-crossing comparator caused by compensation circuit C Equal, the mostEventually making zero crossing accurate.
The invention has the beneficial effects that: when the gradient of the inductor current is larger, the larger advance of the compensation current is larger, and the zero crossing point detected by the zero crossing comparator is more accurate under different gradients of the inductor current.
Drawings
Figure 1 is a zero crossing detection circuit with adaptive delay compensation for a DCDC buck-boost circuit according to the invention,
fig. 2 is a power stage DCDC circuit of the present invention.
Detailed Description
The invention will be further described with reference to the drawings and examples.
In order to overcome the defects of the prior art, the invention provides a zero-crossing detection circuit with self-adaptive delay compensation and a control method thereof. The technical scheme adopted for solving the technical problems is as follows:
the invention provides a zero-crossing detection circuit with self-adaptive delay compensation, which comprises a power level DCDC circuit and a current sampling circuit. The current sampling circuit samples the output V of the power stage DCDC circuit OUT End sampling resistor R 0 Two-end voltage, compensation circuit sampling power stage DCDC circuit inductance L with self-adaptive delay compensation 0 Two-terminal voltage SW 1 、SW 2 The final current sampling circuit and the compensation circuit convert the sampled voltage into current and then convert the current into voltage, and then output the voltage to the in-phase end and the anti-phase end of the zero-crossing comparator respectively, and the zero-crossing comparator outputs a comparison result.
The power stage DCDC circuit is composed of power switch MOS transistors MN0-MN3, an inductor L 0 Sampling resistor R 0 Load capacitance C 0 The composition is formed. The source electrode of the power switch MOS tube MN0 is connected with the internal port SW 1 Grid connection V of power switch MOS tube MN0 0 Terminal, power switch MOS tube MN0 drain electrode connects input port V IN And (3) an end. The source electrode of the power switch MOS tube MN1 is connected to the power ground, and the power switchMOS tube MN1 grid connection V 1 Terminal, power switch MOS tube MN0 drain electrode connects internal port SW 1 . The source electrode of the power switch MOS tube MN2 is connected to the power ground, and the grid electrode of the power switch MOS tube MN2 is connected with the V 2 Terminal, power switch MOS tube MN0 drain electrode connects internal port SW 2 . The source electrode of the power switch MOS tube MN3 is connected with the internal port SW 2 Grid connection V of power switch MOS tube MN3 3 End, output port V is connected to power switch MOS pipe MN3 drain OUT . The inductance L 0 One end is connected with the internal port SW 1 One end is connected with the internal port SW 2 . The load capacitance C 0 The upper polar plate is connected with the output port V OUT The lower polar plate is grounded. The sampling resistor R 0 A termination switching resistor R 3 One end of (2) is connected with the output port V OUT Conversion resistor R 4 Is provided.
The current sampling circuit is composed of P-channel enhancement type MOS transistors MP2-MP4 and a conversion resistor R 3 、R 4 、R 6 The current sources IB1, IB 2. The drain electrode and the grid electrode of the P-channel enhancement type MOS tube MP2 are connected with the current inflow end of the current source IB1 and the grid electrode of the P-channel enhancement type MOS tube MP3, and the source electrode is connected with the conversion resistor R 3 One end and the source electrode of the P channel enhancement type MOS tube MP 4. The drain electrode of the P-channel enhancement type MOS tube MP3 is connected with the grid electrode of the P-channel enhancement type MOS tube MP4 and the current inflow end of the current source IB2, the grid electrode is connected with the grid electrode and the drain electrode of the P-channel enhancement type MOS tube MP2 and the current inflow end, and the source electrode is connected with the conversion resistor R 4 One end of the P-channel enhancement type MOS tube MP4 is connected with a switching resistor R by a drain electrode 6 The grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube MP3 and the current inflow end of the current source IB2, and the source electrode is connected with the conversion resistor R 3 And the source of the P-channel enhancement MOS transistor MP 2. The switching resistor R 3 One end is connected with a sampling resistor R 0 One end is connected with the source electrode of the P-channel enhancement type MOS tube MP4 and the source electrode of the P-channel enhancement type MOS tube MP 2. The switching resistor R 4 One end is connected with the output port V OUT Sampling resistor R 0 One end of the transistor is connected with the source electrode of the P-channel enhancement type MOS tube MP 3. The transferExchange resistor R 6 One end is connected with the same-phase end of the zero-crossing comparator and the drain electrode of the P-channel enhancement type MOS tube MP4, and the other end is connected with the power supply ground. The current inflow end of the current source IB1 is connected with the drain electrode and the grid electrode of the P-channel enhancement type MOS tube MP2 and the grid electrode of the P-channel enhancement type MOS tube MP3, and the current outflow end is connected with the power ground. The current inflow end of the current source IB2 is connected with the grid electrode of the P-channel enhancement type MOS tube MP4 and the drain electrode of the P-channel enhancement type MOS tube MP3, and the current outflow end is connected with the power ground.
The non-inverting terminal of the zero-crossing comparator is connected with a switching resistor R 6 One end of the P channel enhancement type MOS tube MP4 and the drain electrode, the reverse phase end is connected with the conversion resistor R 5 The current outflow end of the current source IB0 and the drain electrode of the P-channel enhancement type MOS tube MP1 are connected with the output port ZC of the zero-crossing detection circuit.
Compensation circuit with self-adaptive delay compensation is composed of N-channel enhancement type MOS tubes MN4-MN7, P-channel enhancement type MOS tubes MP0 and MP1 and conversion resistor R 1 、R 2 、R 5 The current source IB 0. The grid electrode and the drain electrode of the N-channel enhanced MOS tube MN4 are connected with a conversion resistor R 1 And the source electrode of the N-channel enhanced MOS tube MP5 is connected with the power ground. The drain electrode of the N-channel enhanced MOS tube MN5 is connected with a conversion resistor R 2 Gate and drain of N-channel enhancement type MOS transistor MN6 and gate of N-channel enhancement type MOS transistor MN7, gate connected to gate and drain of N-channel enhancement type MOS transistor MN4 and switching resistor R 1 The source is connected to the power ground. The drain electrode and the grid electrode of the N-channel enhanced MOS tube MN6 are connected with the conversion resistor R together 2 And the source electrode of the N channel enhancement type MOS tube MN7 is connected with the power supply ground. The drain electrode of the N-channel enhancement type MOS tube MN7 is connected with the grid electrode and the drain electrode of the P-channel enhancement type MOS tube MP0 and the grid electrode of the P-channel enhancement type MOS tube MP1, and the grid electrode is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube MN6 and the conversion resistor R 2 The source is connected to the power ground. The drain electrode and the grid electrode of the P-channel enhancement type MOS tube MP0 are connected with the drain electrode of the N-channel enhancement type MOS tube MN7 and the grid electrode of the P-channel enhancement type MOS tube MP1 together, and the source electrode is connected with the VCC port. The drain electrode of the P-channel enhanced MOS tube MP1 is connected with a conversion resistor R 5 The grid is connected with the grid and the drain of the P-channel enhancement MOS tube MP0 and the drain of the N-channel enhancement MOS tube MN7, and the source is connected with the internal power supply port VCC of the DCDC circuit. The switching resistor R 1 Terminating in an internal port SW 1 One end is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube MN4 and the grid electrode of the N-channel enhancement type MOS tube MN 5. The switching resistor R 2 Terminating in an internal port SW 2 One end is connected with the drain electrode of the N-channel enhancement type MOS tube MN5, the grid electrode and the source electrode of the N-channel enhancement type MOS tube MN6 and the grid electrode of the N-channel enhancement type MOS tube NM 7. The switching resistor R 5 One end is connected with the drain electrode of the P-channel enhancement type MOS tube MP1, the current outflow end of the current source IB0 and the inverting end of the zero-crossing comparator, and the other end is connected with the power ground. The current inflow end of the current source IB0 is connected with the internal power supply end VCC of the DCDC circuit, and the current outflow end is connected with the drain electrode of the P-channel enhancement type MOS tube MP1 and the switching resistor R 5 And the opposite end of the zero-crossing comparator.
The control method of the zero-crossing detection circuit with the self-adaptive delay compensation comprises the following steps: sampling resistor R 0 Voltage V at both ends CS And V OUT Respectively connected with a conversion resistor R 3 、R 4 Wherein R is one end of 3 ＝R 4 If output port V OUT When current flows, the voltage V at two ends of the sampling resistor CS And V OUT When there is a voltage difference, the current of the current source IB1 and the current source IB2 are equal, the current flowing through the P-channel enhancement type MOS tube MP2 and the P-channel enhancement type MOS tube MP3 are equal, and the current flowing through the P-channel enhancement type MOS tube MP4 is equal to the sampling resistor R 0 The voltage difference across the two ends divided by the switching resistance R 3 Or a switching resistor R 4 Let inductor current be I L The expression is as follows:
wherein V is CS And V OUT For sampling resistor R 0 Voltage across R 0 For sampling resistance value of resistor R 3 、R 6 Respectively the switching resistors R in the circuit 3 、R 6 Is a resistance value of (a). V (V) ZC The current obtained by sampling the current sampling resistor is input into the resistor R 6 And the resulting voltage.
The combination of the formula (1) and the formula (2) can obtain the following formula
Internal node voltage V ZC And inductance L 0 Is a positive correlation of the current of (c).
The conventional zero-crossing detection circuit is connected to a fixed reference voltage at the inverting terminal of the zero-crossing comparator, and is used for detecting the internal node voltage V ZC Below this bias voltage the comparator toggles and the circuit internally considers the inductor current to be zero crossing at this time. However, in an actual circuit, there is a delay in both the current sampling circuit and the zero-crossing comparator, and this delay is related to the circuit structure and can be regarded as a fixed delay. In order to compensate the influence of the time delay on the zero crossing point, the conventional zero crossing detection circuit adds a fixed voltage to the fixed reference voltage connected with the inverting terminal of the zero crossing comparator so as to lead the zero crossing point to be advanced, thereby compensating the influence of the time delay on the zero crossing point. However, in the application of the buck-boost DCDC circuit, the gradient change range of the inductor current is very wide, and the compensation fixed voltage cannot be suitable for all application conditions, so that a voltage which changes along with the gradient change of the inductor current needs to be compensated, and the zero crossing point is better compensated when the gradient of the inductor current is at different values.
The invention considers the problem that the inductance L 0 The voltages at both ends, i.e. the internal node SW 1 、SW 2 The voltage is introduced into the zero-crossing detection circuit, so that the zero-crossing accuracy of the zero-crossing detection circuit is improved.
Internal node SW 1 、SW 2 Is connected to the compensation circuit with the self-adaptive delay compensation proposed by the invention,internal node SW 1 At the switching resistor R 1 Current is generated and mirrored to the N-channel enhancement MOS tube MN5 through the N-channel enhancement MOS tube MN4, and at the moment, the current and the switching resistor R of the N-channel enhancement MOS tube MN5 1 Is equal to the current of the internal node SW 2 At the switching resistor R 2 The current is generated on the N-channel enhancement MOS tube MN6, and the current flowing on the N-channel enhancement MOS tube MN6 is equal to the conversion resistor R 2 The current flowing through the N-channel enhancement MOS transistor MN5 is subtracted from the current flowing through the N-channel enhancement MOS transistor, namely an internal node SW 2 At the switching resistor R 2 Subtracting the internal node SW from the generated current 1 At the switching resistor R 1 The generated current is mirrored to the P-channel enhanced MOS tube MP1 tube through the N-channel enhanced MOS tube MN7 and the P-channel enhanced MOS tube MP0 and finally flows into the conversion resistor R 5 And (3) upper part. When the voltage across the inductor L0 is large, the inductor current IL changes rapidly, and the internal node SW 1 、SW 2 Respectively at the switching resistor R 1 、R 2 The difference between the currents generated is also large, and the large current finally mirrors to the P-channel enhancement MOS tube MP1 to flow into the conversion resistor R 5 Internal voltage node V is improved REF The zero-crossing comparator is enabled to turn over before the zero-crossing point, and the hysteresis phenomenon of the turning-over point of the zero-crossing comparator caused by circuit delay is compensated. When the inductance L 0 When the voltage between the two ends is smaller, the inductance current I L The conversion is slower, the influence of the internal delay of the circuit on the zero crossing point is smaller, and the compensation current flowing through the P-channel enhancement type MOS tube MP1 is smaller, so that the overcompensation phenomenon is avoided.
Flow-through switching resistor R 1 The current of (2) is I R1 Through the conversion resistor R 2 The current of (2) is I R2 Is expressed as follows
Let N channel enhancement type MOS tube MN6 flow current I MN6 ，R 1 ＝R 2 Then
And inductor current I L The slope of (2) can be derived from equation (7)
The simultaneous formulas (6) (7) can be obtained
The equation (8) shows that the compensation current slope is in direct proportion to the inductance current slope, when the inductance current slope is increased, the fixed delay influence duty ratio in the circuit is increased, and at the moment, the compensation current is increased, and the zero crossing hysteresis phenomenon caused by delay is compensated.
In practical application, it is assumed that the delay of the current sampling circuit plus the delay of the zero comparator is T d The mirror proportion of the P-channel enhancement type MOS tube MP0 mirror image to the P-channel enhancement type MOS tube MP1 tube is 1: n. Let the channel current of the P-channel enhancement type MOS tube MP1 tube be I MP1 . Setting the voltage of the change of the non-inverting terminal of the zero-crossing comparator caused by time delay as V Td The voltage of the change of the inverting terminal of the zero-crossing comparator caused by the compensation circuit provided by the invention is V C 。
Combining equation (3) and equation (7), one can obtain:
combining equation (6), we can get:
let V C ＝V Td And R is 5 ＝R 6 The method can obtain:
delay T within the circuit according to equation (11) d When determining, the mirror image proportion N of the P-channel enhancement type MOS tube MP0 to the P-channel enhancement type MOS tube MP1 can be adjusted to ensure that the voltage change V of the same-phase end of the zero-crossing comparator caused by delay Td Voltage change V at inverting terminal of zero-crossing comparator caused by compensation circuit C And the zero crossing points are accurate finally.
The invention relates the compensation current of zero crossing, which can be called as the lead of zero crossing, to the slope of the inductance current, when the falling slope of the inductance current is larger, the lead of the compensation current is larger, and the zero crossing detected by the zero crossing comparator is more accurate under different slopes of the inductance current.
In summary, the invention provides a zero-crossing detection circuit with self-adaptive compensation, which can finally compensate the zero-crossing detection circuit under different input and output voltages and different inductance current slopes, so that the zero-crossing detection is more accurate, and the efficiency of the circuit in a light load mode DCM is improved. Compared with the prior zero-crossing detection circuit, the compensation circuit provided by the invention is self-adaptive according to the slope of the inductance current, so that the zero-crossing accuracy of the circuit working under different input and output voltages is improved, and the whole DCDC step-up voltage is safer and more reliable.
Claims (5)
1. The utility model provides a zero crossing detection circuit with self-adaptation time delay compensation, includes power level DCDC circuit, current sampling circuit, self-adaptation time delay compensation's compensating circuit and zero-crossing comparator, its characterized in that:
the current sampling circuit samples the output V of the power stage DCDC circuit OUT End sampling resistor R 0 The compensation circuit samples the voltage at two ends and the power level DCDC circuit inductance L 0 Both ends are provided withThe voltages at the internal ports SW1, SW2 are denoted as V respectively SW1 、V SW2 The final current sampling circuit and the compensation circuit convert the sampled voltage into current and then convert the current into voltage, and then output the voltage to the in-phase end and the anti-phase end of the zero-crossing comparator respectively, and the zero-crossing comparator outputs a comparison result;
the current sampling circuit comprises P-channel enhancement type MOS transistors MP2-MP4 and a conversion resistor R 3 、R 4 、R 6 Current sources IB1 and IB2; the drain electrode and the grid electrode of the P-channel enhancement type MOS tube MP2 are connected with the current inflow end of the current source IB1 and the grid electrode of the P-channel enhancement type MOS tube MP3, and the source electrode is connected with the conversion resistor R 3 One end and the source electrode of the P channel enhancement type MOS tube MP 4; the drain electrode of the P-channel enhancement type MOS tube MP3 is connected with the grid electrode of the P-channel enhancement type MOS tube MP4 and the current inflow end of the current source IB2, the grid electrode is connected with the grid electrode and the drain electrode of the P-channel enhancement type MOS tube MP2 and the current inflow end, and the source electrode is connected with the conversion resistor R 4 One end; the drain electrode of the P-channel enhanced MOS tube MP4 is connected with a conversion resistor R 6 The grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube MP3 and the current inflow end of the current source IB2, and the source electrode is connected with the conversion resistor R 3 A source electrode of the P channel enhancement MOS tube MP2 and one end of the P channel enhancement MOS tube; the switching resistor R 3 One end is connected with a sampling resistor R 0 One end is connected with the source electrode of the P-channel enhancement type MOS tube MP4 and the source electrode of the P-channel enhancement type MOS tube MP 2; the switching resistor R 4 One end of (a) is connected with the output port V OUT Sampling resistor R 0 The other end of the transistor is connected with the source electrode of the P-channel enhancement type MOS tube MP 3; the switching resistor R 6 One end of the zero-crossing comparator is connected with the same-phase end of the zero-crossing comparator and the drain electrode of the P-channel enhancement type MOS tube MP4, and the other end of the zero-crossing comparator is connected with the power supply ground; the current inflow end of the current source IB1 is connected with the drain electrode and the grid electrode of the P-channel enhancement type MOS tube MP2 and the grid electrode of the P-channel enhancement type MOS tube MP3, and the current outflow end is connected with the power supply ground; the current inflow end of the current source IB2 is connected with the grid electrode of the P-channel enhancement type MOS tube MP4 and the drain electrode of the P-channel enhancement type MOS tube MP3, and the current outflow end is connected with the power ground.
2. The zero crossing detection circuit with adaptive delay compensation of claim 1, wherein:
the power stage DCDC circuit comprises power switch MOS transistors MN0-MN3 and an inductor L 0 Sampling resistor R 0 And a load capacitance C 0 The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the power switch MOS tube MN0 is connected with the internal port SW 1 Grid connection V of power switch MOS tube MN0 0 Terminal, power switch MOS tube MN0 drain electrode connects input port V IN The source electrode of the power switch MOS tube MN1 is connected to the power ground, and the grid electrode of the power switch MOS tube MN1 is connected with the V 1 Terminal, power switch MOS tube MN0 drain electrode connects internal port SW 1 The source electrode of the power switch MOS tube MN2 is connected to the power ground, and the grid electrode of the power switch MOS tube MN2 is connected with the V 2 Terminal, power switch MOS tube MN0 drain electrode connects internal port SW 2 Source electrode of power switch MOS tube MN3 is connected with internal port SW 2 Grid connection V of power switch MOS tube MN3 3 End, output port V is connected to power switch MOS pipe MN3 drain OUT The method comprises the steps of carrying out a first treatment on the surface of the The inductance L 0 Is connected to the internal port SW 1 The other end is connected with the internal port SW 2 The load capacitance C 0 The upper polar plate is connected with the output port V OUT The lower polar plate is grounded, and the sampling resistor R 0 Is connected with the switching resistor R 3 One end of (a) is connected with the output port V OUT Conversion resistor R 4 Is provided.
3. The zero crossing detection circuit with adaptive delay compensation of claim 1, wherein:
the non-inverting terminal of the zero-crossing comparator is connected with a switching resistor R 6 One end of the P channel enhancement type MOS tube MP4 and the drain electrode, the reverse phase end is connected with the conversion resistor R 5 One end of the switching resistor R 5 One end of the resistor R is connected with the current outflow end of the current source IB0 and the drain electrode of the P-channel enhancement MOS tube MP1 6 And a switching resistor R 5 The other end of the zero crossing comparator is grounded, and the output end of the zero crossing comparator is connected with an output port ZC of the zero crossing detection circuit.
4. The zero crossing detection circuit with adaptive delay compensation of claim 1, wherein:
the compensation circuit is composed of N-channel enhancement type MOS tubes MN4-MN7, P-channel enhancement type MOS tubes MP0 and MP1 and a conversion resistor R 1 、R 2 、R 5 A current source IB 0; the grid electrode and the drain electrode of the N-channel enhanced MOS tube MN4 are connected with a conversion resistor R 1 The source electrode of the N-channel enhancement MOS tube MP5 is connected with the power supply ground; the drain electrode of the N-channel enhanced MOS tube MN5 is connected with a conversion resistor R 2 Gate and drain of N-channel enhancement type MOS transistor MN6 and gate of N-channel enhancement type MOS transistor MN7, gate connected to gate and drain of N-channel enhancement type MOS transistor MN4 and switching resistor R 1 The source electrode is connected with the power ground; the drain electrode and the grid electrode of the N-channel enhanced MOS tube MN6 are connected with the conversion resistor R together 2 The source electrode of the N channel enhancement type MOS tube MN7 is connected with the power supply ground; the drain electrode of the N-channel enhancement type MOS tube MN7 is connected with the grid electrode and the drain electrode of the P-channel enhancement type MOS tube MP0 and the grid electrode of the P-channel enhancement type MOS tube MP1, and the grid electrode is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube MN6 and the conversion resistor R 2 The source electrode is connected with the power ground; the drain electrode and the grid electrode of the P-channel enhancement type MOS tube MP0 are connected with the drain electrode of the N-channel enhancement type MOS tube MN7 and the grid electrode of the P-channel enhancement type MOS tube MP1 together, and the source electrode is connected with the VCC port; the drain electrode of the P-channel enhanced MOS tube MP1 is connected with a conversion resistor R 5 The grid electrode is connected with the grid electrode and the drain electrode of the P-channel enhancement type MOS tube MP0 and the drain electrode of the N-channel enhancement type MOS tube MN7, and the source electrode is connected with the internal power supply port VCC of the DCDC circuit; the switching resistor R 1 Is connected to the internal port SW 1 The other end is connected with the grid electrode and the drain electrode of the N-channel enhancement type MOS tube MN4 and the grid electrode of the N-channel enhancement type MOS tube MN 5; the switching resistor R 2 Is connected to the internal port SW 2 The other end is connected with the drain electrode of the N-channel enhancement type MOS tube MN5, the grid electrode and the source electrode of the N-channel enhancement type MOS tube MN6 and the grid electrode of the N-channel enhancement type MOS tube NM 7; the conversion is performedResistor R 5 One end of the zero crossing comparator is connected with the drain electrode of the P channel enhancement type MOS tube MP1, the current outflow end of the current source IB0 and the reverse end of the zero crossing comparator, and the other end of the zero crossing comparator is connected with the power supply ground; the current inflow end of the current source IB0 is connected with the internal power supply end VCC of the DCDC circuit, and the current outflow end is connected with the drain electrode of the P-channel enhancement type MOS tube MP1 and the switching resistor R 5 And the opposite end of the zero-crossing comparator.
5. A control method using the zero-crossing detection circuit with adaptive delay compensation of claim 1, characterized by comprising the steps of:
sampling resistor R 0 Voltage V at both ends CS And V OUT Respectively connected with a conversion resistor R 3 、R 4 Wherein R is one end of 3 ＝R 4 If output port V OUT A current flows through the sampling resistor R 0 Voltage V at two ends CS And V OUT When there is a voltage difference, the current of the current source IB1 and the current source IB2 are equal, the current flowing through the P-channel enhancement type MOS tube MP2 and the current flowing through the P-channel enhancement type MOS tube MP3 are equal, and the current flowing through the P-channel enhancement type MOS tube MP4 is equal to the sampling resistor R 0 The voltage difference across the two ends divided by the switching resistance R 3 Or a switching resistor R 4 Let inductor current be I L The expression is as follows:
wherein V is CS And V OUT For sampling resistor R 0 Voltage across R 0 For sampling resistance value of resistor R 3 、R 6 Respectively the switching resistors R in the circuit 3 、R 6 Resistance value V of (V) ZC The current obtained by sampling the current sampling resistor is input into the resistor R 6 The resulting voltage;
the following formula can be obtained by combining the formula (1) and the formula (2):
i.e. internal node voltage V ZC And inductance L 0 Is a positive correlation of the current of (a);
internal port SW 1 、SW 2 Connected to the compensation circuit, internal ports SW 1 At the switching resistor R 1 Current is generated and mirrored to the N-channel enhancement MOS tube MN5 through the N-channel enhancement MOS tube MN4, and at the moment, the current and the switching resistor R of the N-channel enhancement MOS tube MN5 1 Is equal to the current of the internal port SW 2 At the switching resistor R 2 The current is generated on the N-channel enhancement MOS tube MN6, and the current flowing on the N-channel enhancement MOS tube MN6 is equal to the switching resistor R 2 The current flowing through the N-channel enhancement MOS transistor MN5 is subtracted from the current flowing through the N-channel enhancement MOS transistor, namely an internal node SW 2 At the switching resistor R 2 The resulting current minus the internal port SW 1 At the switching resistor R 1 The generated current is mirrored to the P-channel enhanced MOS tube MP1 tube through the N-channel enhanced MOS tube MN7 and the P-channel enhanced MOS tube MP0 and finally flows into the transistor
Exchange resistor R 5 Applying;
through the switching resistor R 1 The current of (2) is I R1 Through the conversion resistor R 2 The current of (2) is I R2 The expression is as follows:
the current flowing through the N-channel enhanced MOS tube MN6 is I MN6 ，R 1 ＝R 2 Then:
and inductor current I L The slope of (c) is given by equation (7):
simultaneous equations (6) and (7) can be obtained:
the equation (8) can obtain that the compensation current slope is in direct proportion to the inductance current slope, when the inductance current slope is increased, the internal fixed delay influence duty ratio of the circuit is increased, and at the moment, the compensation current is increased, and the zero crossing hysteresis caused by delay is compensated;
the delay of the delay plus zero-crossing comparator of the current sampling circuit is T d The mirror proportion of the P-channel enhancement type MOS tube MP0 mirror image to the P-channel enhancement type MOS tube MP1 tube is 1: n; the channel current of the P-channel enhancement type MOS tube MP1 tube is I MP1 The voltage of the change of the non-inverting terminal of the zero-crossing comparator caused by time delay is V Td The voltage of the change of the inverting terminal of the zero-crossing comparator caused by the compensation circuit is V C ；
Combining equation (3) and equation (7) yields:
combining equation (6), we get:
let V C ＝V Td And R is 5 ＝R 6 The method comprises the following steps of:
delay T within the circuit according to equation (11) d When determining, the mirror image proportion N of the P-channel enhancement type MOS tube MP0 to the P-channel enhancement type MOS tube MP1 is adjusted to ensure that the voltage change V of the same-phase end of the zero-crossing comparator caused by delay Td Voltage change V at inverting terminal of zero-crossing comparator caused by compensation circuit C And the zero crossing points are accurate finally.
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| CN103760408A (en) * | 2014-01-26 | 2014-04-30 | 矽力杰半导体技术(杭州)有限公司 | Zero cross detection circuit |
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| CN103675426A (en) * | 2013-12-24 | 2014-03-26 | 矽力杰半导体技术(杭州)有限公司 | Inductive current zero-crossing detection method, circuit and switch power supply with circuit |
| CN103760408A (en) * | 2014-01-26 | 2014-04-30 | 矽力杰半导体技术(杭州)有限公司 | Zero cross detection circuit |
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