CN103618455A - Method for reducing steady state error of output voltage of single-inductor double-output converter and circuit - Google Patents

Abstract

A method for reducing the steady-state error of the output voltage of a single-inductance double-output converter. When the main loop error amplifier adopts no large capacitance compensation, a current sampling and holding circuit is added in the main loop, and the output DC level V _dc is related to the slope voltage V _ramp1 is superimposed and summed to generate a new ramp voltage V _ramp2 , which is superimposed and summed with the sampled inductor current signal and then used as the input voltage V _sense of the non-inverting input terminal of the comparator. At the same time, the output V _c of the error amplifier is superimposed on a DC level V _dc0 The input signal V _e of the inverting terminal of the comparator is obtained, and V _e is also another input signal of the current sampling and holding circuit. At this time, the main-stage switch control signal output by the comparator can give enough charging time for the converter inductance, thereby reducing The steady-state error of the converter output voltage.

Description

A method and circuit for reducing output voltage steady-state error of single-inductance dual-output converter

technical field

The invention relates to a single-inductance dual-output (SIDO) step-down switching power supply converter, in particular to a method and circuit for reducing the steady-state error of the output voltage of the single-inductance dual-output converter.

Background technique

In a SIDO circuit, it is generally hoped that the circuit can minimize the steady-state error of the output voltage while responding quickly to sudden load changes. In the primary control loop of the traditional SIDO step-down switching power supply converter, because the error amplifier uses PI compensation with a large capacitor, as shown in Figure 1, the transient response of the circuit is very slow. Using a low-gain error amplifier without large capacitor compensation can bring two advantages: one is fast transient response; the other is that a large capacitor is reduced, and the chip area will be greatly reduced. But considering the stability of the system, the gain of the error amplifier must be reduced. A low-gain error amplifier will increase the steady-state error of the output voltage. The main reasons are as follows: First, when the load current increases, the gain of the main loop is small, and the drop in the output voltage cannot be detected sensitively; When the load current increases, the non-inverting input signal V _sense of the main loop comparator increases, resulting in a decrease in the duty cycle of the main switch control signal. Due to the low gain of the error amplifier, it is impossible to generate enough output voltage to adjust the duty cycle. This results in a relatively large circuit output voltage steady-state error.

Contents of the invention

The present invention aims at the defect that a large output voltage steady-state error is caused by using a low-gain error amplifier without large-capacity compensation in the SIDO primary control loop. The method and the circuit for outputting the voltage steady-state error of the output converter add a control circuit for reducing the steady-state error in the main loop, which greatly improves the accuracy of the output voltage.

The specific technical scheme adopted by the present invention is as follows: a method for reducing the steady-state error of the output voltage of a single-inductance dual-output converter. The sum of the load currents of the two circuits, that is, the average value I _L of the total current flowing through the inductor L of the converter. The secondary loop adopts the voltage mode to determine the distribution of the inductor current I _L among the two outputs. The main loop is equipped with an error amplifier, a comparator, Trigger and drive and dead zone control circuit, the error amplifier input reference voltage V _REF1 at the non-inverting terminal, input 0.4×(V _o1 +V _o2 ) at the inverting terminal, V ₀₁ and V ₀₂ are the two output voltages of the converter respectively, the error The output V _c of the amplifier is connected to the inverting input terminal of the comparator, the ramp voltage V _ramp1 and the sampled inductor current I _L R _S signal are superimposed and summed and then connected to the non-inverting input terminal of the comparator, the output of the comparator and the clock signal are respectively input to the trigger The output of the flip-flop is connected to the input of the drive and dead zone control circuit, and the output signal PG of the drive and dead zone control circuit controls the on-off of the main stage switch. It is characterized in that: when the main loop error amplifier adopts a low gain error without large capacitor compensation When the amplifier is used, a current sampling and holding circuit is added in the main loop. One input signal of the current sampling and holding circuit is the sampled inductor current I _L R _S signal, and the DC level V _dc output by the current sampling and holding circuit is superimposed on the ramp voltage V _ramp1 After the summation, a new ramp voltage V _ramp2 is generated, which is superimposed and summed with the sampled inductor current I _{L RS} signal, and then used as the input voltage V _sense of the non-inverting input terminal of the comparator, and at the same time, the output V _c of the error amplifier is superimposed on a DC level V _{dc0 gets} the input signal V _e of the inverting terminal _of the comparator, which is also another input signal of the current sampling and holding circuit _. The maximum value V _p of the input signal V _sense at the non-inverting terminal of the comparator under load, the value of V _p varies with the load, and reaches the maximum value when the converter is fully loaded, V _sense = V _p -V _c , and the output signal of the comparator passes through The trigger and the primary switch control signal PG output by the drive and dead zone control circuit can give the converter inductance enough charging time, thereby reducing the steady-state error of the converter output voltage;

The current sampling and holding circuit added in the above method includes the control signal _V1 and _V2 generation circuit, the D flip-flop enable signal EN generation circuit, the inductor current sampling and holding gate signal _S1 and _S2 generation circuit, the DC level V _dc A generating circuit and a circuit that generates a new ramp voltage V _ramp2 after superimposing the DC voltage V _dc on the ramp voltage V _ramp1 and summing;

短接并连接与非门NAND1的一个输入端，与非门NAND1的另一个输入端连接时钟信号CLK，与非门NAND1的输出端连接触发器D0的时钟端，触发器D0的输出端Q分别连接触发器D1、D2的使能端，触发器D1的输入端D与输出端

短接并连接触发器D2的时钟端，触发器D1的输出端Q空接，与非门NAND2的一个输入端连接触发器D2的输入端D和输出端

，与非门NAND2的另一个输入端连接时钟信号CLK，与非门NAND2的输出端连接触发器D1的时钟端，触发器D2的输出端Q连接触发器D3的使能端并作为控制信号V₂的输出端，触发器D3的时钟端连接时钟信号CLK，触发器D3的输入端D与输出端

短接，触发器D3的输出端Q为控制信号V₁的输出端；The control signal _V1 and _V2 generation circuit includes four D flip-flops D0, D1, D2, D3, two NAND gates NAND1, NAND2, the input terminal D and the output terminal of the flip-flop D0

Short-circuit and connect one input terminal of the NAND gate NAND1, the other input terminal of the NAND gate NAND1 is connected to the clock signal CLK, the output terminal of the NAND gate NAND1 is connected to the clock terminal of the flip-flop D0, and the output terminals Q of the flip-flop D0 are respectively Connect the enable terminals of flip-flops D1 and D2, the input terminal D and output terminal of trigger D1

Short-circuit and connect the clock terminal of flip-flop D2, the output Q of flip-flop D1 is open, and one input of NAND gate NAND2 is connected to the input D and output of flip-flop D2

, the other input terminal of the NAND gate NAND2 is connected to the clock signal CLK, the output terminal of the NAND gate NAND2 is connected to the clock terminal of the flip-flop D1, and the output terminal Q of the flip-flop D2 is connected to the enabling terminal of the flip-flop D3 as the control signal V ₂ , the clock terminal of flip-flop D3 is connected to the clock signal CLK, and the input terminal D of flip-flop D3 is connected to the output terminal

Short circuit, the output terminal Q of the trigger D3 is the output terminal of the control signal _V1 ;

The D flip-flop enabling signal EN generation circuit includes two comparators COMP1, COMP2 and a NOR gate, the non-inverting terminals of the comparators COMP1 and COMP2 are connected to the voltage signals V _H and V _L respectively, and the inverting terminals of the comparators COMP1 and COMP2 Interconnect and connect the two output voltage differences V ₀₁ -V ₀₂ of the converter, V _H and V _L are both selected as (V _o1 -V _o2 )×(1±2%), and the outputs of the comparators COMP1 and COMP2 are respectively connected to The two input terminals of the NOR gate, and the output terminal of the NOR gate generate the enable signal EN and connect to the enable terminal of the flip-flop D0 in the control signal _V1 and _V2 generation circuit;

The inductance current sampling and holding strobe signal _S1 and _S2 generation circuit includes two OR gates OR1, OR2, AND gate AND, NOT gate NOT, and the two input terminals of OR gate OR1 are respectively connected to the main switch control signal PG and the control signal V ₂ , the output of the OR gate OR1 is connected to one input terminal of the AND gate AND, the other input terminal of the AND gate AND is connected to the control signal V ₁ , the output of the AND gate AND is connected to one input terminal of the OR gate OR2, and the other input terminal of the OR gate OR2 One input terminal is connected to the enable signal EN, the output of the OR gate OR2 is connected to the input terminal of the NOT gate and used as the output terminal of the strobe signal _S1 , and the output terminal of the NOT gate is the output terminal of the strobe signal _S2 ;

The DC level V _dc generation circuit includes control switches K ₁ , K ₂ , K ₃ , capacitors C ₁ , C ₂ , operational amplifiers, and buffers. One end of the control switch K ₁ is connected to the inductor current I _{L RS} signal, and the control switch K ₁ The other end of the capacitor _C1 is connected to one end of the capacitor C1 and grounded through the control switch _K2 , the other end of the capacitor _C1 is connected to the inverting terminal of the operational amplifier, one end of the capacitor _C2 and one end of the control switch _K3 , and the capacitor _C2 and the control The other end of the switch K ₃ is connected to the output end of the operational amplifier and the input end of the buffer, the non-inverting end of the operational amplifier is grounded, and the control ends of the control switches K ₁ , K ₂ , and K ₃ are respectively connected to the strobe signals S ₁ , S ₂ , S ₁ , connected to the output of the buffer, the signal V _e and the ramp voltage V _ramp1 are superimposed and summed to generate a DC level V _dc output;

The circuit for generating a new ramp voltage V _ramp2 after superimposing the DC voltage V _dc on the ramp voltage V _ramp1 includes a current source I, NMOS transistors M _N1 and M _N2 , PMOS transistors _MP1 and M _P2 , and control switches K4 and K5 and capacitor C3, the positive end of the current source I is connected to the power supply V _dd , the negative end of the current source I is connected to the drain and gate of the NMOS transistor M _N1 and the gate of the NMOS transistor M _N2 , and the NMOS transistors M _N1 and M _N2 The source is grounded, the drain of the NMOS transistor M _N2 is connected to the drain and gate of the PMOS transistor _MP1 and the gate of the PMOS transistor _MP2 , the sources of the PMOS transistors _MP1 and _MP2 are connected to the power supply _Vdd , and the PMOS transistor M The drain of _P2 is connected to one end of switch K4, the other end of switch K4 is connected to one end of switch K5 and one end of capacitor C3 as the output end of the new ramp voltage signal V _ramp2 , the other end of switch K5 is connected to the other end of capacitor C3 Connect and connect the DC level V _dc , the control terminals of the switches K5 and K4 are respectively connected to the clock control signal CLK and the inverse signal of CLK

Advantage of the present invention and remarkable effect:

The present invention aims at the defect of large output voltage steady-state error caused by adopting a low-gain error amplifier without large capacitance compensation in the SIDO primary control loop, and adds an inductor current sampling and holding circuit to compensate the DC deviation of the output voltage. The steady-state error of the output voltage is reduced, and the precision of the output voltage is improved.

Description of drawings

Figure 1 is a schematic diagram of a traditional SIDO circuit;

Fig. 2 is the schematic diagram of the entire SIDO circuit after improvement;

Fig. 3a is the ramp voltage V _ramp1 waveform without superimposed DC voltage V _dc and the ramp voltage V _ramp2 waveform after superimposing V _dc ;

Figure 3b defines the peak value V _p of the comparator non-inverting input signal V _sense when the input signal V _e at the inverting end of the comparator is at full load;

Fig. 4 is the specific circuit inside the current sampling and holding circuit module and the generation circuit of the ramp signal V _ramp2 ;

FIG. 5 is a waveform diagram of each signal in the current sampling and holding circuit module.

Detailed ways

Figure 1 is a schematic diagram of a traditional SIDO circuit. The control loop of the circuit is divided into a main loop and a secondary loop. The main loop adopts the peak current mode to determine the sum of the load currents of the two circuits (that is, the total current flowing through the inductor), and the secondary loop adopts the voltage mode to determine the distribution of the inductor current in the two circuits. In order to avoid sub-harmonic oscillation when the duty cycle is greater than 50%, the voltage corresponding to the detected inductor current needs to be superimposed with a ramp voltage V _ramp1 . The main loop adopts an error amplifier with large capacitance compensation, the transient response speed of the circuit is slow, and the large capacitance occupies a large chip area. If the error amplifier adopts a low-gain error amplifier without large capacitance compensation (remove the dotted box capacitors C _P1 and R _P1 at the output end of the error amplifier in Figure 1), although it can bring two advantages: one is fast transient response; the other is With the reduction of a large capacitor, the chip area will be greatly reduced. But considering the stability of the system, the gain of the error amplifier must be reduced. And the low-gain error amplifier will make the steady-state error of the output voltage larger.

Fig. 2 is a functional block diagram of the entire SIDO circuit after the improvement of the present invention. The present invention superimposes a DC level V _dc that changes with the load on the ramp voltage V _ramp1 to obtain a new ramp voltage V _ramp2 , and V _ramp2 is summed with the output voltage of the current detector to obtain V _sense as the non-inverting input terminal signal of the comparator . An appropriate DC level V _dc0 is superimposed on the output signal V _c of the error amplifier, so that the input signal value V _e at the inverting terminal of the comparator is equal to the maximum value V _p of the input signal V _sense at the non-inverting terminal of the comparator at full load, and the value of V _p The value varies with load and reaches a maximum at full load. The main switch control signal is generated by the comparator, and the charging time of the inductor is adjusted by the drive and dead zone control circuit, thereby reducing the steady-state error of the output voltage. The working principle of the main loop: the input signal of the non-inverting terminal of the error amplifier of the main loop is the reference voltage V _REF1 , the input signal of the inverting terminal is 0.4×(V _o1 +V _o2 ), and the output voltage V _c is superimposed on a DC voltage V _dc0 to obtain the comparator The inverting terminal of the input signal V _e , the DC level V _dc0 is the difference between the peak values V _p and V _c of the input signal V _sense at the non-inverting terminal of the comparator when the circuit is fully loaded. The main-stage switch control signal is generated by the comparator, and the on-off of the main-stage switch is controlled by the drive and dead zone control circuit, thereby adjusting the charging and discharging time of the circuit for the inductor.

When the load changes suddenly, it may be assumed that when the load of the first channel increases, the output voltage of the first channel will have a downward overshoot, and the average value of the inductor current will increase. Therefore, the input signal V _sense at the non-inverting terminal of the comparator also increases, and the difference between the maximum value V _p of V _sense and V _e becomes smaller. Through the inductor current sampling and holding circuit, the peak value of the inductor current at this time is sampled and added to the peak value of the ramp voltage V _ramp1 and then subtracted from _Ve to obtain V _dc . Finally, V _dc is superimposed on the ramp voltage V _ramp1 to obtain a V _ramp2 signal.

FIG. 3 a shows the waveform of the ramp voltage V _ramp1 without superimposing the DC voltage V _dc and the waveform of the ramp voltage V _ramp2 after superimposing the V _dc . Figure 3b defines the peak value V _p of the comparator’s non-inverting input signal V _sense when the value of the input signal V _e at the inverting terminal of the main loop comparator is full load, V _dc0 is the difference between the output voltage V _c and _Ve of the main loop error amplifier value.

Figure 4 The internal circuit structure of the current sampling and holding circuit, including the control signal V ₁ and V ₂ generation circuit, the D flip-flop enable signal EN generation circuit, the inductor current sampling and holding strobe signal S ₁ and S ₂ generation circuit, the DC level V The _dc generation circuit and the circuit for generating a new ramp voltage V _ramp2 after superimposing the DC voltage V _dc on the ramp voltage V _ramp1 are superimposed and summed.

其中，

分别为A、B的反信号。此时EN会从“0”变为“1”，变为有效使能信号，D触发器工作。D flip-flop enable signal EN generation circuit: the non-inverting terminal of comparator 1 is connected to V _H , the non-inverting terminal of comparator 2 is connected to V _L , and the inverting terminals of both are connected to V _o1 -V _o2 , because the output voltage overshoot is generally less than 5 %, so V _H and V _L can be selected as (V _o1 -V _o2 )×(1±2%), and the output logic levels of the two comparators are A and B respectively. When the circuit is stable, the output levels A and B of the comparator are "1" and "0" respectively. When the load changes, one of the two signals A and B will jump.

in,

They are the inverse signals of A and B respectively. At this time, EN will change from "0" to "1", becoming an effective enable signal, and the D flip-flop will work.

接到输入端D，同时把和CLK的与信号接到时钟信号端CLK，输出端Q接到D触发器1、2的使能端，D触发器1的输出端

接到输入端D，并作为D触发器2的CLK信号，D触发器2的输出端

连接到输入端D，同时与上CLK后接到D触发器1的CLK输入端，D触发器2的输出端Q连到D触发器3的使能端，并作为输出信号V₁输出，D触发器3的输出端

接到输入端D，输出端Q作为输出信号V₂输出。D触发器0-3主要实现的功能如下：如图4所示，D触发器0主要实现EN的锁存功能，D触发器1、2主要实现计数功能，计2个周期的PG信号之后，输出高电平。D触发器3在V₁的基础上再计一个PG周期，输出V₂信号。其中，PG信号为主级开关控制信号。The generation circuit of control signals V ₁ and V ₂ : the enable signal of D flip-flop 0 is connected to the EN signal, and the output terminal

Connect to the input terminal D, and at the same time connect the AND signal of CLK to the clock signal terminal CLK, the output terminal Q is connected to the enable terminal of D flip-flop 1 and 2, and the output terminal of D flip-flop 1

Received to the input terminal D, and used as the CLK signal of D flip-flop 2, the output terminal of D flip-flop 2

Connected to the input terminal D, connected to the CLK input terminal of D flip-flop 1 at the same time as the upper CLK, the output terminal Q of D flip-flop 2 is connected to the enable terminal of D flip-flop 3, and output as the output signal V ₁ , D output of flip-flop 3

Received to the input terminal D, the output terminal Q is output as the output signal _V2 . The main functions of D flip-flops 0-3 are as follows: As shown in Figure 4, D flip-flop 0 mainly realizes the latch function of EN, and D flip-flops 1 and 2 mainly realize the counting function. After counting 2 cycles of the PG signal, output high level. D flip-flop 3 counts another PG cycle on the basis of V ₁ and outputs V ₂ signal. Among them, the PG signal is the primary switch control signal.

Inductor current sampling and holding strobe signal S ₁ and S ₂ generation circuit: PG and V ₂ are ORed, and then V ₁ is phase-ORed, and then EN is phase-ORed to obtain the S ₁ signal, and the S ₂ signal is obtained through the NOT gate.

我们取C₁=C₂，则运放输出端电压最后稳定在I_LR_s的最大值I_LR_s-MAX。其中，K₁、K₂和K₃是同类型的开关，当控制信号高电平时，开关闭合。The inductance current sampling and holding circuit is shown in Figure 4. The non-inverting terminal of the op amp is grounded, the inverting terminal is connected to the capacitor C ₁ , and then the inductor sampling current I _L R _s is connected through the switch K ₁ , grounded through the switch K ₂ , and the output terminal of the op amp passes through The two paths of the capacitor _C2 and the switch _K3 are connected to the inverting terminal of the operational amplifier. The output terminal of the op amp passes through the buffer and is summed with V _e and V _ramp1 to obtain the DC voltage signal V _dc . Its main working principle is as follows: First, K ₁ and K ₃ are connected, K ₂ is disconnected, and the voltage at the output terminal of the operational amplifier is 0, so the voltage at both ends of C ₁ is approximately equal to I _L R _s ; then, K ₁ and K ₃ disconnected, K ₂ is connected, the output voltage changes from 0 to

We take C ₁ =C ₂ , then the voltage at the output terminal of the operational amplifier is finally stabilized at the maximum value of I _L R _s I _L R _s-MAX . Wherein, K ₁ , K ₂ and K ₃ are switches of the same type, and the switches are closed when the control signal is at a high level.

的斜率上升，达到设定电压，此时时钟控制开关K₄断开、K₅闭合，输出电压V_ramp2立刻下降为V_dc，下一个时钟周期重复以上过程。其中，K₄和K₅是同类型的开关，当控制信号高电平时，开关闭合。The realization circuit diagram of superimposing DC voltage V _dc on ramp voltage V _ramp1 includes current source I, NMOS current mirror, PMOS current mirror, capacitor C ₃ , clock control switches K ₄ and K ₅ and reference voltage V _dc . The current I is mirrored by the NMOS current mirror and the PMOS current mirror so that the drain current of _MP2 is I, the switch K ₄ is closed, and the switch K ₅ is opened. The current I charges the capacitor C ₃ , and the voltage on the capacitor changes from V _dc to

The slope rises to reach the set voltage. At this time, the clock control switch K ₄ is opened and K ₅ is closed, the output voltage V _ramp2 immediately drops to V _dc , and the above process is repeated in the next clock cycle. Wherein, K ₄ and K ₅ are switches of the same type, and when the control signal is at a high level, the switches are closed.

Figure 5 is a waveform diagram of signals in the current sampling and holding circuit module, which includes the enable signal EN of D flip-flops 1 and 2, V ₁ and V ₂ signals, the main stage switch control signal PG, and the OR signal of PG and V ₂ , V ₁ and PG, V ₂ or the signal phase and and the inductor current I _L .

The features and contents of this patent have been disclosed above, but those skilled in the art may make various replacements and modifications based on the description of the present invention without departing from the spirit of the invention. Therefore, the protection scope of the present invention should not be limited to the above-mentioned embodiments, but should include various replacements and modifications that do not depart from the present invention, and are covered by the claims.

Claims (2)

1. In a control circuit of the single-inductor dual-output converter, a main loop adopts a peak current loop mode to determine the sum of two paths of load currents of the converter, namely the average value I of the total current flowing through an inductor L of the converter_LThe secondary loop adopts a voltage mode to determine the inductive current I_LThe main loop is provided with an error amplifier, a comparator, a trigger and a driving and dead zone control circuit, and the non-inverting end of the error amplifier inputs a reference voltage V_REF1And the reverse phase terminal inputs 0.4 × (V)_o1+V_o2)，V₀₁、V₀₂Two output voltages of the converter, output V of the error amplifier_cConnected to the inverting input of the comparator, ramp voltage V_ramp1And the sampled inductor current I_LR_SThe in-phase input end of the comparator is connected after the signals are superposed and summed, the output of the comparator and the clock signal are respectively input into the trigger, the output of the trigger is connected with the input of the driving and dead zone control circuit, and the driving and dead zone control circuit outputs a signal PG to control the on-off of the main switch, which is characterized in that: when the main loop error amplifier adopts a low-gain error amplifier without large capacitance compensation, a current sampling and holding circuit is additionally arranged in the main loop, and one input signal of the current sampling and holding circuit is a sampled inductive current I_LR_SDC level V output by signal and current sampling and holding circuit_dcAnd a ramp voltage V_ramp1After superposition and summation, a new slope voltage V is generated_ramp2And then with the sampled inductor current I_LR_SThe signals are superposed and summed to be used as the input voltage V of the non-inverting input end of the comparator_senseWhile simultaneously adjusting the output V of the error amplifier_cSuperposed with a DC level V_dc0Obtaining an inverting input signal V of the comparator_eThe signal V_eIs also another input signal of the current sample-and-hold circuit, and is superposed with a DC level V_dc0Should satisfy the input signal value V of the inverting terminal of the comparator_eComparator non-inverting input signal V when it is equal to converter full load_senseMaximum value of (V)_p，V_pThe value of (A) varies with the load, and reaches a maximum at full load of the converter, V_sense=V_p-V_cAt this time, the signal output by the comparator passes through the D trigger and the main switch control signal PG output by the driving and dead zone control circuit, so that the sufficient charging time of the inductor of the converter can be provided, and the steady-state error of the output voltage of the converter can be reduced.

2. The method of claim 1, further comprising the step of: comprising a control signal V₁And V₂Generating circuit, D touchGenerator enable signal EN generating circuit and inductive current sampling and holding gating signal S₁And S₂Generating circuit, DC level V_dcGenerating circuit and at a ramp voltage V_ramp1Upper superposed direct voltage V_dcAfter superposition and summation, a new slope voltage V is generated_ramp2The circuit of (1);

control signal V₁And V₂The generating circuit comprises four D flip-flops D0, D1, D2 and D3, two AND gates NAND1 and NAND2, and an input end D and an output end of a flip-flop D0

One input end of the NAND gate NAND1 is connected in a short circuit mode, the other input end of the NAND gate NAND1 is connected with a clock signal CLK, the output end of the NAND gate 1 is connected with a clock end of a flip-flop D0, an output end Q of the flip-flop D0 is respectively connected with enable ends of flip-flops D1 and D2, and an input end D and an output end D of the flip-flop D1 are connected with the input end and the output endThe short circuit is connected with the clock end of the flip-flop D2, the output end Q of the flip-flop D1 is connected in a null mode, and one input end of the NAND gate 2 is connected with the input end D and the output end of the flip-flop D2

The other input end of the NAND gate 2 is connected with the clock signal CLK, the output end of the NAND gate 2 is connected with the clock end of the flip-flop D1, and the output end Q of the flip-flop D2 is connected with the enable end of the flip-flop D3 and is used as a control signal V₂Clock terminal of flip-flop D3 is connected to clock signal CLK, input terminal D and output terminal D of flip-flop D3

Short circuit, the output end Q of the trigger D3 is a control signal V₁An output terminal of (a);

the D trigger enable signal EN generating circuit comprises two comparators COMP1 and COMP2 and an exclusive-nor gate, wherein the non-inverting terminals of the comparators COMP1 and COMP2 are respectively connected with a voltage signal V_HAnd V_LThe inverting terminals of the comparators COMP1 and COMP2 are interconnected and connected with the two-way output voltage difference V of the converter₀₁-V₀₂，V_HAnd V_LAre all selected as (V)_o1-V_o2) X (1 +/-2%), the outputs of comparators COMP1 and COMP2 are respectively connected to two input ends of an exclusive-nor gate, and an output end of the exclusive-nor gate generates an enable signal EN which is connected to a control signal V₁And V₂Generating an enabling end of a trigger D0 in the circuit;

inductor current sample-and-hold gating signal S₁And S₂The generating circuit comprises two OR gates OR1, OR2, an AND gate AND, an NOT gate NOT AND an OR gate OR1, wherein two input ends of the OR gate OR1, the AND gate AND, the NOT gate NOT AND the OR gate OR1 are respectively connected with a main switch control signal PG AND a control signal V₂The output of the OR gate OR1 is connected to one input terminal of an AND gate AND, AND the other input terminal of the AND gate AND is connected to the control signal V₁The output of the AND gate AND is connected to one input terminal of an OR gate OR2, the other input terminal of the OR gate OR2 is connected to an enable signal EN, AND the output of the OR gate OR2 is connected to the input terminal of a NOT gate AND serves as a strobe signal S₁The output end of the NOT is a gating signal S₂An output end;

DC level V_dcThe generating circuit comprises a control switch K₁、K₂、K₃Capacitor C₁、C₂Operational amplifier, buffer, control switch K₁One end of which is connected with an inductive current I_LR_SSignal, control switch K₁The other end of the capacitor C is connected with a capacitor₁And through a control switch K₂Ground, capacitor C₁The other end of the first resistor is connected with the inverting terminal of the operational amplifier and the capacitor C₂And a control switch K₃Is connected to a capacitor C₂And a control switch K₃The other end of the operational amplifier is connected with the output end of the operational amplifier and the input end of the buffer, the non-inverting end of the operational amplifier is grounded, and a control switch K₁、K₂、K₃The control terminals respectively select the communication signals S₁、S₂、S₁Connected to the output of the buffer and the signal V_eAnd a ramp voltage V_ramp1The three are superposed and summed to generate a direct current level V_dcOutputting;

at a ramp voltage V_ramp1Upper superposed direct voltage V_dcGenerating new slope voltage V_ramp2Includes a current source I, NMOS tube M_N1、M_N2PMOS transistor M_P1、M_P2Control switches K4 and K5 and a capacitor C3, wherein the positive end of the current source I is connected with a power supply V_ddNegative terminal of current source I and NMOS tube M_N1Drain and gate of (1) and NMOS transistor M_N2Is connected with the grid of the NMOS tube M_N1、M_N2Is grounded, the NMOS tube M_N2Drain electrode of and PMOS transistor M_P1Drain and gate of (1) and PMOS transistor M_P2Is connected with the grid electrode of the PMOS transistor M_P1、M_P2Is connected with a power supply V_ddPMOS transistor M_P2Is connected to one end of a switch K4, and the other end of a switch K4 is connected to one end of a switch K5 and one end of a capacitor C3 as a new ramp voltage signal V_ramp2The other end of the switch K5 is connected with the other end of the capacitor C3 and is connected with a direct current level V_dcThe control ends of the switches K5 and K4 are respectively connected with the clock control signals CLK and the inverse signal of CLK

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