CN113316842B - Circuit board assembly and electronic equipment - Google Patents

Abstract

A circuit board assembly and electronic equipment relate to the technical field of electronic devices and are used for solving the problem that when a packaging substrate warps, the surface mounting process is affected. The circuit board assembly comprises a carrier plate (20), a semiconductor device (21) and a reinforcing assembly (22). The semiconductor device (21) is located on the upper surface of the carrier plate (20). The reinforcement assembly (22) is fixed on the carrier plate (20), and a vertical projection on the upper surface of the carrier plate (20) surrounds the periphery of the semiconductor device (21). The reinforcement assembly (22) comprises a laminate structure consisting of at least a first reinforcement (221) and a second reinforcement (222). The first reinforcement (221) is closer to the carrier plate (20) than the second reinforcement (222). The CTE of the first stiffener (221) is different from the CTE of the second stiffener (222), and the CTE of the first stiffener (221) is less than the CTE of the carrier plate (20).

Description

A circuit board component, electronic equipment

Technical field

The present application relates to the technical field of electronic devices, and in particular to a circuit board assembly and electronic equipment.

Background technique

With the rapid development of wireless communications, automotive electronics and other consumer electronics products, electronic devices are developing in the direction of multi-functions. Based on this, when manufacturing the above-mentioned electronic device in the prior art, the chip is usually packaged and then integrated, and the integrated components are placed in the above-mentioned electronic device.

As chip functions continue to increase, the input/output (I/O) pins of the chip continue to increase, which further increases the size of the packaging substrate used to carry the chip. In this case, the larger-sized packaging substrate is prone to warpage, which has a greater negative impact on the surface mount technology (SMT).

Contents of the invention

Embodiments of the present application provide a circuit board assembly and electronic equipment to solve the problem of affecting the surface mounting process when the packaging substrate warps.

In order to achieve the above objectives, the embodiments of this application adopt the following technical solutions:

In one aspect of the embodiment of the present application, a circuit board assembly is provided. The circuit board assembly includes a carrier board, a semiconductor device, and a reinforcement component. Semiconductor devices are located on the upper surface of the carrier board. The semiconductor device may be a bare chip (die), or a chip packaging structure, with one bare chip or multiple bare chips packaged in the chip packaging structure. In addition, the reinforcing component is fixed on the carrier board, and a vertical projection of the reinforcing component on the upper surface of the carrier board surrounds the semiconductor device. The reinforcement assembly includes a laminated structure composed of at least a first reinforcement member and a second reinforcement member. The first reinforcement member is closer to the carrier board than the second reinforcement member. A coefficient of thermal expansion (CTE) of the first reinforcement is different from a CTE of the second reinforcement, and the CTE of the first reinforcement is smaller than the CTE of the carrier board. As a result, during the manufacturing process of circuit board assemblies, when the preparation temperature changes, a mismatch occurs between the CTE of the packaging substrate and the CTE of the semiconductor device, which manifests as warping of the packaging substrate. On this basis, since the CTE of the first reinforcement and the CTE of the second reinforcement in the reinforcement component are different, the CTE of the first reinforcement and the second reinforcement in the reinforcement component will also produce a mismatch, causing the reinforcement component itself to warping. By setting the fixed position of the reinforcing component on the carrier plate, the warping direction of the reinforcing component is opposite to the warping direction of the carrier plate. In turn, the reinforcing component can exert a force on the carrier plate that is opposite to the warping direction of the carrier plate. In this way, the warpage of the carrier board can be suppressed and the local deformation of the carrier board is limited. In this case, when the chip packaging structure is electrically connected to the PCB using a surface mount process, the warping of both ends of the carrier board, such as the packaging substrate, can be effectively suppressed under the action of the reinforcing components, so that it can Reduce the chance that some solder balls located at the warped position of the package substrate will be separated from the PCB, resulting in open soldering or even breakage. In addition, the deformation amount of the lower surface of the packaging substrate at the position corresponding to the semiconductor device will also be reduced, thereby reducing the probability that multiple solder balls at this position will be bonded due to pressure. On this basis, in the reinforcement assembly, the CTE of the first reinforcement close to the carrier board is smaller than the CTE of the carrier board. In this way, during the warping process of the reinforcing component, the lateral internal stress generated at the interface between the semiconductor device and the carrier board, such as a packaging substrate, can be reduced. This reduces the probability that the base glue between the semiconductor device and the packaging substrate or the solder ball will crack under the above-mentioned internal stress.

Optionally, in some embodiments of the present application, the reinforcing component is connected to the upper surface of the carrier board. The CTE of the semiconductor device is smaller than the CTE of the carrier board. The CTE of the first reinforcement is less than the CTE of the second reinforcement. At this time, the semiconductor device may include at least one bare chip. The carrier board may be a packaging substrate electrically connected to the semiconductor device. Alternatively, the semiconductor device may be a chip packaging structure filled with more plastic sealing layers, and the carrier may be a PCB.

Or, in other embodiments of the present application, the carrier plate has a lower surface opposite to the upper surface. The reinforcing component is connected to the upper surface of the carrier plate. The CTE of the semiconductor device is greater than the CTE of the carrier board. The CTE of the first reinforcement is greater than the CTE of the second reinforcement. At this time, the semiconductor device can be a chip packaging structure filled with more plastic sealing layers, and the carrier board can be a PCB.

Optionally, in some embodiments of the present application, the reinforcing component is connected to the lower surface of the carrier plate. The reinforcement component includes a first reinforcement component closest to the carrier board and a second reinforcement component farthest from the carrier board. The CTE of the semiconductor device is smaller than the CTE of the carrier board. The CTE of the first reinforcement is greater than the CTE of the second reinforcement. At this time, the semiconductor device may include at least one bare chip. The carrier board may be a packaging substrate electrically connected to the semiconductor device. Alternatively, the semiconductor device may be a chip packaging structure filled with more plastic sealing layers, and the carrier may be a PCB.

Or, in other embodiments of the present application, the reinforcing component is connected to the lower surface of the carrier plate. The reinforcement component includes a first reinforcement component closest to the carrier board and a second reinforcement component farthest from the carrier board. The CTE of the semiconductor device is greater than the CTE of the carrier board. The CTE of the first reinforcement is less than the CTE of the second reinforcement. At this time, the semiconductor device can be a chip packaging structure filled with more plastic sealing layers, and the carrier board can be a PCB.

Optionally, the vertical projection of the reinforcing component on the upper surface of the carrier board surrounds at least three adjacent sides of the semiconductor device. Wherein, the side surfaces of the semiconductor device intersect with the upper surface of the carrier board. In this way, in the process of restraining the warpage of the carrier board by the reinforcement component, the force generated by the warpage of the reinforcement component itself can be applied to the parts surrounding the two opposite sides of the semiconductor device, so that the semiconductor device is located in the carrier board The warpage of the two side parts is well suppressed.

Optionally, the reinforcing components are hollow frame structures connected end to end. The vertical projection of the reinforcing component on the upper surface of the carrier board surrounds the semiconductor device. In this way, when the reinforcement component suppresses the warpage of the carrier board, the force generated by the warpage of the reinforcement component itself can be applied to the portion of the carrier board located around the semiconductor device, thereby achieving the purpose of suppressing warpage.

Optionally, the reinforcement component further includes at least one intermediate reinforcement located between the first reinforcement and the second reinforcement. The intermediate reinforcement is connected to the first reinforcement and the second reinforcement. The CTE of the intermediate reinforcement is located between the CTE of the first reinforcement and the CTE of the second reinforcement. In this way, the mismatch between the CTE of the first reinforcement and the CTE of the second reinforcement can be appropriately alleviated through the intermediate reinforcement, thereby improving the stability of the circuit board assembly having the reinforcement component.

Optionally, the reinforcement assembly includes at least two intermediate reinforcements. In some embodiments of the present application, the CTE of the first reinforcement is less than the CTE of the second reinforcement. The CTE of at least two intermediate reinforcements gradually increases in the direction approaching the second reinforcement. Or, in other embodiments of the present application, the CTE of the first reinforcement is greater than the CTE of the second reinforcement. The CTE of at least two intermediate reinforcements gradually decreases in the direction approaching the second reinforcement. In this way, through the plurality of intermediate reinforcements located between the first reinforcement and the second reinforcement, the CTE of the reinforcement component can be gradually changed in a direction away from the packaging substrate, which is beneficial to improving the stability of the reinforcement component.

Optionally, two opposing surfaces of any two adjacent reinforcement members in the reinforcement assembly are respectively provided with at least one first protrusion and at least one first groove. Wherein, each first protrusion is located in a first groove and matches with the first groove. In this way, during the warping process of the reinforcing component, the transverse shear force at the interface between two adjacent reinforcing members can be applied to the side surface of the first protrusion. This can reduce the probability of damage to the bonding layer between two adjacent layers of reinforcements under the action of shear force, and improve the connection strength of two adjacent reinforcements.

Optionally, the reinforcing components are hollow frame structures connected end to end. The first protrusion and the vertical projection of the first groove on the upper surface of the carrier board surround the semiconductor device. This allows the transverse shearing force at the interface between two adjacent reinforcement members to be applied to the side surfaces of the first protrusion surrounding the semiconductor device.

Optionally, among the two opposite surfaces of any two adjacent reinforcement members in the reinforcement assembly, one surface with the first protrusion is also provided with at least one second groove, and the other surface with the first groove is also provided with There is at least one second bump. Wherein, each second protrusion is located in a second groove and matches with the second groove. As mentioned above, during the warping process of the reinforcing component, the transverse shear force at the interface of two adjacent reinforcing members can be applied to the side of the second protrusion. This can further improve the connection strength of two adjacent reinforcements.

Optionally, two opposing surfaces of any two adjacent reinforcement members in the reinforcement assembly are parallel to each other, and both have an included angle with the upper surface of the carrier plate. In this way, the distance between two adjacent reinforcements can be equal everywhere. Thus, the thickness of the adhesive layer used to connect two adjacent reinforcement members is uniform. This allows each part of the above-mentioned adhesive layer to receive uniform force when the reinforcing component is warped.

Optionally, in some embodiments of the present application, the reinforcement component includes a first reinforcement, a second reinforcement and at least one intermediate reinforcement. The surface of the middle reinforcement member facing the first reinforcement member is parallel to the surface of the middle reinforcement member facing the second reinforcement member.

Or, optionally, in other embodiments of the present application, the reinforcement component includes a first reinforcement, a second reinforcement and at least two intermediate reinforcements. The at least two intermediate reinforcements are respectively a first intermediate reinforcement close to the carrier board and a second intermediate reinforcement away from the carrier board. The surface of the first intermediate reinforcement facing the first reinforcement intersects the surface of the first intermediate reinforcement facing the second intermediate reinforcement. The surface of the second intermediate reinforcement facing the first intermediate reinforcement intersects the surface of the second intermediate reinforcement facing the second reinforcement.

Optionally, the carrier board is a packaging substrate, and the semiconductor device is a bare chip. The circuit board assembly also includes: heat dissipation cover and heat dissipation glue. Wherein, the heat dissipation cover is connected to the surface of one of the reinforcement members in the reinforcement assembly facing away from the packaging substrate, and covers the surface of the bare chip facing away from the packaging substrate; the CTE of the heat dissipation cover is greater than the CTE of the packaging substrate. The heat dissipation glue is located between the heat dissipation cover and the bare chip, and is in contact with the heat dissipation cover and the bare chip. The materials that make up thermal paste include thermal interface materials. The CTE of the heat dissipation cover may be greater than the CTE of the packaging substrate. Because the CTE of the reinforcement in the reinforcement assembly closest to the package substrate is less than the CTE of the package substrate, there is a mismatch between the CTE of the thermal cover and the CTE of that reinforcement. In this way, the heat dissipation cover and the reinforcement component can produce warpage in opposite directions to the warpage of the packaging substrate, thereby suppressing the warpage of the packaging substrate.

Optionally, in some embodiments of the present application, the heat dissipation cover is located between the first reinforcement and the second reinforcement. In order to make the direction of warpage of the heat dissipation cover and the reinforcement component together be opposite to the warp direction of the packaging substrate, the CTE of the heat dissipation cover is located between the CTE of the first reinforcement and the CTE of the second reinforcement. Or, in other embodiments of the present application, the heat dissipation cover is located on a side surface of the second reinforcement member facing away from the packaging substrate. In this case, in order to cause the direction of warpage of the heat dissipation cover and the reinforcement component to be opposite to the warp direction of the packaging substrate, the CTE of the heat dissipation cover is greater than the CTE of the second reinforcement.

Optionally, the circuit board assembly also includes a plastic encapsulation layer. The plastic sealing layer is located on the upper surface of the packaging substrate and wraps around all sides of the bare chip; the CTE of the plastic sealing layer is greater than the CTE of the packaging substrate. Wherein, the side surfaces of the bare chip intersect with the upper surface of the packaging substrate. The CTE of the above-mentioned plastic sealing layer can be greater than the CTE of the packaging substrate, so that there is a mismatch between the CTE of the plastic sealing layer and the CTE of the packaging substrate. This can cause the warpage of the plastic sealing layer to be in the opposite direction to the warpage of the packaging substrate, so as to achieve a better effect on the packaging substrate. The warpage is suppressed for the purpose.

Optionally, the circuit board assembly further includes a first adhesive layer and a second adhesive layer. Wherein, the first adhesive layer is located between the carrier board and the reinforcement component, and is used to connect the carrier board and the reinforcement component. The second adhesive layer is located between two adjacent reinforcement members in the reinforcement assembly and is used to connect the two adjacent reinforcement members. Wherein, the shear modulus of the first adhesive layer is smaller than the shear modulus of the second adhesive layer. In this way, using a second adhesive layer with a larger shear modulus can increase the coupling effect between two adjacent reinforcements in the reinforcement assembly. In addition, using a first adhesive layer with a smaller shear module can take advantage of its weak resistance to shear in the lateral direction to reduce the lateral stretching or lateral stretching of the reinforcing component to the carrier board, such as the packaging substrate, during the warping process. The shrinkage effect relieves the stress at the interface between the semiconductor device and the packaging substrate.

Optionally, the equivalent CTE of the reinforcement component is smaller than the CTE of the carrier board. The equivalent CTE of the reinforced component is (∑α _j ×E _j ×V _j )/(∑E _j ×V _j ). Among them, α _j is the CTE of the material of the j-th layer of reinforcement close to the carrier plate in the reinforced component; E _j is the Young's modulus of the j-th layer of reinforcement close to the carrier board in the reinforced component; V _j is the reinforced component , the volume proportion of the jth layer of reinforcement close to the carrier board; j≥1, j is a positive integer. After the CTE value of the carrier board is determined, the equivalent CTE of the reinforcement component can be smaller than the CTE of the carrier board. Therefore, during the warping process of the reinforced component, the lateral internal stress generated at the interface between the semiconductor device and the packaging substrate can be reduced.

Another aspect of the present application provides an electronic device. The electronic device includes a carrier board and any one of the above circuit board components installed on the carrier board. The electronic device has the same technical effect as the circuit board assembly provided by the previous embodiment, which will not be described again here.

Description of the drawings

Figure 1 is a schematic structural diagram of a mobile terminal provided by some embodiments of the present application;

Figure 2a is a schematic structural diagram of the circuit board assembly in Figure 1;

Figure 2b is another structural schematic diagram of the circuit board assembly in Figure 1;

Figure 2c is a schematic structural diagram of the reinforcement component in Figure 2a;

Figure 2d is another structural schematic diagram of the reinforcement component in Figure 2a;

Figure 2e is another structural schematic diagram of the reinforcement component in Figure 2a;

Figure 3 is a structural schematic diagram of the circuit board assembly in Figure 1;

Figure 4a is a schematic diagram of deformation and warpage of the packaging substrate in Figure 3;

Figure 4b is a schematic diagram of the reinforcing component suppressing the warpage of the packaging substrate corresponding to the warpage of the packaging substrate in Figure 4a;

Figure 5a is a schematic diagram of another deformation and warpage of the packaging substrate in Figure 3;

Figure 5b is a schematic diagram of the reinforcing component suppressing the warping of the packaging substrate corresponding to the warping of the packaging substrate in Figure 5a;

Figure 6 is another structural schematic diagram of the circuit board assembly in Figure 1;

Figure 7a is another structural schematic diagram of the circuit board assembly in Figure 1;

Figure 7b is another structural schematic diagram of the circuit board assembly in Figure 1;

Figure 8a is another structural schematic diagram of the circuit board assembly in Figure 1;

Figure 8b is a schematic structural diagram of the first reinforcement and the second reinforcement in Figure 8a;

Figure 8c is another structural schematic diagram of the first reinforcement and the second reinforcement in Figure 8a;

Figure 8d is another structural schematic diagram of the first reinforcement and the second reinforcement in Figure 8a;

Figure 8e is another structural schematic diagram of the first reinforcement and the second reinforcement in Figure 8a;

Figure 8f is another structural schematic diagram of the first reinforcement and the second reinforcement in Figure 8a;

Figure 9a is a structural schematic diagram of the first protrusion on the first reinforcement;

Figure 9b is another structural schematic diagram of the first protrusion on the first reinforcement;

Figure 10a is another structural schematic diagram of the circuit board assembly in Figure 1;

Figure 10b is a schematic structural diagram of the first reinforcement and the second reinforcement;

Figure 11a is another structural schematic diagram of the circuit board assembly in Figure 1;

Figure 11b is another structural schematic diagram of the circuit board assembly in Figure 1;

Figure 12a is a schematic structural diagram of the circuit board assembly in Figure 1;

Figure 12b is a schematic structural diagram of the circuit board assembly in Figure 1;

Figure 13 is a structural schematic diagram of the circuit board assembly in Figure 1;

Figure 14a is a schematic structural diagram of the circuit board assembly in Figure 1;

Figure 14b is a schematic diagram of the reinforcement component in Figure 14a that suppresses warpage of the packaging substrate;

Figure 14c is another schematic diagram of the reinforcement component in Figure 14a suppressing warpage of the packaging substrate;

Figure 14d is a structural schematic diagram of the circuit board assembly in Figure 1;

Figure 15a is a schematic structural diagram of the circuit board assembly in Figure 1;

Figure 15b is a schematic diagram of the reinforcement component in Figure 15a that suppresses warpage of the packaging substrate;

Figure 15c is another schematic diagram of the reinforcement component in Figure 15a suppressing warpage of the packaging substrate;

Figure 16a is a schematic structural diagram of the circuit board assembly in Figure 1;

Figure 16b is a schematic diagram of the reinforcement component in Figure 16a that suppresses warpage of the packaging substrate;

Figure 16c is another schematic diagram of the reinforcing component in Figure 16a suppressing warpage of the packaging substrate.

Reference signs:

01-Electronic equipment; 02-Chip packaging structure; 10-Display screen; 11-Middle frame; 12-Casing; 100-Circuit board assembly; 20-Carrier board; 21-Semiconductor device; 22-Reinforcement component; 221-No. A reinforcement; 222-the second reinforcement; 223-the intermediate reinforcement; 101-packaging substrate; 201-bare chip; 31-first electrical connector; 32-second electrical connector; 41-first adhesive layer ; 42-Second adhesive layer; 51-First protrusion; 61-First groove; 52-Second protrusion; 62-Second groove; 70-Heat dissipation cover; 71-Heat dissipation glue; 72-Plastic sealing Layer; 203-PCB.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments.

Herein, the terms “first”, “second”, etc. are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, "plurality" means two or more.

In addition, in this article, directional terms such as "upper" and "lower" are defined relative to the schematic placement of the structure in the drawings. It should be understood that these directional terms are relative concepts and they are used relative to descriptions and clarifications, which may change accordingly depending on the orientation in which the structure is placed.

An embodiment of the present application provides an electronic device 01 as shown in Figure 1 . The electronic device 01 includes, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, a smart wearable product, etc. The embodiment of the present application does not place any special restrictions on the specific form of the above-mentioned electronic device 01. For convenience of explanation, the following description takes the electronic device 01 as a mobile phone as an example.

In this case, the structure of the above-mentioned electronic device 01, as shown in FIG. 1, mainly includes a display screen 10, a middle frame 11 and a casing 12. The display screen 10 and the middle frame 11 are arranged in the housing 12 .

In addition, the electronic device 01 also includes a circuit board assembly 100 disposed on the side of the middle frame 11 away from the display screen 10 . The middle frame 11 can carry the circuit board assembly 100 .

The circuit board assembly 100 can be electrically connected to a flexible printed circuit (FPC) on the back of the display screen 10 . Therefore, a display signal can be input to the display screen 10 through the circuit board assembly 100, so that the display screen 10 displays a corresponding picture.

In the embodiment of the present application, as shown in FIG. 2a , the above-mentioned circuit board assembly 100 includes a carrier board 20 , a semiconductor device 21 and a reinforcement component 22 .

The above-mentioned semiconductor device 21 may be a bare chip or a chip packaging structure. One or more bare chips are packaged in the chip packaging structure. In addition, the carrier board 20 may be a substrate, a redistribution layer (RDL), a silicon substrate (interposer), or other structures used to carry integrated circuits and transmit electrical signals. Due to differences in materials or structures, the carrier 20 and the semiconductor device 21 have different coefficients of thermal expansion (CTE).

The carrier board 20 includes an upper surface A1 and a lower surface A2 which are oppositely arranged. The reinforcing component 22 is fixed on the carrier plate 20 . In some embodiments of the present application, as shown in FIG. 2 a , the reinforcing component 22 may be located on the same side of the carrier board 20 as the semiconductor device 21 , that is, the reinforcing component 22 is connected to the upper surface A1 of the carrier board 20 .

Or, in other embodiments of the present application, as shown in FIG. 2 b , the reinforcing component 22 and the semiconductor device 21 may be located on both sides of the carrier board 20 , that is, the reinforcing component 22 is connected to the lower surface A2 of the carrier board 20 . Moreover, the vertical projection of the reinforcing component 22 on the upper surface A1 of the carrier board 20 surrounds the periphery of the semiconductor device 21 , that is, surrounds at least one side surface of the semiconductor device 21 . Wherein, the side surface of the semiconductor device 21 intersects the upper surface A1 of the carrier board 20 .

In some embodiments of the present application, in FIG. 2 c , the vertical projection of the reinforcing component 22 on the upper surface A1 of the carrier board 20 surrounds at least three adjacent sides of the semiconductor device 21 .

In this way, the first part a1 in the reinforcement assembly 22 can connect the second part a2 and the third part a3 located on the left and right sides of the semiconductor device 21 . In the process of the reinforcing component 22 suppressing the warping of the carrier board 20, the force generated by the warping of the reinforcing component 22 itself can be effectively applied to the second part a2 and the third part a3 through the first part a1 of the reinforcing component 22, so that The warpage of the portions on both sides of the semiconductor device 21 in the carrier board 20 is well suppressed.

Or, in other embodiments of the present application, as shown in Figure 2d, the reinforcing component 22 is a hollow frame structure connected end to end.

In this case, the vertical projection of the reinforcing component 22 on the upper surface A1 of the carrier board 20 surrounds the semiconductor device 21 , so that the semiconductor device 21 can be surrounded in the hollow area formed by the reinforcing component 22 . In this way, when the reinforcing component 22 suppresses the warping of the carrier board 20, the force generated by the warping of the reinforcing component 22 itself can be applied to the portion of the carrier board 20 located around the semiconductor device 21, thus suppressing the warpage. the goal of.

The above is an example in which the reinforcing component 22 is a continuous structure, and the vertical projection of the reinforcing component 22 on the upper surface A1 of the carrier board 20 surrounds at least one side of the semiconductor device 21 . In other embodiments of the present application, as shown in FIG. 2e , the reinforcing component 22 may also be a discontinuous structure. In this case, the vertical projection of the reinforcing component 22 on the upper surface A1 of the carrier plate 20 includes multiple, for example, four discontinuous subprojections. Each sub-projection is located on one side of the semiconductor device 21 .

In addition, as shown in FIG. 2 a , the reinforcement assembly 22 includes a stacked structure composed of at least a first reinforcement 221 and a second reinforcement 222 . It should be noted that FIG. 2a is an illustration based on an example in which the reinforcing component 22 includes two reinforcing parts, for example, a first reinforcing part 221 and a second reinforcing part 222.

The first reinforcement 221 is closer to the carrier board 20 than the second reinforcement 222 . The CTE of the first reinforcement 221 is different from the CTE of the second reinforcement 222 . Moreover, the CTE of the first reinforcement 221 is smaller than the CTE of the carrier board 20 .

The arrangement of the circuit board assembly 100 and the reinforcing assembly 22 will be described in detail below with examples.

Example 1

In an example, the above-mentioned circuit board assembly 100 may be a chip packaging structure 02a as shown in FIG. 3 . In this case, the semiconductor device 21 in the circuit board assembly 100 may include at least one bare chip 201a as shown in FIG. 3 .

The carrier board 20 in the circuit board assembly 100 may be a packaging substrate 101a for carrying the bare chip 201a as shown in FIG. 3 . The reinforcing component 22 is fixedly connected to the upper surface A1 of the packaging substrate 101a.

As shown in FIG. 3 , the bare chip 201 a can be electrically connected to the circuit in the packaging substrate 101 a through a plurality of first electrical connectors 31 in a flip chip manner. The first electrical connector 31 may be a solder ball or a bump.

A plurality of second electrical connectors 32 are usually provided on the lower surface A2 of the packaging substrate 101a. The second electrical connector 32 may be a solder ball. When the circuit board assembly 100 is installed on a printed circuit board (PCB), the circuit board assembly 100 is electrically connected to the circuit on the PCB through the second electrical connector 32 .

It should be noted that in the embodiment of the present application, the flip chip method is used as an example to introduce the connection method of the bare chip 201a in the chip packaging structure. In actual products, the bare chip 201a can also be wired bonded. ) or other other ways to be electrically connected to the package substrate 101a.

In this example, the CTE of the bare chip 201a is smaller than the CTE of the package substrate 101a. At this time, in order to enable the reinforcing component 22 to exert a force on the carrier plate 20 in a direction opposite to the warping direction of the carrier plate 20, so as to suppress the warpage of the carrier plate 20. The warping direction of the reinforcing component 22 needs to be opposite to the warping direction of the carrier plate 20 . In this example, the reinforcement component 22 includes two reinforcements, namely a first reinforcement 221 and a second reinforcement 222 . The CTE of the first reinforcement 221 is smaller than the CTE of the second reinforcement 222 .

In this way, during the manufacturing process of the circuit board assembly 100, when the manufacturing temperature changes, a mismatch will occur between the CTE of the packaging substrate 101a and the CTE of the semiconductor device 21. The packaging substrate 101a with a larger CTE will have a greater deformation than the larger CTE. For the small semiconductor device 21, the package substrate 101a exhibits a warpage phenomenon as shown in FIG. 4a.

For example, in a high-temperature process, for example, when the second electrical connector 32 on the lower surface A2 of the packaging substrate 101a is reflowed, the amount of expansion of the packaging substrate 101a during deformation is greater than the amount of expansion of the bare chip 201a during deformation. . In this way, as shown in Figure 4a, the package substrate 101a will warp upward.

On this basis, since the CTE of the first reinforcement 221 in the reinforcement assembly 22 is smaller than the CTE of the second reinforcement 222, a mismatch will also occur between the CTE of the first reinforcement 221 and the CTE of the second reinforcement 222, and the CTE will be smaller than the CTE of the second reinforcement 222. The expansion amount of the second reinforcement member 222 with a large CTE is greater than the expansion amount of the first reinforcement member 221 with a smaller CTE. As a result, the reinforcing component 22 itself has downward curvature.

As shown in FIG. 4 b , the warping direction of the reinforcing component 22 (eg, downward) is opposite to the warping direction of the carrier 20 , such as the packaging substrate 101 a (eg, upward as shown in FIG. 4 a ). Moreover, the reinforcing component 22 is connected to the packaging substrate 101a, so the reinforcing component 22 can apply a force (the force direction is downward) to the packaging substrate 101a that is opposite to the warping direction (for example, upward) of the packaging substrate 101a. In this way, upward warping of the packaging substrate 101a can be suppressed and local deformation of the packaging substrate 101a is limited.

In this case, during the process of electrically connecting the chip packaging structure 02 to the PCB using a surface mounting process, the warping at both ends of the packaging substrate 101a can be effectively suppressed under the action of the reinforcing components 22, thereby reducing the risk. The part of the second electrical connector 32 located at the warped position of the package substrate 101a (FIG. 4a) is separated from the PCB, and there is a possibility of open soldering or even breakage.

In addition, since the upward warping of both ends of the packaging substrate 101a can be effectively suppressed by the reinforcing component 22, the lower surface A2 of the packaging substrate 101a protrudes downward at the position corresponding to the semiconductor device 21 (Fig. 4a) The amount of deformation will also be reduced, thereby reducing the probability that the plurality of second electrical connectors 32 at this position will be bonded due to pressure.

On this basis, in the reinforcement assembly 22 , the CTE of the reinforcement closest to the carrier board 20 , such as the first reinforcement 221 , is smaller than the CTE of the carrier board 20 . In this way, during the warping process of the reinforcing component 22, the lateral internal stress F generated at the interface between the semiconductor device 21 and the packaging substrate 101a can be reduced. This reduces the probability that the base glue between the semiconductor device 21 and the packaging substrate 101a or the first electrical connector 31 will crack under the action of the above-mentioned internal stress F.

It should be noted that the above description is based on the fact that the reinforcing component 22 suppresses the upward warping portion of the packaging substrate 101a during the high-temperature process. In other embodiments of the present application, when the preparation temperature decreases, for example, after the primer under the bare chip 201a undergoes a maturation process (temperature is about 150°C), when the temperature gradually decreases, as shown in Figure 5a, the packaging substrate The shrinkage amount of 101a is greater than the shrinkage amount of bare chip 201a. As a result, the packaging substrate 101a will warp downward.

On this basis, since the CTE of the first reinforcement 221 in the reinforcement assembly 22 is smaller than the CTE of the second reinforcement 222, a mismatch will also occur between the CTE of the first reinforcement 221 and the CTE of the second reinforcement 222. The CTE The shrinkage amount of the larger second reinforcement member 222 is greater than the shrinkage amount of the first reinforcement member 221 with smaller CTE, so that the reinforcement assembly 22 itself has upward warping.

As shown in FIG. 5 b , the warping direction of the reinforcing component 22 (for example, upward) is opposite to the warping direction of the packaging substrate 101 a (for example, downward as shown in FIG. 5 a ). Furthermore, the reinforcing component 22 is connected to the packaging substrate 101a, so the reinforcing component 22 can apply a force (the force direction is upward) to the packaging substrate 101a that is opposite to the warping direction (for example, downward) of the packaging substrate 101a. In this way, downward warping of the packaging substrate 101a can be suppressed, and local deformation of the packaging substrate 101a is limited.

In addition, in the embodiment of the present application, in order to further alleviate the lateral internal stress generated by the semiconductor device 21 at the interface between the semiconductor device 21 and the packaging substrate 101a, the equivalent CTE of the above-mentioned reinforcing component 22 is smaller than the carrier board 20, such as the package CTE of substrate 101a. Therefore, when the reinforcing component 22 itself warps, the degree of CTE mismatch between the semiconductor device 21 and the carrier 20 caused by the reinforcing component 22 can be reduced, and the probability of deterioration of stress at the interface between the semiconductor device 21 and the packaging substrate 101a can be reduced.

It can be seen from FIG. 4a and FIG. 5a that the part of the packaging substrate 101a close to the semiconductor device 21 has a small deformation, while the part far from the semiconductor device 21 has a large deformation, especially the two ends of the packaging substrate 101a have the largest deformation. Since the warping direction of the reinforcing component 22 is opposite to that of the packaging substrate 101a, it can be seen from FIG. 4b and FIG. 5b that when the reinforcing component 22 is warped, the reinforcing member 20 exerts an upward or downward force on the packaging substrate 101a in the direction away from the semiconductor device 21. The downward force gradually increases.

In the embodiment of the present application, the equivalent CTE of the above-mentioned reinforcement component 22 can be approximately calculated through the following formula (1):

(∑α _j ×E _j ×V _j )/(∑E _j ×V _j ) (1)

Where, α _j is the CTE of the material of the jth layer of reinforcement close to the carrier plate 20 in the reinforcement assembly 22;

E _j is the Young's modulus of the j-th layer of reinforcement close to the carrier plate 20 in the reinforcement assembly 22;

V _j is the volume specific gravity of the jth layer of reinforcements close to the carrier plate 20 in the reinforcement assembly 22 .

j≥1, j is a positive integer.

For example, the CTE of the packaging substrate 101a may be in the range of 13 to 16 ppm. After the value of the CTE of the packaging substrate 101a is determined, the equivalent CTE of the reinforcement component 22 may be smaller than the CTE of the packaging substrate 101a. Therefore, during the warping process of the reinforcing component 22, the lateral internal stress generated at the interface between the semiconductor device 21 and the packaging substrate 101a can be reduced.

In addition, in order to firmly connect the reinforcing component 22 with the packaging substrate 101a, as shown in FIG. 6, the circuit board component 100 further includes the first adhesive layer 41. The first adhesive layer 41 is located between the packaging substrate 101a as the carrier board 20 and the reinforcing component 22. The first adhesive layer 41 is used to connect the packaging substrate 101a and the reinforcing component 22.

In addition, in order to connect two adjacent reinforcement members in the reinforcement assembly 22 , such as the first reinforcement member 221 and the second reinforcement member 222 in FIG. 6 , the circuit board assembly further includes a second adhesive layer 42 . The second adhesive layer 42 is used to connect two adjacent reinforcement members.

The shear modulus (or strength) of the first adhesive layer 41 should be smaller than the shear modulus of the second adhesive layer 42 .

In this way, using the second adhesive layer 42 with a larger shear modulus can increase the coupling effect between two adjacent reinforcements in the reinforcement assembly 22, such as the above-mentioned first reinforcement 221 and the second reinforcement 222.

In addition, it can be known from the above that during the warping process, the force exerted by the reinforcing component 22 on the packaging substrate 101a is an upward or downward longitudinal force (perpendicular to the upper surface A1 of the packaging substrate 101a). However, the colloid has a greater ability to resist force in the longitudinal direction, but a weaker ability to resist shearing in the transverse direction (parallel to the upper surface A1 of the packaging substrate 101a). Therefore, using the first adhesive layer 41 with a smaller shear module can take advantage of its weak resistance to shearing in the lateral direction to reduce the lateral stretching or shrinking effect of the reinforcing component 22 on the packaging substrate 101a during the warping process. , relieving the stress at the interface between the semiconductor device 21 and the packaging substrate 101a.

The above description is based on the example that the reinforcement component 22 includes two reinforcements, such as the first reinforcement 221 and the second reinforcement 222 .

In other embodiments of the present application, as shown in Figure 7a, the reinforcement assembly 22 may further include at least one intermediate reinforcement 223 located between the first reinforcement 221 and the second reinforcement 222.

In this case, the first reinforcement 221 is the reinforcement closest to the packaging substrate 101a, and the second reinforcement 222 is the reinforcement farthest from the packaging substrate 101a.

The intermediate reinforcement 223 is connected to the first reinforcement 221 and the second reinforcement 222 . For example, the larger second adhesive layer 42 of the shearing module may be disposed between the intermediate reinforcement 223 and the first reinforcement 221 and the second reinforcement 222 respectively.

Furthermore, the CTE of the intermediate stiffener 223 may be located between the CTE of the first stiffener 221 and the CTE of the second stiffener 222 . In this way, the mismatch between the CTE of the first reinforcement 221 and the CTE of the second reinforcement 222 can be appropriately alleviated through the intermediate reinforcement 223, thereby improving the stability of the circuit board assembly 100 having the reinforcement component 22.

On this basis, in some embodiments of the present application, as shown in Figure 7b, the reinforcement component 22 includes at least two intermediate reinforcements, such as a first intermediate reinforcement 223a and a second intermediate reinforcement 223b.

In the case where the CTE of the first reinforcement 221 is smaller than the CTE of the second reinforcement 222 , the CTEs of the at least two intermediate reinforcements gradually increase along the direction approaching the second reinforcement 222 .

For example, in Figure 7b, the CTE of the first intermediate reinforcement 223a is greater than the CTE of the first reinforcement 221 and smaller than the CTE of the second intermediate reinforcement 223b. The CTE of the second intermediate reinforcement 223b is greater than the CTE of the first intermediate reinforcement 223a and smaller than the CTE of the second reinforcement 222. In this way, through the multiple intermediate reinforcements located between the first reinforcement 221 and the second reinforcement 222 , the CTE of the reinforcement component 22 can be gradually increased in the direction away from the packaging substrate 101 a , thereby facilitating the improvement of the reinforcement component 22 stability.

Example 2

In this example, the same as Example 1, the semiconductor device 21 in the above-mentioned circuit board assembly 100 includes a bare chip 201a, and the carrier board 20 in the circuit board assembly 100 is a packaging substrate 101a.

The reinforcing component 22 is disposed on the upper surface of the packaging substrate 101a. The first adhesive layer 41 with a smaller shear module is used between the reinforcing component 22 and the packaging substrate 101a. In the reinforcement assembly 22, a second adhesive layer 42 with a larger shear module is used between two adjacent reinforcements.

The difference from Example 1 is that, as shown in Figure 8a, the two opposing surfaces of any two adjacent reinforcements in the reinforcement assembly 22 are respectively provided with first protrusions 51 and first grooves 61 as shown in Figure 8b. . The first protrusion 51 is located in the first groove 61 and matches with the first groove 61 .

As shown in FIG. 8a , for example, the reinforcing component 22 includes two reinforcing parts, namely a first reinforcing part 221 and a second reinforcing part 222 . In this case, the first protrusion 51 may be provided on the surface of the first reinforcement 221 facing the second reinforcement 222 . A first groove 61 is provided on the surface of the second reinforcement 222 facing the first reinforcement 221 .

In this way, during the warping process of the reinforcing component 22, the transverse shear force F (as shown in FIG. 8a) at the interface of the first reinforcing member 221 and the second reinforcing member 222 can be applied to the first protrusion 51 side. Therefore, the probability of damage of the second adhesive layer 42 under the action of the shear force F can be reduced, and the connection strength between the first reinforcement 221 and the second reinforcement 222 can be improved.

In other embodiments of the present application, as shown in FIG. 8c , at least two first protrusions 51 may be provided on the surface of the first reinforcement 221 facing the second reinforcement 222 . At least two first grooves 61 are provided on the surface of the second reinforcement 222 facing the first reinforcement 221 . Each first protrusion 51 cooperates with a first groove 61 .

Alternatively, as shown in FIG. 8d , at least one first groove 61 can also be provided on the surface of the first reinforcement 221 facing the second reinforcement 222 . At least one first protrusion 51 is provided on the surface of the second reinforcement 222 facing the first reinforcement 221 . Each first protrusion 51 cooperates with a first groove 61 .

Alternatively, in other embodiments of the present application, as shown in FIG. 8e , the first reinforcement 221 faces the second reinforcement 222 and has a first protrusion 51 on its surface, and is also provided with at least one second concave surface. slot 62. In addition, the second reinforcement 222 faces the first reinforcement 221 and has a surface with the first groove 61 and is also provided with at least one second protrusion 52 .

Each second protrusion 52 is located in a second groove 62 and matches with the second groove 62 . The technical effects of the second protrusion 52 and the second groove 62 are the same as the technical effects of the first protrusion 51 and the first groove 61 and will not be described again here.

Alternatively, in other embodiments of the present application, as shown in FIG. 8f , the first reinforcement 221 faces the second reinforcement 222 and has the first groove 61 on its surface, and is also provided with at least one second protrusion. From 52. In addition, the second reinforcement 222 faces the first reinforcement 221 and has a surface of the first protrusion 51 and is also provided with at least one second groove 62 .

In addition, taking each reinforcing member in the reinforcing assembly 22 as an example, for example, the first reinforcing member 221 is a hollow frame structure as shown in FIG. 9a or 9b. In the case where the surface of the first reinforcement 221 facing the second reinforcement 222, as shown in Figure 8b, has at least one first protrusion 51, in some embodiments of the present application, as shown in Figure 9a, each The first protrusions 51 may be cylindrical (projected as a circle on the carrier plate 20 ), or have a block structure, and a plurality of first protrusions 51 are evenly distributed on the first reinforcement 221 .

In this case, the second reinforcement 222 is provided with a plurality of first grooves 61 whose number and shape match the first protrusions 51 toward the first reinforcement 221 .

Or, in other embodiments of the present application, as shown in FIG. 9 b , each first protrusion 51 on the surface of the first reinforcement 221 facing the second reinforcement 222 is on the upper surface A1 of the carrier plate 20 . Vertical projection, surrounding the semiconductor device 21 .

In this case, the second reinforcement 222 faces the first groove 61 provided on the first reinforcement 221 that matches the above-mentioned first protrusion 51, and its vertical projection on the upper surface A1 of the carrier plate 20 surrounds provided around the semiconductor device 21 .

It should be noted that the above is an example of the arrangement manner of the first protrusion 51 and the first groove 61 . The arrangement of the second protrusion 52 and the second groove 62 is the same as that described above, and will not be described again here.

Example three

In this example, the same as Example 1, the semiconductor device 21 in the above-mentioned circuit board assembly 100 includes a bare chip 201a, and the carrier board 20 in the circuit board assembly 100 is a packaging substrate 101a.

The reinforcing component 22 is disposed on the upper surface of the packaging substrate 101a. The first adhesive layer 41 with a smaller shear module is used between the reinforcing component 22 and the packaging substrate 101a. In the reinforcement assembly 22, a second adhesive layer 42 with a larger shear module is used between two adjacent reinforcements.

The difference from Example 1 is that, as shown in Figure 10a, the two opposing surfaces of any two adjacent reinforcements in the reinforcement assembly 22 are parallel to each other, and both have an included angle β with the upper surface A1 of the packaging substrate 101a. .

For example, take the reinforcement component 22 including a first reinforcement 221 and a second reinforcement 222. The first reinforcement 221 faces the surface B1 of the second reinforcement 222, and the second reinforcement 222 faces the surface B1 of the first reinforcement 221. Surfaces B2 are parallel to each other.

In this way, the distance between the first reinforcement 221 and the second reinforcement 222 can be equal everywhere. Thus, the thickness of the second adhesive layer 42 used to connect the first reinforcement 221 and the second reinforcement 222 is made uniform. This allows each part of the second adhesive layer 42 to receive uniform force when the reinforcing component 22 warps.

On this basis, there is an included angle β between surfaces B1 and B2 in FIG. 10a and the upper surface A1 of the packaging substrate 101a. In this way, the second adhesive layer 42 used to connect the first reinforcement member 221 and the second reinforcement member 222 can be arranged obliquely.

It can be seen from the above that the colloid has a greater ability to resist force in the longitudinal direction (perpendicular to the upper surface A1 of the packaging substrate 101a), but has a weaker ability to resist shearing in the transverse direction (parallel to the upper surface A1 of the packaging substrate 101a). Therefore, the inclined second adhesive layer 42 can transmit the longitudinal force generated when the reinforcing component 22 warps to the packaging substrate 101a in the longitudinal direction, thereby improving the restraining effect of the reinforcing component 22 on the warping of the packaging substrate 101a.

On this basis, in other embodiments of the present application, as shown in FIG. 10b , a first protrusion 51 can also be provided on the surface of the first reinforcement 221 facing the second reinforcement 222 , and the first protrusion 51 can be provided on the surface of the second reinforcement 222 . A first groove 61 matching the first protrusion 51 is provided toward the surface of the first reinforcement 221 . The arrangement of the first protrusion 51 and the first groove 61 is the same as that described above and will not be described again here.

Alternatively, a second groove 62 can also be provided on the surface of the first reinforcement 221 facing the second reinforcement 222 , and a third groove 62 matching the second groove 62 can be provided on the surface of the second reinforcement 222 facing the first reinforcement 221 . Two bumps 52. The arrangement of the second groove 62 and the second protrusion 52 is the same as that described above, and will not be described again here.

In addition, in other embodiments of the present application, as shown in FIG. 11 a , the reinforcement component 22 includes a first reinforcement 221 , a second reinforcement 222 and at least one intermediate reinforcement 223 .

The surface of the middle reinforcement 223 facing the first reinforcement 221 is parallel to the surface of the middle reinforcement 223 facing the second reinforcement 222 .

Alternatively, in other embodiments of the present application, as shown in FIG. 11 b , the reinforcement component 22 includes a first reinforcement 221 , a second reinforcement 222 and at least two intermediate reinforcements 223 .

Among them, the at least two intermediate reinforcements 223 are respectively a first intermediate reinforcement 223a close to the packaging substrate 101a, and a second intermediate reinforcement 223b far away from the packaging substrate 101a.

The surface C1 of the first intermediate reinforcement 223a facing the first reinforcement 221 intersects the surface C1 of the first intermediate reinforcement 223a facing the second intermediate reinforcement 223b.

The surface D1 of the second intermediate reinforcement 223b facing the first intermediate reinforcement 223a intersects the surface D2 of the second intermediate reinforcement 223b facing the second reinforcement 222.

The above is an example of the manner in which the opposing surfaces of two adjacent reinforcement members in the reinforcement assembly 22 are arranged as inclined surfaces.

As mentioned above, when the reinforcement assembly 22 includes a plurality of intermediate reinforcements 223 , two adjacent reinforcements can also be fixedly connected through the mutual cooperation of the first protrusion 51 and the first groove 61 .

Example 4

In this example, the same as Example 1, the semiconductor device 21 in the above-mentioned circuit board assembly 100 includes a bare chip 201a, and the carrier board 20 in the circuit board assembly 100 is a packaging substrate 101a.

The reinforcing component 22 is disposed on the upper surface of the packaging substrate 101a. The first adhesive layer 41 with a smaller shear module is used between the reinforcing component 22 and the packaging substrate 101a. In the reinforcement assembly 22, a second adhesive layer 42 with a larger shear module is used between two adjacent reinforcements.

The difference from Example 1 is that, as shown in Figure 12a, the chip packaging structure 02a as the circuit board assembly 100 also includes a heat dissipation cover 70 and a heat dissipation glue 71.

The heat dissipation cover 70 is connected to the surface of one of the reinforcement members in the reinforcement assembly 22 facing away from the packaging substrate 101a, and covers the surface of the bare chip 201a facing away from the packaging substrate 101a.

The heat dissipation glue 71 is located between the heat dissipation cover 70 and the bare chip 201a, and is in contact with the heat dissipation cover 70 and the bare chip 201a. Among them, the material constituting the heat dissipation glue 71 includes thermal interface material. Therefore, the heat generated by the bare chip 201a during operation can be transferred to the heat dissipation cover 70 through the heat dissipation glue 71, and the heat can be conducted out of the chip packaging structure 02a through the heat dissipation cover 70.

In addition, the CTE of the heat dissipation cover 70 may be greater than the CTE of the package substrate 101a. Since the CTE of the first reinforcement member 221 in the reinforcement assembly 22 that is closest to the package substrate 101a is smaller than the CTE of the package substrate 101a, there is a mismatch between the CTE of the heat dissipation cover 70 and the CTE of the first reinforcement member 221. In this way, the heat dissipation cover 70 and the reinforcing component 22 can produce warpage in opposite directions to the warpage of the packaging substrate 101a, thereby suppressing the warpage of the packaging substrate 101a.

The following is an example of how to set the heat dissipation cover 70 .

For example, in some embodiments of the present application, the heat dissipation cover 70 may be located on a side surface of the second reinforcement 222 away from the packaging substrate 101a as shown in FIG. 12a.

In this case, in order to cause the direction of warpage of the heat dissipation cover 70 together with the reinforcement assembly 22 to be opposite to the warp direction of the package substrate 101 a , the CTE of the heat dissipation cover 70 is greater than the CTE of the second reinforcement 222 .

In addition, as shown in FIG. 12 b , the chip packaging structure 02 a as the circuit board assembly 100 also includes a plastic encapsulation layer 72 .

The plastic encapsulation layer 72 is located on the upper surface A1 of the packaging substrate 101a and wraps around each side of the bare chip 201a. Wherein, the side surface of the bare chip 201a intersects with the upper surface of the packaging substrate 101a. Being wrapped by the plastic sealing layer 72 can prevent water vapor and impurities in the air from entering the inside of the bare chip 201a, thereby affecting the performance of the bare chip 201a.

In addition, the CTE of the above-mentioned plastic sealing layer 72 may be greater than the CTE of the packaging substrate 101a, so that there is a mismatch between the CTE of the plastic sealing layer 72 and the CTE of the packaging substrate 101a, thereby causing the warpage of the plastic sealing layer 72 and the warpage of the packaging substrate 101a. The curvature direction is opposite to achieve the purpose of suppressing the warpage of the packaging substrate 101a.

Or, in other embodiments of the present application, as shown in FIG. 13 , in the case where the reinforcement assembly 22 at least includes a first reinforcement 221 and a second reinforcement 222 , the heat dissipation cover 70 is located between the first reinforcement 221 and the second reinforcement 222 . between two reinforcements 222.

In this case, in order to cause the direction of warping of the heat dissipation cover 70 together with the reinforcement assembly 22 to be opposite to the warping direction of the package substrate 101a, the CTE of the heat dissipation cover 70 is located between the CTE of the first reinforcement 221 and the second reinforcement. Between 222 CTE.

It should be noted that the heat dissipation cover 70 can be fixedly connected to the reinforcement in the reinforcement assembly 22 through the larger second adhesive layer of the shearing module.

Example five

In this example, the same as Example 1, the semiconductor device 21 in the above-mentioned circuit board assembly 100 includes a bare chip 201a, and the carrier board 20 in the circuit board assembly 100 is a packaging substrate 101a.

The first adhesive layer 41 with a smaller shear module is used between the reinforcing component 22 and the packaging substrate 101a. In the reinforcement assembly 22, a second adhesive layer 42 with a larger shear module is used between two adjacent reinforcements.

The difference from Example 1 is that in this example, as shown in FIG. 14a , the reinforcing component 22 is disposed on the lower surface A2 of the packaging substrate 101a as the carrier 20 and is connected to the lower surface A2 of the packaging substrate 101a.

Taking the reinforcement component 22 as an example, including a first reinforcement 221 close to the packaging substrate 101a and a second reinforcement 222 far away from the packaging substrate 101a, since the CTE of the bare chip 201a is smaller than the CTE of the packaging substrate 101a, in this example, in order to make the reinforcement The warping direction of the component 22 is opposite to the warping direction of the packaging substrate 101a, and the CTE of the first reinforcing member 221 is greater than the CTE of the second reinforcing member 222.

In this way, when the package substrate 101a is heated, the deformation amount is greater than that of the bare chip 201a, and it warps upward, as shown in Figure 14b, the expansion amount of the first reinforcement member 221 is greater than the expansion amount of the second reinforcement member 222, thereby making the reinforcement The downward warping of the component 22 is opposite to the warping direction of the packaging substrate 101a, and the two ends of the packaging substrate 101a are pulled downward to achieve the purpose of suppressing the warping of the packaging substrate 101a.

Or, when the package substrate 101a is cooled and deforms more than the bare chip 201a, and warps downward, as shown in Figure 14c, the shrinkage amount of the first reinforcement member 221 is greater than the shrinkage amount of the second reinforcement member 222, thereby making the reinforcement The upward warping direction of the component 22 is opposite to the warping direction of the packaging substrate 101a, and the two ends of the packaging substrate 101a are pressed upward to achieve the purpose of suppressing the warping of the packaging substrate 101a.

On this basis, in some embodiments of the present application, as shown in Figure 14d, when the reinforcement component 22 includes at least two intermediate reinforcements, such as the first intermediate reinforcement 223a and the second intermediate reinforcement 223b, due to When the CTE of the first reinforcement 221 is greater than the CTE of the second reinforcement 222, the CTE of at least two intermediate reinforcements gradually decreases in the direction approaching the second reinforcement 222.

For example, in Figure 14d, the CTE of the first intermediate reinforcement 223a is smaller than the CTE of the first reinforcement 221 and larger than the CTE of the second intermediate reinforcement 223b. The CTE of the second intermediate reinforcement 223b is smaller than the CTE of the first intermediate reinforcement 223a and greater than the CTE of the second reinforcement 222. In this way, through the plurality of intermediate reinforcements located between the first reinforcement 221 and the second reinforcement 222 , the CTE of the reinforcement component 22 can be gradually reduced in the direction away from the packaging substrate 101 a , thereby facilitating the improvement of the reinforcement component 22 stability.

Example 6

In this example, different from the above-mentioned Examples 1 to 5, in the circuit board assembly 100, the semiconductor device 21 shown in FIG. 2a may be the chip packaging structure 02b shown in FIG. 15a. The chip packaging structure 02b includes a bare chip 201b and a packaging substrate 101b for carrying the bare chip 201b.

In this case, the above-mentioned carrier board 20 in the circuit board assembly 100 may be a PCB 203 as shown in Figure 15a. The chip packaging structure 02 b is electrically connected to the upper surface A1 of the PCB 203 serving as the carrier board 20 through a plurality of second electrical connectors 32 .

Among them, in this example, the CTE of the chip packaging structure 02b is smaller than the CTE of the PCB 203.

In addition, in this example, as shown in FIG. 15a , the reinforcing component 22 is disposed on the upper surface A1 of the PCB 203 and is connected to the upper surface A1 of the PCB 203 .

Taking the reinforcement component 22 as an example, including a first reinforcement 221 close to the PCB 203 and a second reinforcement 222 far away from the PCB 203, since the CTE of the chip packaging structure 02b is smaller than the CTE of the PCB 203, in this example, in order to prevent the warpage of the reinforcement component 22 The direction is opposite to the warping direction of the PCB 203 , and the CTE of the first reinforcement 221 is smaller than the CTE of the second reinforcement 222 .

In this way, when the PCB 203 is heated, the deformation amount is greater than that of the chip packaging structure 02b, and it warps upward, as shown in Figure 15b, the expansion amount of the second reinforcement member 222 is greater than the expansion amount of the first reinforcement member 221, thereby making the reinforcement assembly 22. The downward warping direction is opposite to the warping direction of PCB203. Press both ends of PCB203 downward to suppress the warping of PCB203.

Or, when the PCB 203 is cold, the deformation amount is greater than that of the chip packaging structure 02b, and it warps downward, as shown in Figure 15c, the shrinkage amount of the second reinforcement member 222 is greater than the shrinkage amount of the first reinforcement member 221, so that the reinforcement component 22 The upward warping is opposite to the warping direction of PCB203. Pull both ends of PCB203 upward to suppress the warping of PCB203.

Example 7

This example is the same as Example 6. In the circuit board assembly 100, the semiconductor device 21 is a chip packaging structure 02b. The above-mentioned carrier board 20 in the circuit board assembly 100 is the PCB 203. The CTE of chip package structure 02b is smaller than the CTE of PCB203.

The difference from Example 6 is that, as shown in FIG. 16a , the reinforcing component 22 is disposed on the lower surface A2 of the PCB 203 and is connected to the lower surface A2 of the PCB 203 .

Taking the reinforcement component 22 as an example, including a first reinforcement 221 close to the PCB 203 and a second reinforcement 222 far away from the PCB 203, since the CTE of the chip packaging structure 02b is smaller than the CTE of the PCB 203, in this example, in order to prevent the warpage of the reinforcement component 22 The direction is opposite to the warping direction of the PCB 203 , and the CTE of the first reinforcement 221 is greater than the CTE of the second reinforcement 222 .

In this way, when the PCB 203 is heated, the deformation amount is greater than that of the chip packaging structure 02b, and it warps upward, as shown in Figure 16b, the expansion amount of the first reinforcement member 221 is greater than the expansion amount of the second reinforcement member 222, thereby making the reinforcement assembly 22. The downward warping direction is opposite to the warping direction of PCB203. Pull both ends of PCB203 downward to suppress the warping of PCB203.

Or, when the PCB 203 is cold and deforms more than the chip package structure 02b and warps downward, as shown in Figure 15c, the shrinkage amount of the first reinforcement member 221 is greater than the shrinkage amount of the second reinforcement member 222, thereby strengthening the component. 22 The upward warping is opposite to the warping direction of PCB203. Press both ends of PCB203 upward to suppress the warping of PCB203.

Example 8

This example is the same as Example 6. In the circuit board assembly 100, the semiconductor device 21 is a chip packaging structure 02b. The above-mentioned carrier board 20 in the circuit board assembly 100 is the PCB 203. As shown in Figure 15a, the reinforcing component 22 is disposed on the upper surface A1 of the PCB 203 and is connected to the upper surface A1 of the PCB 203.

The difference from Example 6 is that when the chip packaging structure 02b is filled with more plastic sealing layers 72, the CTE of the chip packaging structure 02b may be greater than the CTE of the PCB 203.

In this case, for example, the reinforcement component 22 includes a first reinforcement 221 close to the PCB 203 and a second reinforcement 222 far away from the PCB 203. Since the CTE of the chip packaging structure 02b is greater than the CTE of the PCB 203, in this example, in order to make the reinforcement The warping direction of the component 22 is opposite to the warping direction of the PCB 203 , and the CTE of the first reinforcement 221 is greater than the CTE of the second reinforcement 222 .

In this way, when the PCB 203 is heated and deforms less than the chip packaging structure 02b and warps downward, as shown in Figure 15c, the expansion of the first reinforcement 221 is greater than the expansion of the second reinforcement 222, thereby making the reinforcement The downward warping of the component 22 is opposite to the warping direction of the PCB 203, and the two ends of the PCB 203 are pulled upward to achieve the purpose of suppressing the warping of the PCB 203.

Or, when the PCB 203 is cold and deforms less than the chip packaging structure 02b and warps upward, as shown in FIG. 15a , the shrinkage amount of the first reinforcement member 221 is greater than the shrinkage amount of the second reinforcement member 222 , so that the reinforcement component 22 The upward warping direction is opposite to the warping direction of PCB203. Press both ends of PCB203 downward to suppress the warping of PCB203.

Example nine

This example is the same as Example 7. In the circuit board assembly 100, the semiconductor device 21 is a chip packaging structure 02b. The above-mentioned carrier board 20 in the circuit board assembly 100 is the PCB 203. As shown in Figure 16a, the reinforcing component 22 is disposed on the lower surface A2 of the PCB 203 and is connected to the lower surface A2 of the PCB 203.

The difference from Example 7 is that when the chip packaging structure 02b is filled with more plastic sealing layers 72, the CTE of the chip packaging structure 02b may be greater than the CTE of the PCB 203.

Taking the reinforcement component 22 as an example, including a first reinforcement 221 close to the PCB 203 and a second reinforcement 222 far away from the PCB 203, since the CTE of the chip packaging structure 02b is smaller than the CTE of the PCB 203, in this example, in order to prevent the warpage of the reinforcement component 22 The direction is opposite to the warping direction of the PCB 203 , and the CTE of the first reinforcement 221 is smaller than the CTE of the second reinforcement 222 .

In this way, when the PCB 203 is heated and the deformation amount is less than the chip packaging structure 02b and warps downward, as shown in Figure 16c, the expansion amount of the second reinforcement member 222 is greater than the expansion amount of the first reinforcement member 221, thereby making the reinforcement The upward warping of the component 22 is opposite to the warping direction of the PCB 203, and the two ends of the PCB 203 are pressed upward to achieve the purpose of suppressing the warping of the PCB 203.

Or, when the PCB 203 is cold and deforms less than the chip packaging structure 02b and warps upward, as shown in FIG. 16b , the shrinkage amount of the second reinforcement member 222 is greater than the shrinkage amount of the first reinforcement member 221 , so that the reinforcement component 22 The downward warping direction is opposite to the warping direction of PCB203. Pull both ends of PCB203 downward to suppress the warping of PCB203.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (18)

1. A circuit board assembly, comprising:

a carrier plate;

The semiconductor device is positioned on the upper surface of the carrier plate;

the reinforcement component is fixed on the carrier plate, and the vertical projection of the reinforcement component on the upper surface of the carrier plate surrounds the semiconductor device;

the reinforcement assembly comprises a laminated structure consisting of at least a first reinforcement and a second reinforcement; the first stiffener is closer to the carrier plate than the second stiffener, the coefficient of thermal expansion CTE of the first stiffener is different from the CTE of the second stiffener, and the CTE of the first stiffener is less than the CTE of the carrier plate;

two opposite surfaces of any two adjacent reinforcing members in the reinforcing assembly are parallel to each other, and an included angle is formed between each reinforcing member and the upper surface of the carrier plate.

2. The circuit board assembly of claim 1, wherein the reinforcement assembly is coupled to an upper surface of the carrier plate;

the CTE of the semiconductor device is less than the CTE of the carrier plate; the CTE of the first stiffener is less than the CTE of the second stiffener;

or,

the CTE of the semiconductor device is greater than the CTE of the carrier plate; the CTE of the first stiffener is greater than the CTE of the second stiffener.

3. The circuit board assembly of claim 1, wherein the carrier plate has a lower surface opposite the upper surface; the reinforcement component is connected with the lower surface;

The CTE of the semiconductor device is less than the CTE of the carrier plate; the CTE of the first stiffener is greater than the CTE of the second stiffener;

or,

the CTE of the semiconductor device is greater than the CTE of the carrier plate; the CTE of the first stiffener is less than the CTE of the second stiffener.

4. A circuit board assembly according to any of claims 1-3, wherein the vertical projection of the reinforcement assembly onto the upper surface of the carrier plate encloses at least three adjacent sides of the semiconductor device;

the side surface of the semiconductor device is intersected with the upper surface of the carrier plate.

5. The circuit board assembly of claim 4, wherein the reinforcement assembly is a hollow frame structure that is joined end to end;

and the vertical projection of the reinforcing component on the upper surface of the carrier plate is enclosed around the semiconductor device.

6. The circuit board assembly of any one of claims 1-3, wherein the reinforcement assembly further comprises at least one intermediate reinforcement member positioned between the first reinforcement member and the second reinforcement member;

the middle reinforcement is connected with the first reinforcement and the second reinforcement;

The CTE of the intermediate stiffener is between the CTE of the first stiffener and the CTE of the second stiffener.

7. The circuit board assembly of claim 6, wherein the reinforcement assembly comprises at least two intermediate stiffeners;

the CTE of the first stiffener is less than the CTE of the second stiffener; the CTE of at least two of the intermediate reinforcements is progressively increased in a direction toward the second reinforcement;

or,

the CTE of the first stiffener is greater than the CTE of the second stiffener; the CTE of at least two of the intermediate stiffeners gradually decreases in a direction toward the second stiffener.

8. A circuit board assembly according to any one of claims 1-3, wherein,

two opposite surfaces of any two adjacent reinforcing members in the reinforcing assembly are respectively provided with at least one first bulge and at least one first groove;

wherein each first protrusion is positioned in one first groove and matched with the first groove.

9. The circuit board assembly of claim 8, wherein the reinforcement assembly is a hollow frame structure that is joined end to end;

the first protrusion and the vertical projection of the first groove on the upper surface of the carrier plate are surrounded on the periphery of the semiconductor device.

10. The circuit board assembly according to claim 8, wherein one of the two opposite surfaces of any adjacent two of the reinforcement members of the reinforcement assembly, having the first protrusion, is further provided with at least one second recess, and the other surface having the first recess is further provided with at least one second protrusion;

wherein each second protrusion is positioned in one second groove and matched with the second groove.

11. The circuit board assembly of claim 1, wherein the reinforcement assembly comprises a first reinforcement, a second reinforcement, and at least one intermediate reinforcement;

the surface of the intermediate reinforcement facing the first reinforcement is parallel to the surface of the intermediate reinforcement facing the second reinforcement.

12. The circuit board assembly of claim 1, wherein the reinforcement assembly comprises a first reinforcement, a second reinforcement, and at least two intermediate reinforcements; the at least two middle reinforcements are respectively a first middle reinforcement close to the carrier plate and a second middle reinforcement far away from the carrier plate;

a surface of the first intermediate reinforcement facing the first reinforcement intersecting a surface of the first intermediate reinforcement facing the second intermediate reinforcement;

The surface of the second intermediate reinforcement facing the first intermediate reinforcement intersects the surface of the second intermediate reinforcement facing the second reinforcement.

13. The circuit board assembly of any of claims 1-3, wherein the carrier is a package substrate and the semiconductor device is a bare chip;

the circuit board assembly further includes:

the heat dissipation cover is connected with the surface of one reinforcement piece in the reinforcement assembly, which faces away from the packaging substrate, and covers the surface of the bare chip, which faces away from the packaging substrate; the CTE of the heat spreader lid is greater than the CTE of the package substrate;

the heat dissipation glue is positioned between the heat dissipation cover and the bare chip and is contacted with the heat dissipation cover and the bare chip; the material comprising the heat-dissipating glue comprises a thermal interface material.

14. The circuit board assembly of claim 13 wherein the circuit board assembly comprises,

the heat dissipation cover is positioned between the first reinforcement and the second reinforcement; the CTE of the heat dissipating cover is between the CTE of the first stiffener and the CTE of the second stiffener;

or, the heat dissipation cover is positioned on one side surface of the second reinforcement, which faces away from the packaging substrate; the heat dissipating cover has a CTE greater than a CTE of the second stiffener.

15. The circuit board assembly of claim 13, wherein the circuit board assembly further comprises:

the plastic layer is positioned on the upper surface of the packaging substrate and wraps all sides of the bare chip; the CTE of the plastic layer is larger than that of the packaging substrate;

the side surface of the bare chip is intersected with the upper surface of the packaging substrate.

16. A circuit board assembly according to any one of claims 1-3, wherein,

the circuit board assembly further includes:

the first bonding layer is positioned between the carrier plate and the reinforcing component and is used for connecting the carrier plate with the reinforcing component;

the second adhesive layer is positioned between two adjacent reinforcement members in the reinforcement assembly and is used for connecting the two adjacent reinforcement members;

wherein the shear modulus of the first adhesive layer is less than the shear modulus of the second adhesive layer.

17. A circuit board assembly according to any of claims 1-3, wherein the equivalent CTE of the reinforcement assembly is less than the CTE of the carrier plate;

the equivalent CTE of the reinforcement component is (Σα _j ×E _j ×V _j )/(ΣE _j ×V _j )；

Wherein alpha is _j CTE of a material of the reinforcement assembly adjacent to the j-th layer of reinforcement of the carrier plate;

E _j Young's modulus of a j-th layer of reinforcement in the reinforcement component, which is close to the carrier plate;

V _j the bulk specific gravity of the j-th layer reinforcement in the reinforcement component, which is close to the carrier plate;

j is greater than or equal to 1, and j is a positive integer.

18. An electronic device comprising a carrier plate and the circuit board assembly of any one of claims 1-17 mounted on the carrier plate.