CN113284527B - Clock data recovery circuit, memory storage device and signal adjustment method - Google Patents

Abstract

The invention provides a clock data recovery circuit, a memory storage device and a signal adjustment method. The method includes: detecting the phase difference between the first signal and the clock signal; generating a voting signal based on the phase difference and the first clock frequency; and sequentially outputting a plurality of adjustment signals based on the voting signal and the second clock frequency. , wherein the first clock frequency is different from the second clock frequency; and the clock signal is generated according to the plurality of adjustment signals output sequentially.

Description

Clock data recovery circuit, memory storage device and signal adjustment method

Technical field

The present invention relates to a signal adjustment technology, and in particular to a clock data recovery circuit, a memory storage device and a signal adjustment method.

Background technique

Digital cameras, mobile phones and MP3 players have grown rapidly in recent years, causing consumer demand for storage media to increase rapidly. Since the rewriteable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatile data, power saving, small size, and no mechanical structure, it is very suitable for built-in Among the various portable multimedia devices exemplified above.

Generally speaking, memory storage devices have built-in clock and data recovery (Clock and Data Recovery, CDR) circuits to correct data signals and clock signals. As the transmission frequency of data signals continues to increase, the clock correction efficiency and jitter suppression of the clock data recovery circuit are becoming more important. In some cases, when the phase difference or frequency difference between the data signal and the clock signal is large, the jitter tolerance of the clock data recovery circuit may be caused by the instantaneous adjustment of the phase or frequency being too large. decline.

Contents of the invention

The present invention provides a clock data recovery circuit, a memory storage device and a signal adjustment method, which can improve the jitter tolerance of the clock data recovery circuit.

Exemplary embodiments of the present invention provide a clock data recovery circuit, which includes a phase detector, a voting circuit, a digital loop filter, and a phase interpolator. The phase detector is used to detect the phase difference between the first signal and the clock signal. The voting circuit is connected to the phase detector and used to generate a voting signal according to the phase difference and the first clock frequency. The digital loop filter is connected to the voting circuit and used to sequentially output a plurality of adjustment signals according to the voting signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency. The phase interpolator is connected to the phase detector and the digital loop filter and is used to generate the clock signal according to the plurality of adjustment signals output sequentially.

In an exemplary embodiment of the present invention, the digital loop filter includes an accumulation circuit and a dividing circuit. The accumulation circuit is connected to the voting circuit. The dividing circuit is connected to the accumulation circuit. The accumulation circuit is used to determine a first adjustment code according to the voting signal and the first clock frequency. The dividing circuit is used to divide the first adjustment code into a plurality of second adjustment codes and generate the plurality of adjustment signals according to the plurality of second adjustment codes.

In an exemplary embodiment of the present invention, the digital loop filter further includes a multiplexer. The multiplexer is connected to the dividing circuit and the phase interpolator and is used to sequentially output the plurality of adjustment signals to the phase interpolator according to the second clock frequency.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, a memory control circuit unit and a clock data recovery circuit. The connection interface unit is used to connect to the host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The clock data recovery circuit is provided in at least one of the connection interface unit, the rewritable non-volatile memory module and the memory control circuit unit. The clock data recovery circuit is used to detect the phase difference between the first signal and the clock signal. The clock data recovery circuit is further used to generate a voting signal based on the phase difference and the first clock frequency. The clock data recovery circuit is further configured to sequentially output a plurality of adjustment signals according to the voting signal and the second clock frequency. The clock data recovery circuit is further used to generate the clock signal according to the plurality of adjustment signals output sequentially. The first clock frequency is different from the second clock frequency.

In an exemplary embodiment of the present invention, the clock data recovery circuit includes an accumulation circuit and a dividing circuit. The dividing circuit is connected to the accumulation circuit. The accumulation circuit is used to determine a first adjustment code according to the voting signal and the first clock frequency. The dividing circuit is used to divide the first adjustment code into a plurality of second adjustment codes and generate the plurality of adjustment signals according to the plurality of second adjustment codes.

In an exemplary embodiment of the present invention, the clock data recovery circuit further includes a multiplexer. The multiplexer is connected to the dividing circuit and used to sequentially output the plurality of adjustment signals to the phase interpolator in the clock data recovery circuit according to the second clock frequency.

Exemplary embodiments of the present invention further provide a signal adjustment method for use in a memory storage device. The memory storage device has a rewritable non-volatile memory module, and the signal adjustment method includes: detecting a phase difference between a first signal and a clock signal; and generating a voting signal according to the phase difference and the first clock frequency. ; Sequentially outputting a plurality of adjustment signals according to the voting signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the plurality of adjustment signals according to the sequential output. the clock signal.

In an exemplary embodiment of the present invention, the step of sequentially outputting the plurality of adjustment signals according to the voting signal and the second clock frequency includes: determining the first clock frequency according to the voting signal and the first clock frequency. an adjustment code; and dividing the first adjustment code into a plurality of second adjustment codes and generating the plurality of adjustment signals according to the plurality of second adjustment codes.

In an exemplary embodiment of the present invention, the step of sequentially outputting the plurality of adjustment signals according to the voting signal and the second clock frequency further includes: adjusting the plurality of adjustment signals according to the second clock frequency. The signals are sequentially output to the phase interpolator in the memory storage device.

In an exemplary embodiment of the present invention, the plurality of adjustment signals output sequentially are used to gradually adjust the clock signal to meet the target phase difference or target frequency difference.

An exemplary embodiment of the present invention further provides a clock data recovery circuit, which includes a phase detector, a voting circuit, a bit loop filter and a phase interpolator. The voting circuit is connected to the output of the phase detector. The digital loop filter is connected to the output of the voting circuit. The phase interpolator is connected to the output of the digital loop filter and the phase detector. The voting circuit operates at a first clock frequency. The digital loop filter operates at a second clock frequency. The first clock frequency is different from the second clock frequency.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, a memory control circuit unit and a clock data recovery circuit. The connection interface unit is used to connect to the host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The clock data recovery circuit is provided in at least one of the connection interface unit, the rewritable non-volatile memory module and the memory control circuit unit. The voting circuit in the clock data recovery circuit operates at a first clock frequency. The digital loop filter in the clock data recovery circuit operates at the second clock frequency. The digital loop filter is connected to the output of the voting circuit. The first clock frequency is different from the second clock frequency.

In an exemplary embodiment of the present invention, the first clock frequency is lower than the second clock frequency.

Based on the above, after measuring the phase difference between the first signal and the clock signal, the voting circuit may generate a voting signal according to the phase difference and the first clock frequency. The digital loop filter can sequentially output a plurality of adjustment signals according to the voting signal and a second clock frequency, and the first clock frequency is different from the second clock frequency. The phase interpolator may generate the clock signal according to the plurality of adjustment signals output sequentially. In this way, the jitter tolerance of the clock data recovery circuit can be improved.

Description of the drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention;

FIG. 1 is a schematic diagram of a clock data recovery circuit according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic diagram of a digital loop filter according to an exemplary embodiment of the present invention;

FIG. 3 is a schematic diagram of sequentially outputting multiple adjustment signals according to an exemplary embodiment of the present invention;

FIG. 4 is a schematic diagram of adjusting a clock signal according to a plurality of adjustment signals output sequentially according to an exemplary embodiment of the present invention;

Figure 5 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention;

Figure 6 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention;

Figure 7 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention;

Figure 8 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 9 is a flow chart of a signal adjustment method according to an exemplary embodiment of the present invention.

Explanation of reference numbers

10: Clock data recovery circuit;

11: Phase detector;

12: Voting circuit;

13: Digital loop filter;

14: Phase interpolator;

15: Phase locked loop circuit;

Din,PS,UP,DN,PC(i),PC(1)～PC(n),PC(D),CLK(HS),CLK(LS),CLK(REF): signal;

21: Accumulation circuit;

22: Split circuit;

23: Multiplexer;

201,202: Amplifier;

211,212: Accumulator;

221: Adder;

T(0),T(1),T(01)～T(05): time point;

50,70,80: memory storage device;

51,71: Host system;

510: system bus;

511: processor;

512: Random access memory;

513: read-only memory;

514: Data transmission interface;

52: Input/output (I/O) device;

60: motherboard;

601:U disk;

602: memory card;

603:Solid state drive;

604: Wireless memory storage device;

605: Global positioning system module;

606: Network interface card;

607: Wireless transmission device;

608:Keyboard;

609: screen;

610: Trumpet;

72:SD card;

73: CF card;

74: Embedded storage device;

741: Embedded multimedia card;

742: Embedded multi-chip package storage device;

801: Connect interface unit;

802: Memory control circuit unit;

803: Rewritable non-volatile memory module;

S901: Step (detect the phase difference between the first signal and the clock signal);

S902: Step (generate a voting signal based on the phase difference and the first clock frequency);

S903: Step (sequentially output multiple adjustment signals according to the voting signal and the second clock frequency, wherein the first clock frequency is different from the second clock frequency);

S904: Step (generate the clock signal according to the plurality of adjustment signals output sequentially).

Detailed ways

Several exemplary embodiments are provided below to illustrate the present invention. However, the present invention is not limited to the illustrated exemplary embodiments. Appropriate combinations between the exemplary embodiments are also allowed. The word "connection" used throughout the description of this case (including the claims) can refer to any direct or indirect means of connection. For example, if a first device is described as being connected to a second device, it should be understood that the first device can be directly connected to the second device, or the first device can be indirectly connected through other devices or some connection means. ground to the second device. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.

FIG. 1 is a schematic diagram of a clock data recovery circuit according to an exemplary embodiment of the present invention. Please refer to FIG. 1 , the clock data recovery circuit 10 can be used to receive the signal (also called the first signal) Din and generate the signal CLK (HS). Signal CLK(HS) is the clock signal.

The clock data recovery circuit 10 can detect the phase difference between the signal Din and CLK(HS) and adjust the signal CLK(HS) according to the phase difference. For example, the clock data recovery circuit 10 may adjust the phase and/or frequency of the signal CLK(HS) according to the phase and/or frequency of the signal Din. Thereby, the clock data recovery circuit 10 can be used to lock the signals Din and CLK(HS) into a preset phase relationship. For example, the phase difference between signals Din and CLK(HS) can be locked at 0 degrees, 90 degrees, 180 degrees, 270 degrees, or 360 degrees. In an example embodiment, the signal Din may be a data signal. The locked signal CLK(HS) can also be used to analyze (eg, sample) the signal Din to obtain the bit data (eg, bit 1/0) conveyed by the signal Din.

The clock data recovery circuit 10 includes a phase detector 11 , a voting circuit 12 , a digital loop filter 13 and a phase interpolator 14 . The phase detector 11 can be used to receive the signals Din and CLK(HS) and detect the phase difference between the signals Din and CLK(HS). The phase detector 11 can generate a signal PS based on the measured phase difference. In other words, the signal PS may reflect the phase difference between the signals Din and CLK(HS).

Voting circuit 12 is connected to phase detector 11 and can receive signal PS. The voting circuit 12 may generate the signal UP/DN based on the signal PS. Signal UP/DN can be used to change the phase and/or frequency of signal CLK(HS). For example, signal UP may be used to advance at least one rising edge and/or at least one falling edge of signal CLK(HS). Signal DN may be used to delay at least one rising edge and/or at least one falling edge of signal CLK(HS). In an example embodiment, the signals UP/DN are also called voting signals.

Digital loop filter 13 is connected to voting circuit 12 . Digital loop filter 12 may receive signal UP/DN and generate signal PC(i) based on signal UP/DN. Signal PC(i) can correspond to a code (or control code). This code (or control code) can be used to control the phase and/or frequency of signal CLK(HS). In an example embodiment, signal PC(i) is also called an adjustment signal.

The phase interpolator 14 is connected to the digital loop filter 13 , the phase detector 11 and the phase locked loop (PhaseLocked Loop, PLL) circuit 15 . The phase interpolator 14 is used to receive the signal PC(i) from the digital loop filter 13 and the signal CLK(REF) from the phase locked loop circuit 15 . The signal CLK(REF) is also called the reference clock signal. For example, signal CLK(REF) may serve as the basis for phase interpolator 14 . Phase interpolator 14 may perform phase interpolation on signal CLK(REF) based on signal PC(i) to generate signal CLK(HS). Additionally, phase interpolator 14 may adjust the phase and/or frequency of signal CLK(HS) based on signal PC(i). The phase locked loop circuit 15 may be included in the clock data recovery circuit 10 or be independent of the clock data recovery circuit 10, which is not limited by the present invention.

Through the cooperative operation of the phase detector 11, voting circuit 12, digital loop filter 13 and phase interpolator 14, the signals Din and CLK(HS) can be locked in the preset phase relationship to facilitate subsequent signal analysis. . In addition, the signal CLK(HS) can also be provided to other circuit components.

It should be noted that the voting circuit 12 can operate at a certain clock frequency (also called a first clock frequency), and the digital loop filter 13 can operate at another clock frequency (also called a second clock frequency). From another perspective, the digital loop filter 13 can operate at the first clock frequency and the second clock frequency simultaneously. The first clock frequency is different from the second clock frequency. For example, the first clock frequency may be lower than the second clock frequency. For example, the first clock frequency may be 20 MHz, and the second clock frequency may be 100 MHz, and the present invention does not limit the actual values of the first clock frequency and the second clock frequency.

In an exemplary embodiment, the voting circuit 12 may receive the signal CLK(LS) and use the frequency of the signal CLK(LS) as the first clock frequency. The voting circuit 12 may output the signal UP/DN according to the frequency of the signal CLK(LS) and the signal PS. For example, voting circuit 12 may be triggered by the rising edge and/or falling edge of signal CLK(LS) to generate signal PS.

In an exemplary embodiment, the digital loop filter 13 may receive the signal CLK(HS) and use the frequency of the signal CLK(HS) as the second clock frequency. The digital loop filter 13 can output the signal UP/DN according to the frequency of the signal CLK(HS) and the signal UP/DN. For example, the digital loop filter 13 may be triggered by the rising edge and/or falling edge of the signal CLK(HS) to output the signal PC(i).

In an exemplary embodiment, the signal CLK(LS) is generated by dividing the signal CLK(HS), for example. For example, a frequency divider (Divider) can be used to divide the signal CLK(HS) to generate the signal CLK(LS). The frequency divider may be included in the clock data recovery circuit 10 or be independent of the clock data recovery circuit 10 .

In an example embodiment, the value of i ranges from 1 to n, and n is an integer greater than 1. The second clock frequency may be approximately n times the first clock frequency. In response to a signal UP/DN generated by the voting circuit 12, the digital loop filter 13 can sequentially output n signals PC(1)˜PC(n) according to the frequency of the signal UP/DN and the signal CLK(HS). to phase interpolator 14. The phase interpolator 14 can generate the signal CLK(HS) and/or adjust the phase (or frequency) of the signal CLK(HS) according to the n signals PC(1)˜PC(n) outputted sequentially. In this way, the n signals PC(1)~PC(n) sequentially output can be used to gradually adjust the signal CLK(HS) to meet a phase difference (also called a target phase difference) or a frequency difference (also called a target phase difference). target frequency difference).

FIG. 2 is a schematic diagram of a digital loop filter according to an exemplary embodiment of the present invention. Referring to FIG. 2 , the digital loop filter 13 may include an accumulation circuit 21 , a dividing circuit 22 and a multiplexer 23 . The accumulation circuit 21 can determine an adjustment code (also called a first adjustment code) based on the signal UP/DN and the first clock frequency. The dividing circuit 22 is connected to the accumulation circuit 21 and the multiplexer 23 . The dividing circuit 22 can divide the first adjustment code into a plurality of adjustment codes (also referred to as second adjustment codes) and generate signals PC(1)˜PC(n) according to the plurality of second adjustment codes. The multiplexer 23 can sequentially output the signals PC(1)˜PC(n) according to the second clock frequency.

From another perspective, part of the circuits of the digital loop filter 13 (ie, the accumulation circuit 21 and the dividing circuit 22) operate at the first clock frequency and operate according to the first clock frequency (for example, generating signals PC(1)˜PC( n)). Another part of the circuit of the digital loop filter 13 (ie, the multiplexer 23) operates at the second clock frequency and operates according to the second clock frequency (for example, the output signal PC(i)).

In an exemplary embodiment, the accumulation circuit 21 includes an amplifier 201, an amplifier 202, an accumulator 211, an accumulator 212 and an adder 221. The input terminals of the amplifiers 201 and 202 may be connected to the output terminal of the phase detector 11 of FIG. 1 to receive the signal UP/DN. The input of accumulator 211 may be connected to the output of amplifier 202 . The output terminals of the accumulator 211 and the amplifier 201 may be connected to the input terminal of the adder 221 . The input terminal of the accumulator 212 may be connected to the output terminal of the adder 221 . The output of accumulator 212 may be connected to the input of dividing circuit 22 .

In an exemplary embodiment, amplifier 201 is also called a proportional gain amplifier, and amplifier 202 is also called an integral gain amplifier. For example, the amplifier 201 can amplify the value corresponding to the signal UP/DN by N times, and the amplifier 202 can amplify the value corresponding to the signal UP/DN by M times. N is greater than M. For example, N may be 6 and/or M may be 4, and the values of N and M are not limited thereto. The value amplified by M times by the amplifier 202 can be used to update the value stored in the accumulator 211 . The adder 221 can add the value stored in the accumulator 211 to the value output by the amplifier 201 and update the value stored in the accumulator 212 according to the operation result. This value is the first adjustment code. The accumulation circuit 21 may receive the signal CLK(LS) and update the first adjustment code according to the frequency of the signal CLK(LS) (ie, the first clock frequency). Then, the accumulation circuit 21 may transmit the signal corresponding to the first adjustment code to the dividing circuit 22 .

According to the output of the accumulation circuit 21, the dividing circuit 22 can generate signals PC(1)˜PC(n). Each of the signals PC(1)˜PC(n) corresponds to a second adjustment code. In an exemplary embodiment, assuming that a first adjustment code can be used individually and once to adjust the signal CLK(HS) to meet a target phase difference or target frequency difference, then the signals PC(1)˜PC(n) All corresponding second adjustment codes can jointly and gradually adjust the signal CLK(HS) to meet the target phase difference or target frequency difference.

FIG. 3 is a schematic diagram of sequentially outputting multiple adjustment signals according to an exemplary embodiment of the present invention. FIG. 4 is a schematic diagram of adjusting a clock signal according to a plurality of adjustment signals output sequentially according to an exemplary embodiment of the present invention.

Referring to Figures 3 and 4, it is assumed that the signal PC(D) traditionally corresponding to the first adjustment code (i.e., the adjustment signal) can be output according to the triggering of the signal CLK(LS), and the signal PC(D) can indicate that Figure 1 The phase interpolator 14 adjusts the phase (or frequency) of the signal CLK (HS) from the current value PH (1) to the target value PH (2) at one time between time points T (0) ~ T (1). . The difference between the current value PH(1) and the target value PH(2) is ΔPH (ie, target phase difference or target frequency difference).

In an exemplary embodiment, the signals PC(1)˜PC(n) are sequentially output according to the triggering of the signal CLK(HS). According to the sequentially output signals PC(1)~PC(n), at time points T(01)~T(05), the phase (or frequency) of the signal CLK(HS) is gradually changed from the current value PH(1) and Stably adjust to the target value PH(2). The difference between the current value PH(1) and the target value PH(2) is also ΔPH (ie, target phase difference or target frequency difference).

In an example embodiment, assume n=5. At time point T(01), in response to signal PC(1), the phase (or frequency) of signal CLK(HS) is adjusted from the current value PH(1) to PH(1)+ΔPH×(1/5); At time point T(02), in response to signal PC(2), the phase (or frequency) of signal CLK(HS) is adjusted to PH(1)+ΔPH×(2/5); at time point T(03) , in response to signal PC(3), the phase (or frequency) of signal CLK(HS) is adjusted to PH(1)+ΔPH×(3/5); at time point T(04), in response to signal PC(4 ), the phase (or frequency) of the signal CLK(HS) is adjusted to PH(1)+ΔPH×(4/5); and, at time point T(05), in response to the signal PC(5), the signal CLK( The phase (or frequency) of HS) is adjusted to PH(1)+ΔPH=PH(2).

Compared with adjusting the signal CLK(HS) all at once according to the signal PC(D), the phase (or frequency) of the signal CLK(HS) is stably adjusted according to the sequentially output signals PC(1)~PC(n). To the target value PH(2), the clock data recovery circuit 10 of FIG. 1 can have higher jitter tolerance. In particular, the larger ΔPH (ie, the target phase difference or the target frequency difference) is, the more advantageous the advantage of adjusting the signal CLK(HS) in stages can be highlighted.

In an exemplary embodiment, the clock data recovery circuit 10 of FIG. 1 may be disposed in a memory storage device to receive the signal Din from the host system. However, in another exemplary embodiment, the clock data recovery circuit 10 of FIG. 1 can also be provided in other types of electronic devices, and is not limited to memory storage devices.

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rerewritable non-volatile memory module) and a controller (also called a control circuit). Typically a memory storage device is used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 5 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 6 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIGS. 5 and 6 , the host system 51 generally includes a processor 511 , a random access memory (RAM) 512 , a read only memory (ROM) 513 and a data transmission interface 514 . The processor 511 , the random access memory 512 , the read-only memory 513 and the data transmission interface 514 are all connected to a system bus 510 .

In this exemplary embodiment, the host system 51 is connected to the memory storage device 50 through the data transmission interface 514 . For example, host system 51 may store data to or read data from memory storage device 50 via data transfer interface 514 . In addition, the host system 51 is connected to the I/O device 52 through the system bus 510 . For example, host system 51 may transmit output signals to or receive input signals from I/O device 52 via system bus 510 .

In an example embodiment, the processor 511 , the random access memory 512 , the read-only memory 513 and the data transmission interface 514 may be disposed on the motherboard 60 of the host system 51 . The number of data transmission interfaces 514 may be one or more. Through the data transmission interface 514, the motherboard 60 can be connected to the memory storage device 50 via wired or wireless means. The memory storage device 50 may be, for example, a U disk 601, a memory card 602, a solid state drive (SSD) 603 or a wireless memory storage device 604. The wireless memory storage device 604 may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a low-power Bluetooth memory storage device (eg, iBeacon ) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 60 can also be connected to various I/Os such as a Global Positioning System (GPS) module 605, a network interface card 606, a wireless transmission device 607, a keyboard 608, a screen 609, a speaker 610, etc. through the system bus 510. device. For example, in an exemplary embodiment, the motherboard 60 can access the wireless memory storage device 604 through the wireless transmission device 607 .

In an example embodiment, the host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiments, the host system is described as a computer system, FIG. 7 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Please refer to FIG. 7 . In another exemplary embodiment, the host system 71 may also be a digital camera, video camera, communication device, audio player, video player or tablet computer, and the memory storage device 70 may be used therefor. Various non-volatile memory storage devices such as Secure Digital (SD) card 72, Compact Flash (CF) card 73 or embedded storage device 74. The embedded storage device 74 includes an embedded Multi Media Card (eMMC) 741 and/or an embedded Multi Chip Package (eMCP) storage device 742 and other types of substrates that directly connect the memory module to the host system. embedded storage device.

FIG. 8 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG. 8 , the memory storage device 80 includes a connection interface unit 801 , a memory control circuit unit 802 and a rewritable non-volatile memory module 803 . It should be noted that the clock data recovery circuit 10 of FIG. 1 can be disposed in the connection interface unit 801 to receive the signal Din from the host system 51 . Alternatively, the clock data recovery circuit 10 of FIG. 1 can also be provided in the memory control circuit unit 802 and/or the rewritable non-volatile memory module 803, which is not limited by the present invention.

The connection interface unit 801 is used to connect the memory storage device 80 to the host system. In this exemplary embodiment, the connection interface unit 801 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 801 may also be in compliance with the Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, high-speed peripheral component interface (Peripheral Component Interconnect Express, PCIExpress) standard, universal serial bus (Universal Serial Bus, USB) standard, SD interface standard, ultra high speed generation (Ultra High Speed-I, UHS-I) interface Standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Memory (Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 801 and the memory control circuit unit 802 may be packaged in a chip, or the connection interface unit 801 may be arranged outside a chip including the memory control circuit unit 802.

The memory control circuit unit 802 is used to execute multiple logic gates or control instructions implemented in hardware or firmware and write and read data in the rewritable non-volatile memory module 803 according to the instructions of the host system. and erase operations.

The rewritable non-volatile memory module 803 is connected to the memory control circuit unit 802 and used to store data written by the host system. The rewritable non-volatile memory module 803 may be a single-level cell (SLC) NAND flash memory module (that is, a flash memory module that can store 1 bit in one memory cell), a multi-level memory module Multi Level Cell (MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in one memory cell), Triple Level Cell (TLC) NAND flash memory module (that is, a flash memory module that can store 3 bits in one storage unit), a Quad Level Cell (QLC) NAND flash memory module (that is, a flash memory module that can store 4 bits in one storage unit) flash memory module), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 803 stores one or more bits based on changes in voltage (hereinafter also referred to as critical voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell." As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple memory states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the storage units of the rewritable non-volatile memory module 803 will constitute multiple physical programming units, and these physical programming units will constitute multiple physical erasure units. Specifically, memory cells on the same word line will form one or more physical programming units. If each storage unit can store more than 2 bits, the physical programming units on the same word line can at least be classified into lower physical programming units and upper physical programming units. For example, the Least Significant Bit (LSB) of a memory unit belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory unit belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit will be greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. Reliability of programmed units.

In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the entity programming unit is an entity page (page) or an entity sector (sector). If the entity programming units are entity pages, these entity programming units usually include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors to store user data, while the redundant bit area is used to store system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other example embodiments, the data bit zone may also include 8, 16, or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of memory cells that are erased together. For example, the physical erasure unit is a physical block.

FIG. 9 is a flow chart of a signal adjustment method according to an exemplary embodiment of the present invention. Referring to FIG. 9 , in step S901 , the phase difference between the first signal and the clock signal is detected. In step S902, a voting signal is generated according to the phase difference and the first clock frequency. In step S903, a plurality of adjustment signals are output sequentially according to the voting signal and a second clock frequency, where the first clock frequency is different from the second clock frequency. In step S904, the clock signal is generated according to the plurality of adjustment signals output sequentially.

However, each step in Figure 9 has been described in detail above and will not be described again here. It is worth noting that each step in Figure 9 can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. In addition, the method in Figure 9 can be used in conjunction with the above example embodiments or can be used alone, and is not limited by the present invention.

To sum up, in the exemplary embodiment of the present invention, the voting circuit can operate at a first clock frequency, and the digital loop filter can operate at a higher second clock frequency, so as to generate multiple signals in response to a voting signal. an adjustment signal. These adjustment signals can be used to adjust the clock signal generated by the clock data recovery circuit multiple times to meet the target phase difference or frequency difference. Compared with the traditional adjustment of the clock signal once, in the exemplary embodiment of the present invention, the clock signal is adjusted multiple times, so that the clock data recovery circuit has higher jitter tolerance.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention, but not to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention. scope.

Claims (16)

1. A clock data recovery circuit, comprising:

a phase detector for detecting a phase difference between the first signal and the clock signal;

voting circuit, connect to stated phase detector and use for according to stated phase difference and first clock frequency produce the voting signal;

a digital loop filter connected to the voting circuit and configured to sequentially output a plurality of adjustment signals according to the voting signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and

a phase interpolator connected to the phase detector and the digital loop filter for generating the clock signal according to the plurality of adjustment signals sequentially output,

wherein the digital loop filter comprises:

an accumulation circuit connected to the voting circuit; and

a dividing circuit connected to the accumulating circuit,

the accumulation circuit is used for determining a first adjustment code according to the voting signal and the first clock frequency, and

the dividing circuit is used for dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals according to the plurality of second adjusting codes.

2. The clock data recovery circuit of claim 1, wherein the first clock frequency is lower than the second clock frequency.

3. The clock data recovery circuit of claim 1, wherein the digital loop filter further comprises:

and the multiplexer is connected to the dividing circuit and the phase interpolator and is used for outputting the plurality of adjustment signals to the phase interpolator in sequence according to the second clock frequency.

4. The clock data recovery circuit of claim 1, wherein the plurality of sequentially output adjustment signals are used to gradually adjust the clock signal to meet a target phase difference or a target frequency difference.

5. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module;

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

a clock data recovery circuit arranged in at least one of the connection interface unit, the rewritable nonvolatile memory module and the memory control circuit unit,

wherein the clock data recovery circuit is configured to detect a phase difference between the first signal and the clock signal,

the clock data recovery circuit is used for generating a voting signal according to the phase difference and a first clock frequency,

the clock data recovery circuit is used for outputting a plurality of adjusting signals according to the voting signal and the second clock frequency in sequence,

the clock data recovery circuit is used for generating the clock signal according to the plurality of adjustment signals which are sequentially output, and

the first clock frequency is different from the second clock frequency,

wherein the clock data recovery circuit comprises:

an accumulation circuit; and

a dividing circuit connected to the accumulating circuit;

the accumulation circuit is used for determining a first adjustment code according to the voting signal and the first clock frequency, and

the dividing circuit is used for dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals according to the plurality of second adjusting codes.

6. The memory storage device of claim 5, wherein the first clock frequency is lower than the second clock frequency.

7. The memory storage device of claim 5, wherein the clock data recovery circuit further comprises:

and the multiplexer is connected to the dividing circuit and used for outputting the plurality of adjustment signals to the phase interpolator in the clock data recovery circuit in sequence according to the second clock frequency.

8. The memory storage device of claim 5, wherein the plurality of adjustment signals output in sequence are used to gradually adjust the clock signal to meet a target phase difference or a target frequency difference.

9. A signal conditioning method for a memory storage device having a rewritable non-volatile memory module, the signal conditioning method comprising:

detecting a phase difference between the first signal and the clock signal;

generating a voting signal according to the phase difference and the first clock frequency;

sequentially outputting a plurality of adjustment signals according to the voting signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and

generating the clock signal according to the plurality of adjustment signals sequentially output,

wherein the step of sequentially outputting the plurality of adjustment signals according to the voting signal and the second clock frequency comprises:

determining a first adjustment code according to the voting signal and the first clock frequency; and

dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals according to the plurality of second adjusting codes.

10. The signal conditioning method of claim 9, wherein the first clock frequency is lower than the second clock frequency.

11. The signal conditioning method according to claim 9, wherein the step of sequentially outputting the plurality of conditioning signals according to the voting signal and the second clock frequency further comprises:

the plurality of adjustment signals are sequentially output to a phase interpolator in the memory storage device according to the second clock frequency.

12. The signal conditioning method according to claim 9, wherein the plurality of conditioning signals sequentially output are used to progressively condition the clock signal to meet a target phase difference or a target frequency difference.

13. A clock data recovery circuit comprising:

a phase detector;

voting circuitry connected to the phase detector;

a digital loop filter connected to the voting circuit; and

a phase interpolator coupled to the digital loop filter and the phase detector,

wherein the voting circuit operates at a first clock frequency,

the digital loop filter operates at a second clock frequency and

the first clock frequency is different from the second clock frequency,

wherein the digital loop filter comprises:

an accumulation circuit connected to the voting circuit; and

a dividing circuit connected to the accumulating circuit,

the accumulation circuit is used for determining a first adjustment code according to the voting signal generated by the voting circuit and the first clock frequency, and

the dividing circuit is used for dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals which are sequentially output to the phase interpolator according to the plurality of second adjusting codes.

14. The clock data recovery circuit of claim 13, wherein the first clock frequency is lower than the second clock frequency.

15. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module;

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

a clock data recovery circuit arranged in at least one of the connection interface unit, the rewritable nonvolatile memory module and the memory control circuit unit,

wherein the voting circuit in the clock data recovery circuit operates at a first clock frequency,

the digital loop filter in the clock data recovery circuit operates at a second clock frequency,

the digital loop filter is connected to the voting circuit, and

the first clock frequency is different from the second clock frequency,

wherein the digital loop filter comprises:

an accumulation circuit connected to the voting circuit; and

a dividing circuit connected to the accumulating circuit,

the accumulation circuit is used for determining a first adjustment code according to the voting signal generated by the voting circuit and the first clock frequency, and

the dividing circuit is used for dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals which are sequentially output to the phase interpolator according to the plurality of second adjusting codes.

16. The memory storage device of claim 15, wherein the first clock frequency is lower than the second clock frequency.