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CN113270128B - Integrated memory cell and memory array - Google Patents

Integrated memory cell and memory array Download PDF

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Publication number
CN113270128B
CN113270128B CN202110803438.3A CN202110803438A CN113270128B CN 113270128 B CN113270128 B CN 113270128B CN 202110803438 A CN202110803438 A CN 202110803438A CN 113270128 B CN113270128 B CN 113270128B
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transistor
nmos
nmos tube
tube
storage
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CN113270128A (en
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袁庆鹏
蔡晓波
张思萌
张新龙
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Shanghai Yicun Core Semiconductor Co ltd
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Shanghai Yicun Core Semiconductor Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The invention provides an integrated memory unit, which comprises a static random access memory unit; a nonvolatile memory cell including a first memory transistor and a second memory transistor; the gating unit comprises a first gating NMOS tube and a second gating NMOS tube, the first gating NMOS tube and the second gating NMOS tube are used for loading data in the nonvolatile storage unit to the static random access storage unit, the first gating NMOS tube and the second gating NMOS tube are used as control tubes of the nonvolatile storage unit, the total area of the storage is saved, the erasing, programming and reading operations of the nonvolatile storage unit are compatible, and the reliability of data transfer between the static random access storage unit and the nonvolatile storage unit is high. The invention also provides a memory array comprising at least one integrated memory cell.

Description

Integrated memory cell and memory array
Technical Field
The present invention relates to the field of memory technologies, and in particular, to an integrated memory cell and memory array.
Background
Static Random-Access Memory (SRAM) is a semiconductor Memory device that uses various mechanisms to store states. For example, an SRAM may store a logic low or "0" in one configuration and a logic high or "1" in another configuration. SRAM can be used in computer design because of its relatively low power consumption, speed, and simplicity of operation. One application of SRAM is as configuration memory for Field Programmable Gate Arrays (FPGAs). SRAM has a faster read and write speed than other memories, but the stored data is lost when power is lost. The nonvolatile memory and the static random access memory are combined, each memory unit is correspondingly connected with more control switch tubes, the memory chip has large area, complex structure and higher cost, and the transfer of data in the nonvolatile memory and the static random access memory is unreliable.
The invention patent publication US7164608B2 discloses an integrated non-volatile static random access memory circuit formed on a substrate, as in fig. 1, a non-volatile SRAM array having an array of integrated non-volatile SRAM circuits arranged in rows and columns on the substrate. Each integrated non-volatile SRAM circuit includes an SRAM cell, a first and a second non-volatile storage element. The SRAM cell has a latched storage element of the first and second non-volatile storage elements in communication to receive and permanently retain the digital signal from the latched storage element. The power detection circuit detects power interruptions and power activations and communicates the detection of power interruptions and power activations to the plurality of integrated non-volatile SRAM circuits. Upon detecting a power interruption, the SRAM cell sends a digital signal to the first and second non-volatile storage elements. Upon detecting power up, the SRAM cell of each non-volatile SRAM receives a digital signal from the first and second non-volatile storage elements. However, each of the non-volatile memory elements of the patent uses two gate control transistors, which occupies a large area of the memory.
Therefore, it is desirable to provide an integrated memory cell and memory array to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The present invention is directed to an integrated memory cell and memory array to solve the problem of unreliable data transfer between the non-volatile memory and the sram.
To achieve the above object, the integrated memory cell of the present invention comprises:
the static random access memory unit comprises a first inverter and a second inverter which are connected in a cross-coupling mode and are used for storing data; the first inverter is connected with the second inverter; the first phase inverter comprises a first PMOS tube and a first NMOS tube, the source electrode of the first PMOS tube is connected with a programming erasing voltage end, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is grounded, the second phase inverter comprises a second PMOS tube and a second NMOS tube, the source electrode of the second PMOS tube is connected with the programming erasing voltage end, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded; the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are both connected with the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube, and the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are both connected with the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube;
the static random access memory unit further comprises a third NMOS tube and a fourth NMOS tube, wherein the source electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube, and the drain electrode of the third NMOS tube is connected with a first bit line; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube, the source electrode of the fourth NMOS tube is connected with a second bit line, and the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are connected with the same word line;
the nonvolatile storage unit comprises a first storage transistor and a second storage transistor, wherein the drain electrode of the first storage transistor is connected with a first detection node on a connecting line of the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube, the drain electrode of the second storage transistor is connected with a second detection node on a connecting line of the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube, and the grid electrode of the first storage transistor and the grid electrode of the second storage transistor are both connected with a first signal control line;
the gating unit comprises a first gating NMOS tube and a second gating NMOS tube, wherein the source electrode of the first storage transistor is connected with the source electrode of the first gating NMOS tube, and the drain electrode of the first gating NMOS tube is connected with a power supply voltage end; the source electrode of the second storage transistor is connected with the source electrode of the second gating NMOS tube, the drain electrode of the second gating NMOS tube is connected with the power supply voltage end, the grid electrode of the first gating NMOS tube and the grid electrode of the second gating NMOS tube are both connected with a second signal control line, and the first gating NMOS tube and the second gating NMOS tube are used for loading data in the nonvolatile storage unit to the static random access storage unit.
The integrated memory cell of the present invention has the following beneficial effects: the storage unit is formed by connecting the static random access storage unit, the nonvolatile storage unit and the gating unit, so that the traditional static random access memory has a nonvolatile function; the NMOS tube is used as a control tube of the nonvolatile storage unit, the first storage transistor is connected with the first gating NMOS tube, the second storage transistor is connected with the second gating NMOS tube, and each storage transistor is only connected with one gating NMOS tube, so that the total area of the storage is saved, and the production cost of the storage is further reduced; the grid of the first storage transistor and the grid of the second storage transistor are both connected with the first signal control line, so that the grid of the first storage transistor and the grid of the second storage transistor can be controlled independently, the erasing, programming and reading operations of the nonvolatile storage unit are compatible, and the data transfer reliability between the static random access storage unit and the nonvolatile storage unit is high.
Preferably, one end of the first storage transistor close to the drain of the first storage transistor is provided with a first tunneling window. The beneficial effects are that: the first tunneling window is arranged on one side of the first storage transistor close to the drain electrode of the first storage transistor, and the erasing operation speed of the tunneling effect of the drain electrode region is higher than that of the uniform tunneling effect, so that the erasing operation is realized through the tunneling effect of the drain electrode region, and the erasing efficiency of the nonvolatile storage unit is improved.
Preferably, one end of the second storage transistor close to the drain of the second storage transistor is provided with a second tunneling window.
Further preferably, the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are high voltage transistors, and the high voltage transistors can bear a high voltage required by the erasing operation and the programming operation of the nonvolatile memory cell.
Preferably, when the data in the static random access memory unit is transferred to the nonvolatile memory unit, the nonvolatile memory unit is erased, and after the erasing operation is finished, the nonvolatile memory unit is programmed;
the erasing operation comprises terminating the programming erasing voltage with a power supply voltage, and grounding the second signal control line to enable the first gating NMOS tube and the second gating NMOS tube to be in a cut-off state; the first signal control line is connected with a first high voltage to enable the first storage transistor and the second storage transistor to be in a conducting state; and the first storage transistor and the second storage transistor both generate a tunneling effect, and the erasing operation of the first storage transistor and the second storage transistor is completed.
Further preferably, the programming operation includes terminating the program erase voltage with a second high voltage, the second high voltage being smaller than the first high voltage, grounding the first signal control line to make the first storage transistor and the second storage transistor in a cut-off state, grounding the second signal control line to make the first gated NMOS transistor and the second gated NMOS transistor in a cut-off state, and both the source of the first storage transistor and the source of the second storage transistor being in a floating state;
the voltage difference between the grid electrode and the drain electrode of the first storage transistor is negative second high voltage, the first storage transistor generates a tunneling effect, and the programming operation of the first storage transistor is completed;
the voltage difference between the gate and the drain of the second storage transistor is 0, and the second storage transistor does not perform a programming operation.
Preferably, the loading of the data in the nonvolatile memory cell into the static random access memory cell includes disconnecting the program erase voltage terminal from a power supply voltage to eliminate the influence of the data in the static random access memory cell on the loading operation;
the second signal control line controls the first gating NMOS tube and the second gating NMOS tube to be in an open state; respectively applying detection voltages to the first storage transistor and the second storage transistor through the first signal control line, wherein current flows through the first storage transistor, and the first detection node has induced voltage; no current flows through the second storage transistor;
and after the influence of the data in the static random access memory unit on the loading operation is eliminated, the programming erasing voltage is connected with the power supply voltage, and a positive feedback loop formed by the first phase inverter and the second phase inverter amplifies the voltage difference between the first detection node and the second detection node to the power supply voltage.
The invention also provides a memory array comprising at least one integrated memory cell.
The memory array of the invention has the advantages that: the memory array comprises at least one integrated memory unit, the erasing, programming and reading operations of the nonvolatile memory unit are compatible, and the data transfer reliability between the static random access memory unit and the nonvolatile memory unit is high.
Drawings
FIG. 1 is a circuit diagram of a prior art non-volatile random access memory;
FIG. 2 is a circuit diagram of a prior art non-volatile static memory cell;
FIG. 3 is a circuit diagram of an integrated memory cell according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems of the prior art, an embodiment of the present invention provides an integrated memory cell, and fig. 3 is a circuit diagram of the memory cell of the present invention. Referring to fig. 3, the memory cell includes:
static random access memory cell 1;
a nonvolatile memory cell 2, wherein the nonvolatile memory cell 2 comprises a first memory transistor 201 and a second memory transistor 202, an input terminal of the first memory transistor 201 is connected to a first output terminal of the static random access memory cell 1, and an input terminal of the second memory transistor 202 is connected to a second output terminal of the static random access memory cell 1; the grid of the first storage transistor 201 and the grid of the second storage transistor 202 are both connected with a first signal control line 7;
in some embodiments, the nonvolatile Memory unit 2 is an Electrically Erasable Programmable Read Only Memory (EEPROM).
In some embodiments, the first memory transistor 201 and the second memory transistor 202 can both be N-type MOS transistors.
The gating unit 3 includes a first gating NMOS tube 301 and a second gating NMOS tube 302, the first gating NMOS tube 301 is connected to the first storage transistor 201, the second gating NMOS tube 302 is connected to the second storage transistor 202, and the first gating NMOS tube 301 and the second gating NMOS tube 302 are used for loading data in the nonvolatile storage unit 2 to the static random access storage unit 1.
The advantages of the invention are described below with reference to the accompanying drawings:
fig. 1 is a circuit diagram of a non-volatile random access memory of the prior art. Referring to fig. 1, a first floating gate transistor MC1Connecting a first gating transistor ST x1And a second strobeTransistor STx2Second floating gate transistor MC2Connecting a first gating transistor STx3And a second gate transistor STx4Each floating gate transistor is connected with two gating transistors as control tubes thereof, and occupies a larger area of a memory chip.
FIG. 2 is a circuit diagram of a prior art non-volatile static memory cell. Referring to fig. 2, the first nonvolatile memory cell 14 and the second nonvolatile memory cell 16 are connected in a cross-coupled manner, and when the memory reads data, the nonvolatile memory cells may be "locked up" and read incorrectly due to the tendency and randomness of the SRAM memory after being powered up. The gate control transistors of the first nonvolatile memory cell 14 and the second nonvolatile memory cell 16 are a first transistor 18 and a second transistor 20, and both the first transistor 18 and the second transistor 20 are PMOS transistors.
Referring to fig. 3, in order to solve the problems mentioned in the prior art, the first memory transistor 201 of the memory cell of the present invention is connected to the first gate NMOS transistor 301, and the second memory transistor 202 is connected to the second gate NMOS transistor 302, so that it can be seen that each memory transistor of the present invention uses only one gate NMOS transistor as its control transistor. Therefore, the invention has the advantages that: the storage unit saves the number of gating NMOS tubes, thereby saving the areas of the storage unit and a chip;
according to the invention, the drain input end of the first storage transistor 201 and the drain input end of the second storage transistor 202 are respectively connected with two output ends of the static random access memory unit 1, the grid electrode of the first storage transistor 201 and the grid electrode of the second storage transistor 202 are both connected with the first signal control line 7, therefore, the grid electrode of the first storage transistor 201 and the grid electrode of the second storage transistor 202 can be independently controlled, the erasing, programming and reading operations of the nonvolatile memory unit are compatible, and the reliability of the erasing, programming and reading operations is higher. The data transfer reliability between the static random access memory unit and the nonvolatile memory unit is high. The first gating NMOS tube 301 and the second gating NMOS tube 302 are used as gating control tubes of the nonvolatile memory unit, and the NMOS gating control tubes are adopted in the nonvolatile memory unit, so that the area of a memory is further saved compared with PMOS gating control tubes.
Referring to fig. 3, the sram cell 1 includes a first inverter 101 and a second inverter 102 coupled to each other in a cross-coupling manner, and stores data. The first inverter 101 is connected to the second inverter 102, and the input terminals and the output terminals of the two inverters are connected in a cross-reverse manner, that is, the output terminal of the first inverter 101 is connected to the input terminal of the second inverter 102, and the output terminal of the second inverter 102 is connected to the input terminal of the first inverter 101. The locking and saving of the output state of sram cell 1 is achieved, and thus the sram cell has two level stable states of 0 and 1.
As a preferred embodiment of the present invention, the first inverter 101 includes a first PMOS transistor 1011 and a first NMOS transistor 1012, a source of the first PMOS transistor 1011 is connected to a program-erase voltage VPP, a drain of the first PMOS transistor 1011 is connected to a drain of the first NMOS transistor 1012, a gate of the first PMOS transistor 1011 is connected to a gate of the first NMOS transistor 1012, and a source of the first NMOS transistor 1012 is grounded. The second inverter 102 includes a second PMOS transistor 1021 and a second NMOS transistor 1022, a source of the second PMOS transistor 1021 is connected to the program erase voltage VPP, a drain of the second PMOS transistor 1021 is connected to a drain of the second NMOS transistor 1022, a gate of the second PMOS transistor 1021 is connected to a gate of the second NMOS transistor 1022, a source of the second NMOS transistor 1022 is grounded, a gate of the first NMOS transistor 1012 is connected to the first input terminal of the nonvolatile memory cell 2, and a gate of the second NMOS transistor 1022 is connected to the second input terminal of the nonvolatile memory cell 2.
The substrate of the first PMOS transistor 1011 and the substrate of the second PMOS transistor 1021 are both connected to the program-erase voltage terminal VPP, and the substrate of the first NMOS transistor 1012 and the substrate of the second NMOS transistor 1022 are both grounded (not shown).
The drain of the first PMOS transistor 1011 and the drain of the first NMOS transistor 1012 are both connected to the gate of the second PMOS transistor 1021 and the gate of the second NMOS transistor 1022, and the gate of the first PMOS transistor 1011 and the gate of the first NMOS transistor 1012 are both connected to the drain of the second PMOS transistor 1021 and the drain of the second NMOS transistor 1022.
In a preferred embodiment of the present invention, the output terminal of the first inverter 101 is connected to the drain of the second storage transistor 202, and the output terminal of the second inverter 102 is connected to the drain of the first storage transistor 201. The output end of the first inverter 101 is connected to the second detection node QB, which is connected to the drain of the first PMOS transistor 1011 and the drain of the first NMOS transistor 1012, and the output end of the second inverter 102 is connected to the first detection node Q, which is connected to the drain of the second PMOS transistor 1021 and the drain of the second NMOS transistor 1022. The drain of the first storage transistor 201 is connected to the first sensing node Q, and the drain of the second storage transistor 202 is connected to the second sensing node QB.
Referring to fig. 3, as a preferred embodiment of the present invention, the sram cell 1 further includes a third NMOS transistor 103 and a fourth NMOS transistor 104, a drain of the first PMOS transistor 1011 and a drain of the first NMOS transistor 1012 are connected to a source of the third NMOS transistor 103, and a drain of the third NMOS transistor 103 is connected to the first bit line 4. The drain of the second PMOS transistor 1021 and the drain of the second NMOS transistor 1022 are connected to the drain of the fourth NMOS transistor 104, and the source of the fourth NMOS transistor 104 is connected to the second bit line 5. The grid electrode of the third NMOS tube 103 and the fourth NMOS tube are connected with the same word line 6.
It can be stated that both the first bit line 4 and the second bit line 5 of the invention are used for read and write operations of the sram cell 1 of the invention. The transfer operation of the data of the static random access memory cell 1 to the nonvolatile memory cell 2 and the load operation of the data of the nonvolatile memory cell 2 to the static random access memory cell 1 are not related to the read-write circuit of the static random access memory cell 1, so during the transfer operation and the load operation, the word line 6 is grounded, the third NMOS transistor 103 and the fourth NMOS transistor 104 are both in the off state, and the first bit line 4 and the second bit line 5 are both in the floating state.
In a preferred embodiment of the present invention, the substrate of the third NMOS transistor 103 and the substrate of the fourth NMOS transistor 104 are both grounded (not shown in the figure). The first PMOS transistor 1011, the first NMOS transistor 1012, the second PMOS transistor 1021, the second NMOS transistor 1022, the third NMOS transistor 103, and the fourth NMOS transistor 104 are all high voltage transistors capable of withstanding a high voltage required for the erasing operation and the programming operation of the nonvolatile memory cell 2.
It can be noted that, since the first storage transistor 201, the second storage transistor 202, the third NMOS transistor 103, the fourth NMOS transistor 104, the first gate NMOS transistor 301, and the second gate NMOS transistor 302 are all NMOS transistors, the first storage transistor 201, the second storage transistor 202, the third NMOS transistor 103, the fourth NMOS transistor 104, the first gate NMOS transistor 301, and the second gate NMOS transistor 302 can be built in one high-voltage well, that is, the six NMOS transistors share one high-voltage well. The third NMOS transistor 103 and the fourth NMOS transistor 104, the nonvolatile memory cell 2 and the gating cell 3 share one high voltage well, which saves the isolation distance between a plurality of different wells, thereby further reducing the area of the integrated memory cell, compared to the nonvolatile random access memory as shown in fig. 1.
As a preferred embodiment of the present invention, the source of the first gating NMOS transistor 301 is connected to the source of the first storage transistor 201, the source of the second gating NMOS transistor 302 is connected to the source of the second storage transistor 202, the gates of the first and second gating NMOS transistors 301 and 302 are both connected to the second signal control line 8, and the drains of the first and second gating NMOS transistors 301 and 302 are both connected to the power supply voltage terminal VDD. The advantages are that: the first gating NMOS tube 301 is used for controlling the first storage transistor 201, and the second gating NMOS tube 302 is used for controlling the second storage transistor 202, so that the purpose of independent control is achieved, the erasing operation, the programming operation and the loading recovery operation of the storage can be accurately controlled, the reliability is higher, and the stability of the storage array for transferring data in case of power failure and loading recovery data after the storage array recovers power supply is improved.
In a preferred embodiment of the present invention, the substrate of the first memory transistor 201, the substrate of the second memory transistor 202, the substrate of the first gate NMOS transistor 301, and the substrate of the second gate NMOS transistor 302 are all grounded (not shown in the figure).
As a preferred embodiment of the present invention, a first tunneling window (not shown in the figure) is disposed on a side of the first storage transistor 201 close to the drain of the first storage transistor 201. It is added that the second storage transistor 202 has the same structure as the first storage transistor 201, that is, a second tunneling window (not shown) is disposed near a side of the second storage transistor 202, so that both the first storage transistor 201 and the second storage transistor 202 can generate a tunneling effect during an erase operation. The advantages are that: the first tunneling window is disposed to enable the first storage transistor 201 to generate a tunneling effect, and the tunneling window is disposed near the drain of the first storage transistor 201, so that the first storage transistor 201 can generate a tunneling effect in the drain region during an erase phase. Since the erase operation speed by the tunneling effect of the drain region is faster than the erase operation speed by the uniform tunneling effect, the erase operation is realized by the tunneling effect of the drain region, and the erase efficiency of the nonvolatile memory cell is improved. Compared with the uniform tunneling effect, the tunneling effect of the drain region is more advantageous in programming speed, and the generated tunnel current density is larger because the tunneling window of the drain region is smaller than the current injection area of the uniform tunneling window.
In a preferred embodiment of the present invention, when the data in the static random access memory unit 1 is transferred to the nonvolatile memory unit 2, an erase operation is performed on the nonvolatile memory unit 2, and after the erase operation is completed, a program operation is performed on the nonvolatile memory unit 2;
the erasing operation comprises connecting the programming and erasing voltage end VPP with a power supply voltage, and connecting the second signal control line 8 with the ground to enable the first gating NMOS tube 301 and the second gating NMOS tube 302 to be in a cut-off state; the first signal control line 7 is connected with a first high voltage to make the first storage transistor 201 and the second storage transistor 202 in a conducting state; the first storage transistor 201 and the second storage transistor 202 both generate tunneling effect, and the erasing operation of the first storage transistor 201 and the second storage transistor 202 is completed.
The programming operation comprises connecting the programming and erasing voltage end VPP with a second high voltage, wherein the second high voltage is smaller than the first high voltage, the first signal control line 7 is grounded to enable the first storage transistor 201 and the second storage transistor 202 to be in a cut-off state, the second signal control line 8 is grounded to enable the first gating NMOS tube 301 and the second gating NMOS tube 302 to be in a cut-off state, and the source electrode of the first storage transistor 201 and the source electrode of the second storage transistor 202 are both in a floating state;
the voltage difference between the gate and the drain of the first storage transistor 201 is a negative second high voltage, and the first storage transistor 201 generates a tunneling effect to complete the programming operation of the first storage transistor 201; the voltage difference between the gate and the drain of the second memory transistor 202 is 0, and the second memory transistor 202 does not perform the programming operation.
As a preferred embodiment of the present invention, the loading of the data in the nonvolatile memory cell 2 into the static random access memory cell 1 includes disconnecting the program erase voltage VPP from the power supply voltage to eliminate the influence of the data in the static random access memory cell 1 on the loading operation;
the second signal control line 8 controls the first gate NMOS transistor 301 and the second gate NMOS transistor 302 to be in an on state; applying a detection voltage to the first storage transistor 201 and the second storage transistor 202 through the first signal control line 7, respectively, wherein a current flows through the first storage transistor 201, and a first sensing voltage is provided at the first sensing node Q; no current flows through the second storage transistor 202, and a second sensing voltage is present at the second sensing node QB;
after the influence of the data in the static random access memory unit 1 on the loading operation is eliminated, the program erase voltage end VPP is connected to the power supply voltage, and the positive feedback loop formed by the first inverter 101 and the second inverter 102 amplifies the voltage difference between the first detection node Q and the second detection node QB to the power supply voltage.
The working principle of the memory cell of the invention is described below with reference to specific embodiments:
1. when the sram cell 1 is in the latch state, that is, before the data in the sram cell 1 is transferred to the nonvolatile memory cell 2, it is assumed that the logic level of the first detection node Q is "1" and the logic level of the second detection node QB is "0".
2. When data in the static random access memory unit 1 needs to be transferred to the nonvolatile memory unit 2, sequentially performing an erasing operation and a programming operation on the nonvolatile memory unit 2, so that the data in the static random access memory unit 1 is transferred to the nonvolatile memory unit 2.
(1) The erase operation includes:
the program erase voltage end VPP is connected to a power voltage VDD, a logic level of a first detection node Q in an erase operation process is identical to a logic level of a first detection node Q when the sram cell 1 is in a latch state, and a logic level of a second detection node QB in an erase operation process is identical to a logic level of a second detection node QB when the sram cell 1 is in the latch state, that is, the logic level of the first detection node Q is "1" and the logic level of the second detection node QB is "0".
The first signal control line 7 is connected with a first high voltage to enable the first storage transistor 201 and the second storage transistor 202 to be in a conducting state, the first high voltage is specifically 16V, the second signal control line 8 is grounded to enable the first gating NMOS tube 301 and the second gating NMOS tube 302 to be in a blocking state, the voltage of the drain of the first storage transistor 201 and the voltage of the first detection node Q are coupled to a power supply voltage VDD, the source and the drain of the first storage transistor 201 are both connected with the power supply voltage VDD, the voltage difference between the gate and the drain of the first storage transistor 201 is (16-VDD) V, and the first storage transistor 201 generates a tunneling effect (Fowler-Nordheim). The drain of the second storage transistor 202 and the voltage of the second detection node QB are coupled to ground, the source and the drain of the second storage transistor 202 are both grounded, the voltage difference between the gate and the drain of the second storage transistor 202 is 16V, and the second storage transistor 202 also generates a tunneling effect. The erasing operation for the first memory transistor 201 and the second memory transistor 202 is completed. The erase effect of the first memory transistor 201 is inferior to the erase effect of the second memory transistor 202. But the poor erase effect of the first memory transistor 201 relative to the second memory transistor 202 has no effect on the programming operation described below.
(2) The programming operation includes:
the program erase voltage terminal VPP is connected to a second high voltage, so that the level of the first detection node Q is coupled to the second high voltage, specifically, the second high voltage is 12V. The logic level of the second detection node QB is still "0".
The first signal control line 7 is grounded to make the first storage transistor 201 and the second storage transistor 202 in a cut-off state, the second signal control line 8 is grounded to make the first gating NMOS transistor 301 and the second gating NMOS transistor 302 in a cut-off state, and the source of the first storage transistor 201 and the source of the second storage transistor 202 are both in a floating state. The voltage difference between the gate and the drain of the first storage transistor 201 is-12V, and the first storage transistor 201 generates a tunneling effect, thereby completing the programming operation of the first storage transistor 201. The voltage difference between the gate and the drain of the second memory transistor 202 is 0V, the second memory transistor 202 does not perform the programming operation, and the second memory transistor 202 is still in the erased state.
3. When the data in the nonvolatile memory unit needs to be loaded to the static random access memory unit 1, the loading operation is executed:
the program erase voltage terminal VPP is disconnected from the power supply voltage to eliminate the influence of the data in the sram cell 1 on the loading operation.
After eliminating the influence of the data in the sram cell 1 on the loading operation, the second signal control line 8 is connected to the power supply voltage VDD to turn on the first gate NMOS transistor 301 and the second gate NMOS transistor 302. A probe voltage, specifically, the probe voltage may be 1.5V, is applied to the first memory transistor 201 and the second memory transistor 202 through the first signal control line 7, respectively, to detect the states of the first memory transistor 201 and the second memory transistor 202. After the programming operation is completed, it is detected that the first storage transistor 201 is in a conducting state, a current flows through the first storage transistor 201, and a first induced voltage can be detected at the first detection node Q. The second storage transistor 202 is in an off state, no current flows through the second storage transistor 202, and a second induced voltage is detected at the second detection node QB. The first induced voltage is greater than the second induced voltage.
After eliminating the influence of the data in the sram cell 1 on the load restore operation, the program-erase voltage VPP is switched from the floating state to the power supply voltage VDD, and a positive feedback loop formed by the first inverter 101 and the second inverter 102 amplifies the voltage difference between the first detection node Q and the second detection node QB to the power supply voltage VDD, so that the load result is: the first detection node has a logic level of "1" and the second detection node has a logic level of "0". After the loading operation is completed, the logic level of the first detection node Q is consistent with the logic level of the first detection node Q in the latch state of the static random access memory unit, and is "1"; the logic level of the second detection node QB is consistent with the logic level of the second detection node QB in the latch state of the sram cell, and is "0", which indicates that the data in the nonvolatile memory cell 2 has been loaded to the sram cell 1, thereby completing the loading operation.
In some embodiments, the integrated memory unit of the present invention may cooperate with the power detection circuit and the control instruction of the memory chip to implement reliable transfer and storage of data, and the specific operations are as follows:
when the power supply detection circuit detects that the memory chip is powered off, a control instruction in the memory chip enables data in the static random access memory unit to be transferred to the nonvolatile memory unit;
when the power supply detection circuit detects that the power supply of the memory chip is recovered, the control instruction in the memory chip enables the data in the nonvolatile memory unit to be loaded to the static random access memory unit, so that the problem of data loss when the static random access memory unit is powered off is solved, and the reliable storage of the data is realized.
Embodiments of the present invention further provide a memory array, which includes at least one integrated memory cell according to the present invention.
The memory array of the embodiment of the invention has the advantages that: the memory array comprises at least one integrated memory unit, the data transfer reliability between the static random access memory unit and the nonvolatile memory unit is high, the time is short, the static random access memory can be manufactured based on a standard Complementary Metal Oxide Semiconductor (CMOS) logic process, the production is easy, the structure is simple, the cost is low, the stability and the reliability are realized, and the traditional static random access memory has the nonvolatile function.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (6)

1. An integrated memory cell, comprising:
the static random access memory unit comprises a first phase inverter and a second phase inverter which are connected in a cross coupling mode and used for storing data, the first phase inverter comprises a first PMOS tube and a first NMOS tube, the source electrode of the first PMOS tube is connected with a programming and erasing voltage end, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is grounded, the second phase inverter comprises a second PMOS tube and a second NMOS tube, the source electrode of the second PMOS tube is connected with the programming and erasing voltage end, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are both connected with the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube, the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are both connected with the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube;
the static random access memory unit further comprises a third NMOS tube and a fourth NMOS tube, wherein the source electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube, the drain electrode of the third NMOS tube is connected with a first bit line, the drain electrode of the fourth NMOS tube is connected with the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube, the source electrode of the fourth NMOS tube is connected with a second bit line, and the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are connected with the same word line;
the nonvolatile storage unit comprises a first storage transistor and a second storage transistor, wherein the drain electrode of the first storage transistor is connected with a first detection node on a connecting line of the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube, the drain electrode of the second storage transistor is connected with a second detection node on a connecting line of the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube, and the grid electrode of the first storage transistor and the grid electrode of the second storage transistor are both connected with a first signal control line;
a gating unit including a first gating NMOS transistor and a second gating NMOS transistor, wherein a source of the first storage transistor is connected to a source of the first gating NMOS transistor, a drain of the first gating NMOS transistor is connected to a power voltage terminal, a source of the second storage transistor is connected to a source of the second gating NMOS transistor, a drain of the second gating NMOS transistor is connected to the power voltage terminal, a gate of the first gating NMOS transistor and a gate of the second gating NMOS transistor are both connected to a second signal control line, and the first gating NMOS transistor and the second gating NMOS transistor are used for loading data in the nonvolatile storage unit to the static random access storage unit, wherein the first PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are high voltage transistors to bear high voltages required by the erasing operation and the programming operation of the nonvolatile storage unit, when the data in the static random access memory unit is transferred to the nonvolatile memory unit, erasing the nonvolatile memory unit, and after the erasing operation is finished, programming the nonvolatile memory unit, wherein the erasing operation comprises that the programming erasing voltage is connected with a power supply voltage, the second signal control line is grounded to enable the first gating NMOS tube and the second gating NMOS tube to be in a cut-off state, the first signal control line is connected with a first high voltage to enable the first memory transistor and the second memory transistor to be in a conducting state, and the first memory transistor and the second memory transistor both generate a tunneling effect to finish the erasing operation of the first memory transistor and the second memory transistor.
2. The integrated memory cell of claim 1, wherein an end of the first memory transistor proximate to the drain of the first memory transistor is provided with a first tunneling window.
3. The integrated memory cell of claim 1, wherein an end of the second memory transistor proximate to the drain of the second memory transistor is provided with a second tunneling window.
4. The integrated memory cell of claim 1, wherein the program operation includes terminating the program erase voltage to a second high voltage, the second high voltage being less than the first high voltage, the first signal control line being grounded to place the first memory transistor and the second memory transistor in an off state, the second signal control line being grounded to place the first gated NMOS transistor and the second gated NMOS transistor in an off state, the source of the first memory transistor and the source of the second memory transistor both being in a floating state;
the voltage difference between the grid electrode and the drain electrode of the first storage transistor is negative second high voltage, the first storage transistor generates a tunneling effect, and the programming operation of the first storage transistor is completed;
the voltage difference between the gate and the drain of the second storage transistor is 0, and the second storage transistor does not perform a programming operation.
5. The integrated memory cell of claim 1 wherein loading the data in the nonvolatile memory cell into the sram cell comprises disconnecting the program erase voltage terminal from a power supply voltage to eliminate an effect of the data in the sram cell on the loading;
the second signal control line controls the first gating NMOS tube and the second gating NMOS tube to be in an open state; respectively applying detection voltages to the first storage transistor and the second storage transistor through the first signal control line, wherein current flows through the first storage transistor, and the first detection node has a first induction voltage; no current flows through the second storage transistor, and a second sensing voltage is provided at the second sensing node;
the programming erasing voltage end is connected with a power voltage again, and a positive feedback loop formed by the first phase inverter and the second phase inverter amplifies the voltage difference between the first detection node and the second detection node to the power voltage.
6. A memory array comprising at least one integrated memory cell according to any of claims 1 to 5.
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