CN113257185B

CN113257185B - Display panel, display device and method for arranging light-emitting elements of display panel

Info

Publication number: CN113257185B
Application number: CN202110578548.4A
Authority: CN
Inventors: 翟应腾; 符鞠建
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2021-05-26
Filing date: 2021-05-26
Publication date: 2022-09-30
Anticipated expiration: 2041-05-26
Also published as: CN113257185A

Abstract

The invention discloses a display panel, a display device and a light-emitting element configuration method of the display panel. The display panel comprises a plurality of sub-pixels; each sub-pixel comprises a light emitting module, a gating module and a pixel driving circuit; the light emitting module includes a first light emitting element and a second light emitting element; the gating module comprises a first gating unit, a second gating unit and a third gating unit; if the first gating unit is conducted, the second gating unit and the third gating unit are disconnected, and the first light-emitting element and the second light-emitting element are connected in series; if the first gating unit is disconnected, the second gating unit and the third gating unit are conducted, and the first light-emitting element and the second light-emitting element are connected in parallel. The display panel, the display device and the light-emitting element configuration method of the display panel can meet the requirements of high manufacturing yield and low power consumption at the same time.

Description

Display panel, display device and method for arranging light-emitting elements of display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel, a display device and a light-emitting element configuration method of the display panel.

Background

With the continuous development of display technologies, more and more electronic devices with display functions are widely applied to daily life and work of people, and great convenience is brought to the daily life and work of people.

The main component of the electronic device that implements the display function is the display panel. The conventional display panel generally includes a plurality of sub-pixels arranged in an array, each sub-pixel includes two light emitting elements and a pixel driving circuit electrically connected to the light emitting elements, and the pixel driving circuit provides a driving current to the light emitting elements to drive the light emitting elements to emit light. The two light-emitting elements can be connected in two ways, one way is that the two light-emitting elements are arranged in series, so that the driving current is halved, and the power consumption of the display panel is reduced; the other is that the two light-emitting elements are arranged in parallel, so that when one light-emitting element fails, the other light-emitting element can replace the damaged light-emitting element to emit light, and the manufacturing yield of the display panel is improved.

However, when two light emitting devices in each sub-pixel of the display panel are arranged in series, the sub-pixel can emit light when both the two light emitting devices are normal, which results in low yield rate of the display panel; when two light emitting elements in each sub-pixel of the display panel are arranged in parallel, the driving current is large, which results in increased power consumption, i.e. the display panel in the prior art cannot meet the requirements of high manufacturing yield and low power consumption at the same time.

Disclosure of Invention

The invention provides a display panel, a display device and a method for configuring a light-emitting element of the display panel, which can meet the requirements of high manufacturing yield and low power consumption at the same time.

In a first aspect, an embodiment of the present invention provides a display panel, where the display panel includes a plurality of sub-pixels; each sub-pixel comprises a light emitting module, a gating module and a pixel driving circuit;

the light emitting module comprises a first light emitting element and a second light emitting element;

the gating module comprises a first gating unit, a second gating unit and a third gating unit;

if the first gating unit is conducted, the second gating unit and the third gating unit are disconnected, and the first light-emitting element and the second light-emitting element are connected in series; if the first gating unit is disconnected, the second gating unit and the third gating unit are conducted, and the first light-emitting element and the second light-emitting element are connected in parallel.

In a second aspect, an embodiment of the present invention further provides a display device, where the display device includes: the display panel of the first aspect.

In a third aspect, an embodiment of the present invention further provides a light emitting element arrangement method of a display panel, where the display panel according to the first aspect is adopted, and the light emitting element arrangement method of the display panel includes:

controlling the first gating unit to be conducted, and the second gating unit and the third gating unit to be disconnected so that the first light-emitting element and the second light-emitting element of the sub-pixel are connected in series;

performing display test on the display panel, and determining a fault sub-pixel according to a test display picture;

and controlling the first gating unit corresponding to the failure sub-pixel to be disconnected, and controlling the second gating unit and the third gating unit to be connected so as to enable the first light-emitting element and the second light-emitting element to be connected in parallel.

According to the technical scheme, when the display panel is subjected to display test, the first gating unit is conducted to enable the first light-emitting element and the second light-emitting element to be connected in series, and then the sub-pixel with the fault is determined according to a test display picture. When the sub-pixel with the fault is determined, the first gating unit of the sub-pixel with the fault is disconnected, and the second gating circuit and the third gating circuit are connected, so that the first light-emitting element and the second light-emitting element of the sub-pixel with the fault are connected in parallel, when one light-emitting element is damaged, the other light-emitting element replaces the damaged light-emitting element to emit light, the problem that one light-emitting element is damaged and cannot emit light is avoided, and the preparation yield of the display panel is improved; meanwhile, the first gating unit of the sub-pixel without faults is switched on, and the second gating unit and the third gating unit are switched off, so that the first light-emitting element and the second light-emitting element of the sub-pixel without faults are connected in series, the driving current of the sub-pixel is further reduced, and the power consumption of the display panel is reduced.

Drawings

FIG. 1 is a schematic diagram of a display panel in the prior art;

FIG. 2 is a schematic diagram of a display panel according to the prior art;

fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a sub-pixel of FIG. 3;

FIG. 5 is a schematic structural diagram of another sub-pixel of FIG. 3;

FIG. 6 is a schematic diagram of a structure of another sub-pixel in FIG. 3;

FIG. 7 is a schematic structural diagram of another sub-pixel of FIG. 3;

FIG. 8 is a schematic structural diagram of another sub-pixel of FIG. 3;

FIG. 9 is a schematic structural diagram of another sub-pixel of FIG. 3;

FIG. 10 is a schematic diagram of a display panel according to another embodiment of the present invention;

FIG. 11 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of another sub-pixel of FIG. 3;

FIG. 13 is a flowchart of a method for configuring light emitting elements of a display panel according to an embodiment of the present invention;

FIG. 14 is a flowchart of a method for configuring light-emitting elements of a display panel according to another embodiment of the present invention;

FIG. 15 is a flowchart illustrating a method for configuring light-emitting elements of a display panel according to another embodiment of the present invention;

fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a display panel in the prior art, as shown in fig. 1, a display panel 100 'in the prior art includes a plurality of sub-pixels 10', each sub-pixel 10 'includes a pixel driving circuit 13', a first light emitting element 111 'and a second light emitting element 112', the first light emitting element 111 'and the second light emitting element 112' are connected in parallel and are electrically connected to the pixel driving circuit 13 ', when one of the sub-pixels 10' is damaged, the other light emitting element replaces the damaged light emitting element to emit light, for example, when the first light emitting element 111 'is damaged, the second light emitting element 112' replaces the first light emitting element 111 'to emit light, so that the manufacturing yield of the display panel 100' can be improved; alternatively, fig. 2 is a schematic structural diagram of another display panel in the prior art, as shown in fig. 2, the anode of the first light emitting element 111 ' is electrically connected to the pixel driving circuit 13 ', and the cathode of the first light emitting element 111 ' is electrically connected to the anode of the second light emitting element 112 ', that is, the first light emitting element 111 ' and the second light emitting element 112 ' are connected in series, so that the current for driving the light emitting elements to emit light is reduced by half, and the power consumption of the display panel 100 ' is reduced.

However, when two light emitting elements in each sub-pixel 10 ' of the display panel 100 ' are arranged in parallel, although one light emitting element in the sub-pixel 10 ' is damaged and the other light emitting element can emit light instead of the damaged light emitting element, since the first light emitting element 111 ' and the second light emitting element 112 ' of the sub-pixel where the undamaged light emitting element is located are also in a parallel state, when the display panel 100 ' is in a display stage, a driving current for driving the sub-pixel 10 ' to emit light is large, so that power consumption is high; when two light emitting elements in each sub-pixel 10 'of the display panel 100' are arranged in series, both the two light emitting elements can emit light only when the sub-pixel 10 'is normal, and once one of the light emitting elements is damaged, the display panel cannot be used, so that the manufacturing yield of the display panel 100' is low, that is, the display panel in the prior art cannot meet the requirements of high manufacturing yield and low power consumption at the same time.

In view of the above technical problem, an embodiment of the present invention provides a display panel, including a plurality of sub-pixels; each sub-pixel comprises a light emitting module, a gating module and a pixel driving circuit; the light emitting module comprises a first light emitting element and a second light emitting element; the gating module comprises a first gating unit, a second gating unit and a third gating unit; if the first gating unit is conducted, the second gating unit and the third gating unit are disconnected, and the first light-emitting element and the second light-emitting element are connected in series; if the first gating unit is disconnected, the second gating unit and the third gating unit are conducted, and the first light-emitting element and the second light-emitting element are connected in parallel.

By adopting the technical scheme, when the display panel is subjected to the display test, the first gating unit is conducted so as to enable the first light-emitting element and the second light-emitting element to be connected in series, and then the sub-pixel with the fault is determined according to the test display picture. When the sub-pixel with the fault is determined, the first gating unit of the sub-pixel with the fault is switched off, the second gating circuit and the third gating circuit are switched on, so that the first light-emitting element and the second light-emitting element of the sub-pixel with the fault are connected in parallel, when one light-emitting element is damaged, the other light-emitting element replaces the damaged light-emitting element to emit light, the problem that the sub-pixel cannot emit light due to the fact that one light-emitting element is damaged is avoided, and the preparation yield of the display panel is improved; meanwhile, the first gating unit of the sub-pixel without faults is switched on, and the second gating unit and the third gating unit are switched off, so that the first light-emitting element and the second light-emitting element of the sub-pixel without faults are connected in series, the driving current of the sub-pixel is further reduced, and the power consumption of the display panel is reduced.

The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

Fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and as shown in fig. 3, the display panel 100 according to the embodiment of the present invention includes a driving circuit 20 and a plurality of sub-pixels 10; each sub-pixel 10 includes a light emitting module and a pixel driving circuit; the driving circuit 20 is electrically connected to the pixel driving circuit through a signal line (not shown in the figure), and provides a driving signal to the pixel driving circuit, so that the pixel driving circuit drives the light emitting module to emit light, thereby achieving the effect of displaying the image, where the signal line may include, for example, a first scanning signal line, a second scanning signal line, a light emitting control signal line, and the like, the first scanning signal line is used for transmitting a first scanning signal, the second scanning signal line is used for transmitting a second scanning signal, and the light emitting control signal line is used for transmitting a light emitting control signal. Optionally, the display panel 100 further includes a driving chip 30, and the driving chip 30 is electrically connected to the driving circuit 20 through a signal line (not shown in the figure), and provides signals required for normal operation of the driving circuit 20 to the driving circuit 20, where the signal line may be, for example, a clock signal line, a high-level signal line, a low-level signal line, and the like, the clock signal line is used for transmitting a clock signal, the high-level signal line is used for transmitting a high-level signal, and the low-level signal line is used for transmitting a low-level signal. The position of the driving circuit 20 in the display panel 100 is not specifically limited in this embodiment, and a person skilled in the art can set the driving circuit according to actual situations, and fig. 3 only illustrates the driving circuit 20 disposed on one side of the display panel 100.

Fig. 4 is a schematic structural diagram of a sub-pixel in fig. 3, and as shown in fig. 4, each sub-pixel 10 includes a light emitting module 11 and a pixel driving circuit 13, and besides, each sub-pixel 10 further includes a gating module 12; wherein the light emitting module 11 includes a first light emitting element 111 and a second light emitting element 112; the gating module 12 includes a first gating unit 121, a second gating unit 122, and a third gating unit 123; if the first gate unit 121 is turned on, the second gate unit 122 and the third gate unit 123 are turned off, and the first light emitting element 111 and the second light emitting element 112 are connected in series; if the first gate unit 121 is turned off, the second gate unit 122 and the third gate unit 123 are turned on, and the first light emitting element 111 and the second light emitting element 112 are connected in parallel.

The display panel comprises a test stage and a display stage, namely before the display panel is normally displayed, the display panel needs to be subjected to display test firstly to determine whether all sub-pixels in the display panel are in a normal display state, and the stage is the test stage; when all the sub-pixels in the display panel are in the normal display state, the display panel can be normally used to display the subsequent pictures, and the display stage is the stage of display.

In the testing stage, the first gate unit 121 in all the sub-pixels 10 is turned on, the second gate unit 122 and the third gate unit 123 are turned off, that is, the first light emitting elements 111 and the second light emitting elements 112 in all the sub-pixels 10 are in a serial state, then the pixel driving circuit 13 provides a driving current for the light emitting module 11 corresponding to the first gate unit, drives the light emitting module 11 to emit light, and then determines that the sub-pixel 10 with a fault is a faulty sub-pixel according to the display picture, wherein the faulty sub-pixel may be a faulty light emitting element, for example, the first light emitting element 111 or the second light emitting element 112 is damaged, at this time, the first gate unit 121 may be turned off, the second gate unit 122 and the third gate unit 123 are turned on, so that the first light emitting element 111 and the second light emitting element 112 in the faulty sub-pixel are connected in parallel, and at this time, even if one of the light emitting elements is damaged, the display of the sub-pixel can be realized by another light emitting element instead of the lost light emitting element emitting light. That is to say, in the display stage, the first light emitting element 111 and the second light emitting element 112 in the faulty sub-pixel are connected in parallel, and the first light emitting element 111 and the second light emitting element 112 in the non-faulty sub-pixel are connected in series, so that the high production yield can be ensured, the low power consumption requirement can be met, and the problem that the prior art cannot meet the requirements of high production yield and low power consumption at the same time can be solved.

It should be noted that the display phase generally includes an initialization phase, a data writing phase, and a light emitting phase, in the display phase, the first light emitting element 111 and the second light emitting element 112 in the defective sub-pixel are connected in parallel, and the first light emitting element 111 and the second light emitting element 112 in the non-defective sub-pixel are connected in series, and the display phase includes: at least in the light emitting stage, the first gate unit 121 in the defective sub-pixel is turned off, the second gate unit 122 and the third gate unit 123 are turned on, and the first light emitting element 111 and the second light emitting element 112 are connected in parallel; the first gate unit 121 in the non-defective sub-pixel is turned on and the second gate unit 122 and the third gate unit 123 are turned off.

Alternatively, the first light emitting element 111 and the second light emitting element 112 may be, for example, Organic Light Emitting Diodes (OLEDs), Micro light emitting diodes (Micro LEDs), or the like, and the present embodiment does not limit the types of the first light emitting element 111 and the second light emitting element 112.

Alternatively, with continued reference to fig. 4, the first gating unit 121 is connected in series between the first light emitting element 111 and the second light emitting element 112; the input terminal of the second gating unit 122 is electrically connected to the cathode of the first light emitting element 111; the output terminal of the second gating unit 122 is electrically connected to the cathode of the second light emitting element 112; the input terminal of the third gating unit 123 is electrically connected to the positive electrode of the first light emitting element 111; the output terminal of the third gate unit 123 is electrically connected to the positive electrode of the second light emitting element 112.

By the above connection manner, when the first gate unit 121 is turned on and the second gate unit 122 and the third gate unit 123 are turned off, the first light emitting element 111 and the second light emitting element 112 are connected in series; when the first gating unit 121 is turned off and the second gating unit 122 and the third gating unit 123 are turned on, the first light emitting element 111 and the second light emitting element 112 are connected in parallel, and of course, the connection manner among the first light emitting element 111, the second light emitting element 112, the first gating unit 121, the second gating unit 122, and the third gating unit 123 is not limited thereto, and a person skilled in the art may set the connection manner according to actual situations.

Optionally, fig. 5 is a schematic structural diagram of another sub-pixel in fig. 3, and as shown in fig. 5, the first gating unit 121 includes a first transistor M1, the second gating unit 122 includes a second transistor M2, and the third gating unit 123 includes a third transistor M3; a first terminal of the first transistor M1 is electrically connected to the cathode of the first light-emitting element 111, and a second terminal of the first transistor M1 is electrically connected to the anode of the second light-emitting element 112; a first terminal of the second transistor M2 is electrically connected to the negative electrode of the first light-emitting element 111, and a second terminal of the second transistor M2 is electrically connected to the negative electrode of the second light-emitting element 112; a first terminal of the third transistor M3 is electrically connected to the positive electrode of the first light-emitting element 111, and a second terminal of the third transistor M3 is electrically connected to the positive electrode of the second light-emitting element 112. That is, the first gating unit 121, the second gating unit 122, and the third gating unit 123 all include transistors, and it should be noted that the types of the first gating unit 121, the second gating unit 122, and the third gating unit 123 are not limited to the transistors, and as long as devices capable of performing on or off functions are within the protection scope of the present invention, they are not described herein again.

Optionally, with continued reference to fig. 5, when both the second gating unit 122 and the third gating unit 123 are transistors, the conductivity type of the transistor of the second gating unit 122 is the same as the conductivity type of the transistor of the third gating unit 123; the control terminal C2 of the second gate unit 122 is electrically connected to the control terminal C3 of the third gate unit 123.

Illustratively, the second gating unit 122 and the third gating unit 123 are both NMOS transistors, or the second gating unit 122 and the third gating unit 123 are both PMOS transistors.

In this embodiment, when the conductivity type of the transistor of the second gate unit 122 is the same as that of the transistor of the third gate unit 123, the control terminal C2 of the second gate unit 122 and the control terminal C3 of the third gate unit 123 may be simultaneously connected to a control signal line to receive the same signal, so that the second gate unit 122 and the third gate unit 123 are simultaneously turned on or off, and it is not necessary to separately set control signal lines for the second gate unit 122 and the third gate unit 123 to control the turning on or off of the second gate unit 122 and the third gate unit 123, which reduces the number of signal lines, reduces the occupied area of the signal lines, and also simplifies the process steps.

Optionally, the conductivity types of the first gating unit 121 and the second gating unit 122 are opposite, for example, the first gating unit 121 is a PMOS transistor, and the second gating unit 122 is an NMOS transistor; the control terminal of the first gate unit 121, the control terminal of the second gate unit 122, and the control terminal of the third gate unit 123 are electrically connected.

Considering that, when the first gate unit 121 is turned on, the second gate unit 122 and the third gate unit 123 are turned off, and when the first gate unit 121 is turned off, the second gate unit 122 and the third gate unit 123 are turned on, that is, the turn-on or turn-off time of the first gate unit 121 and the second gate unit 122 (the third gate unit 123) is opposite, the control terminal C1 of the first gate unit 121, the control terminal C2 of the second gate unit 122, and the control terminal C3 of the third gate unit 123 can be electrically connected by setting the conduction types of the first gate unit 121 and the second gate unit 122 to be opposite, and thus, the turn-on or turn-off of the first gate unit 121 and the second gate unit 122 (the third gate unit 123) can be controlled by the same control signal line (the first control signal line Lc described later) without separately setting a control signal line for the control terminal of the first gate unit 121, the number of signal lines is reduced, the occupied area of the signal lines is reduced, and the process steps can be simplified.

Optionally, the pixel driving circuit 13 provided in the embodiment of the present invention may be 7T1C (7 transistors and 1 storage capacitor) or 2T1C (2 transistors and 1 storage capacitor), and the like, and the specific structure of the pixel driving circuit 13 is not limited in the embodiment of the present invention.

For example, fig. 6 is a schematic structural diagram of another sub-pixel shown in fig. 3, as shown in fig. 6, the pixel driving circuit 13 provided in the embodiment of the present invention includes 7T1C, that is, the pixel driving circuit 13 may include a driving transistor T, a Data writing transistor M4, a threshold compensation transistor M5, reset transistors M6 and M7, light emitting control transistors M8 and M9, and a storage capacitor Cst, wherein a first electrode of the light emitting control transistor M8 is electrically connected to a positive power supply terminal PVDD, a first electrode of the Data writing transistor M4 is electrically connected to a Data signal terminal Data, a gate of the Data writing transistor M4 and a gate of the threshold compensation transistor M5 may be electrically connected to a second Scan signal terminal Scan2, first electrodes of the reset transistors M6 and M7 are electrically connected to an initialization signal terminal Vref (the corresponding initialization signal terminals may be the same or different), a gate of the reset transistor M6 may be electrically connected to a first Scan signal terminal Scan1, the gate of the reset transistor M7 may be electrically connected to the first Scan signal terminal Scan1 or the second Scan signal terminal Scan2 (only electrically connected to the second Scan signal terminal Scan2 is exemplified in the figure), the gates of the emission control transistors M8 and M9 may be electrically connected to the emission control signal terminal Emit, respectively, the emission control transistor M9 is electrically connected to the anode of the first light-emitting element 111, and the cathode of the second light-emitting element 112 is electrically connected to the negative power supply terminal PVEE. As can be seen from the foregoing, the driving circuit 20 can be electrically connected to the pixel driving circuit 13 through, for example, a first scanning signal line, a second scanning signal line and a light-emitting control signal line, and specifically, the first scanning signal line is electrically connected to the first scanning signal terminal Scan1 to transmit a first scanning signal; the second Scan signal line is electrically connected to the second Scan signal terminal Scan2 for transmitting a second Scan signal; the light emission control signal line is electrically connected to the light emission control signal terminal Emit to transmit the light emission control signal. In addition, the display panel further includes a Data line, a positive power line, a negative power line, an initialization signal line (all shown in the figure), and the like, specifically, the Data line is electrically connected to the Data signal terminal Data to transmit a Data signal; the positive power line is electrically connected with the positive power end PVDD to transmit a positive power signal; the negative power line is electrically connected with the negative power supply end PVEE to transmit a negative power supply signal; the initialization signal line and the initialization signal terminal Vref are used for transmitting initialization signals. It should be noted that the driving principle of the pixel driving circuit 13 is similar to that of the pixel driving circuit of 7T1C in the prior art, and is not described herein again.

Optionally, when the first gating unit 121 is set to be on, the second gating unit 122 and the third gating unit 123 are turned off; alternatively, when the first gate unit 121 is turned off, the second gate unit 122 and the third gate unit 123 may be turned on in various ways, and a typical example will be described below.

Alternatively, fig. 7 is a schematic structural diagram of still another sub-pixel of fig. 3, and as shown in fig. 7, the control terminal C1 of the first gate unit 121 is electrically connected to the positive power signal line Lpvdd; the control terminal C2 of the second gating unit 122 and the control terminal C3 of the third gating unit 123 are electrically connected to the negative power supply signal line Lpvee, wherein the first gating unit 121 includes an NMOS transistor, and the second and

third gating units

122 and 123 include a PMOS transistor; alternatively, the control terminal C2 of the second gate unit 122 and the control terminal C3 of the third gate unit 123 are both electrically connected to the positive power supply signal line Lpvdd; the control terminal C1 of the first gating unit 121 is electrically connected to the negative power supply signal line Lpvee, wherein the first gating unit 121 includes a PMOS transistor, and the second and

third gating units

122 and 123 include NMOS transistors. It should be noted that, in fig. 7, the control terminal C2 of the second gate unit 122 and the control terminal C3 of the third gate unit 123 are both electrically connected to the positive power supply signal line Lpvdd; the control terminal C1 of the first gating unit 121 is electrically connected to the negative power signal line Lpvee, wherein the first gating unit 121 includes a PMOS transistor, and the second and

third gating units

122 and 123 include NMOS transistors for illustration.

Illustratively, with continued reference to fig. 7, the first gating unit 121 includes a PMOS transistor, and the second and

third gating units

122 and 123 include NMOS transistors, and when the gates of the NMOS transistors are electrically connected to the positive power signal line Lpvdd, the positive power signal transmitted by the positive power signal line Lpvdd controls the NMOS transistors to be turned on; when the gate of the PMOS transistor is electrically connected to the negative power signal line Lpvee, the negative power signal transmitted by the negative power signal line Lpvee controls the PMOS transistor to be turned on. When a defective sub-pixel is determined, for example, the gate of the PMOS transistor in the defective sub-pixel may be disconnected from the negative power signal line Lpvee by means of laser cutting, and the gate of the NMOS transistor continues to remain electrically connected to the positive power signal line Lpvdd, so that the first light-emitting element 111 and the second light-emitting element 112 of the defective sub-pixel are connected in parallel; in the non-defective sub-pixel, the gate of the NMOS transistor in the non-defective sub-pixel is disconnected from the positive power supply signal line Lpvdd and the gate of the PMOS transistor continues to be electrically connected to the negative power supply signal line Lpvee by means of, for example, laser cutting, so that the first light-emitting element 111 and the second light-emitting element 112 of the non-defective sub-pixel are connected in series. For example, the sub-pixel shown in fig. 7 is a defective sub-pixel, the gate of the PMOS transistor in the defective sub-pixel is disconnected from the negative power supply signal line Lpvee, and the gate of the NMOS transistor continues to remain electrically connected to the positive power supply signal line Lpvdd, so that the first light-emitting element 111 and the second light-emitting element 112 of the sub-pixel are connected in parallel.

In this embodiment, the control terminal C1 of the first gate unit 121, the control terminal C2 of the second control unit 122, and the control terminal C3 of the third gate unit 123 are electrically connected to the negative power signal line Lpvee and the positive power signal line Lpvdd originally in the display panel 100, and there is no need to separately provide a signal line for controlling the first gate unit 121, the second gate unit 122, and the third gate unit 123 to be turned on or off, so that the structure is simple, the number of control terminals on the driving chip 30 is reduced, and the chip cost is saved.

Alternatively, fig. 8 is a schematic structural diagram of another sub-pixel in fig. 3, and as shown in fig. 8, the control terminal C1 of the first gating unit 121 is electrically connected to the high-level signal line Lvgh; the control terminal C2 of the second gate unit 122 and the control terminal C3 of the third gate unit 123 are both electrically connected to the low-level signal line Lvgl, wherein the first gate unit 121 includes an NMOS transistor, and the second gate unit 122 and the third gate unit 123 include a PMOS transistor; alternatively, the control terminal C2 of the second gate unit 122 and the control terminal C3 of the third gate unit 123 are both electrically connected to the high-level signal line Lvgh; the control terminal C1 of the first gate unit 121 is electrically connected to the low-level signal line Lvgl, wherein the first gate unit 121 includes a PMOS transistor, and the second and

third gate units

122 and 123 include NMOS transistors. In fig. 8, the control terminal C2 of the second gate unit 122 and the control terminal C3 of the third gate unit 123 are both electrically connected to the high-level signal line Lvgh; the control terminal C1 of the first gate unit 121 is electrically connected to the low-level signal line Lvgl, wherein the first gate unit 121 includes a PMOS transistor, and the second gate unit 122 and the third gate unit 123 include NMOS transistors for example.

As can be seen from the foregoing, the driver chip 30 is electrically connected to the driver circuit 20 through a clock signal line, a high-level signal line, a low-level signal line, and the like, and supplies signals necessary for normal operation of the driver circuit 20 to the driver circuit 20 through the clock signal line, the high-level signal line, the low-level signal line, and the like.

In this embodiment, by electrically connecting the control terminal C1 of the first gate unit 121, the control terminal C2 of the second control unit 122, and the control terminal C3 of the third gate unit 123 to the high-level signal line Lvgh and the low-level signal line Lvgl, which are originally in the display panel 100, it is not necessary to separately provide signal lines for controlling the first gate unit 121, the second gate unit 122, and the third gate unit 123 to be turned on or off.

Illustratively, the first gating unit 121 includes a PMOS transistor, and the second gating unit 122 and the third gating unit 123 include NMOS transistors, and when the gates of the NMOS transistors are electrically connected to the high-level signal line Lvgh, the high-level signal transmitted by the high-level signal line Lvgh controls the NMOS transistors to be turned on; when the gate of the PMOS transistor is electrically connected to the low-level signal line Lvgl, the low-level signal transmitted by the low-level signal line Lvgl controls the PMOS transistor to be turned on. When a faulty sub-pixel is determined, for example, the gate of the PMOS transistor in the faulty sub-pixel can be disconnected from the low-level signal line Lvgl by means of laser cutting, and the gate of the NMOS transistor continues to be electrically connected to the high-level signal line Lvgh, so that the first light-emitting element 111 and the second light-emitting element 112 of the sub-pixel are connected in parallel; in the non-defective sub-pixel, for example, the gate of the NMOS transistor in the non-defective sub-pixel is disconnected from the high-level signal line Lvgh by laser cutting, and the gate of the PMOS transistor is continuously kept electrically connected to the low-level signal line Lvgl, so that the first light-emitting element 111 and the second light-emitting element 112 of the sub-pixel are connected in series. For example, if the sub-pixel shown in fig. 8 is a non-defective sub-pixel, the gate of the NMOS transistor in the non-defective sub-pixel is disconnected from the high-level signal line Lvgh, and the gate of the PMOS transistor is continuously electrically connected to the low-level signal line Lvgl, so that the first light-emitting element 111 and the second light-emitting element 112 of the sub-pixel are connected in series.

Optionally, fig. 9 is a schematic structural diagram of another sub-pixel in fig. 3, and as shown in fig. 9, the control terminal C1 of the first gate unit 121, the control terminal C2 of the second gate unit 122, and the control terminal C3 of the third gate unit 123 are all electrically connected to the second control signal line 40; the control terminal C1 of the first gate unit 121, the control terminal C2 of the second gate unit 122, and the control terminal C3 of the third gate unit 123 are also electrically connected to the third control signal line 50 through an isolation resistor R; in the light emitting stage of the light emitting module, the second control signal line 40 and the third control signal line 50 have opposite polarities of potentials.

Illustratively, the first gating unit 121 includes a PMOS transistor, the second gating unit 122 and the third gating unit 123 include NMOS transistors, the control terminal C1 of the first gating unit 121, the control terminal C2 of the second gating unit 122 and the control terminal C3 of the third gating unit 123 are electrically connected to a first control signal line Lc, the first control signal line Lc is electrically connected to the second control signal line 40, and the first control signal line Lc is also electrically connected to the third control signal line 50 through an isolation resistor R. The signal transmitted by the second control signal line 40 in the light emitting phase is a low level signal, and may be electrically connected to the first control signal line Lc through a low resistance (the resistance value is less than 100 ohms) wire, for example, at this time, the signal transmitted by the first control signal line Lc is a low level signal, the first gating unit 121 is turned on, the second gating unit 122 and the third gating unit 123 are turned off, and the first light emitting element 111 and the second light emitting element 112 are connected in series. Even if the signal transmitted by the third control signal line 50 is at a high level, the signal transmitted by the first control signal line Lc is not affected by the signal transmitted by the third control signal line 50 due to the existence of the isolation resistor R, i.e., the signal transmitted by the first control signal line Lc cannot be raised. After the faulty sub-pixel is determined, the number of the faulty sub-pixels is generally small, so that the connection line between the first control signal line Lc and the second control signal line 40 in the faulty sub-pixel can be blown by a laser cutting scheme, as shown in fig. 9, in the light emitting stage, the high level transmitted by the third control signal line 50 is transmitted to the first control signal line Lc through the isolation resistor R, so that the first gating unit 121 in the faulty sub-pixel is turned off, the second gating unit 122 and the third gating unit 123 are turned on, and at this time, the first light emitting element 111 and the second light emitting element 112 are connected in parallel. That is, the high level transmitted by the third control signal line 50 is isolated by the isolation resistor R, so that the low level transmitted by the second control signal line 40 is transmitted to the first control signal line Lc, and further the first gate unit 121 of the non-faulty sub-pixel is turned on, the second gate unit 122 and the third gate unit 123 are turned off, and the first light emitting element 111 and the second light emitting element 112 are connected in series. Since the number of the faulty sub-pixels is small, in order to transmit the high-level signal to the first control signal line Lc through the isolation resistor R, the connection line between the first control signal line Lc and the second control signal line 40 needs to be cut off, that is, only the connection line between the first control signal line Lc and the second control signal line 40 in the faulty sub-pixel needs to be cut off (the number of the cut-off lines is small), and the process steps are simplified.

Optionally, with continued reference to fig. 9, the second control signal line 40 comprises a light emission control signal line; the third control signal line 50 includes a scan signal line.

Illustratively, the first gating unit 121 includes a PMOS transistor, the second gating unit 122 and the third gating unit 123 include NMOS transistors, the control terminal C1 of the first gating unit 121, the control terminal C2 of the second gating unit 122 and the control terminal C3 of the third gating unit 123 are electrically connected to a first control signal line Lc, the first control signal line Lc is electrically connected to the light emission control signal line, and the first control signal line Lc is also electrically connected to the scanning signal line through an isolation resistor R. The signal transmitted by the light-emitting control signal line in the light-emitting stage is a low-level signal, and may be electrically connected to the first control signal line Lc through a low-resistance (resistance value less than 100 ohms) wire, for example. The signal transmitted by the first control signal line Lc is a low level signal, the first gate unit 121 is turned on, the second gate unit 122 and the third gate unit 123 are turned off, and the first light emitting element 111 and the second light emitting element 112 are connected in series. Even if the signal transmitted by the scan signal line is at a high level, the signal transmitted by the first control signal line Lc is not affected by the signal transmitted by the scan signal line due to the existence of the isolation resistor R, i.e., the signal transmitted by the first control signal line Lc cannot be raised. After the faulty sub-pixel is determined, the number of the faulty sub-pixels is generally small, so that the connecting line between the first control signal line Lc and the light-emitting control signal line in the faulty sub-pixel can be blown by a laser cutting scheme, as shown in fig. 9, in the light-emitting stage, the high level transmitted by the scanning signal line is transmitted to the first control signal line Lc through the isolation resistor R, the first gating unit 121 in the faulty sub-pixel is turned off, the second gating unit 122 and the third gating unit 123 are turned on, and at this time, the first light-emitting element 111 and the second light-emitting element 112 are connected in parallel.

It should be noted that the second control signal line 40 and the third control signal line 50 include, but are not limited to, a light-emitting control signal line and a scanning signal line, as long as the polarities of the second control signal line 40 and the third control signal line 50 are opposite in the light-emitting phase, and for example, the polarities may be: the second control signal line 40 includes a negative power supply signal line, and the third control signal line 50 includes a positive power supply signal line; alternatively, the second control signal line 40 includes a low-level signal line; the third control signal line 50 includes a high-level signal line. The original signal lines of the display panel are multiplexed into the second control signal line 40 and the third control signal line 50, so that the signal lines do not need to be separately arranged, the structure is simple, the number of control ends on the driving chip 30 is reduced, and the chip cost is saved.

Optionally, the resistance of the isolation resistor R is a1, a1 is greater than or equal to 10k Ω, and the resistance of the isolation resistor R is set to be greater than or equal to 10k Ω, so that even if the signal transmitted by the third control signal line 50 is a high-level signal, the high-level signal cannot be transmitted to the first control signal line Lc at all due to the higher resistance of the isolation resistor R.

Optionally, fig. 10 is a schematic structural diagram of another display panel provided in an embodiment of the present invention, and it should be noted that a specific structure of the sub-pixel shown in fig. 10 is the same as that of the sub-pixel in fig. 5, so that the specific structure of the sub-pixel is not shown here, and when the following description is provided, reference may be made to the specific structure of the sub-pixel shown in fig. 5.

Referring to fig. 5 and 10, the control terminal C1 of the first gate unit 121, the control terminal C2 of the second gate unit 122, and the control terminal C3 of the third gate unit 123 of each sub-pixel 10 in the same row are electrically connected. Optionally, the control terminal C1 of the first gating unit 121, the control terminal C2 of the second gating unit 122, and the control terminal C3 of the third gating unit 123 are electrically connected to the first control signal line Lc, the first control signal line Lc is electrically connected to the second control signal line 40 and the third control signal line 50, respectively, in a light emitting stage of the light emitting module, the polarities of the potentials of the second control signal line 40 and the third control signal line 50 are opposite, for example, the signal transmitted by the second control signal line 40 is a low level signal, and the signal transmitted by the third control signal line 50 is a high level signal.

In the present embodiment, the control terminal C1 of the first gating unit 121, the control terminal C2 of the second gating unit 122 and the control terminal C3 of the third gating unit 123 of each sub-pixel 10 in the same row are electrically connected, so that the sub-pixels 10 in a row share the second control signal line 40 and the third control signal line 50, wherein when one or more sub-pixels 10 in the row have a failure, the on or off state of the first gating unit 121 in the sub-pixel 10 in the row is the same, and the on or off state of the second gating unit 122 and the third gating unit 123 is the same, so that only one time of the electrical connection between the first control signal line Lc and the third control signal line 50 or between the first control signal line Lc and the second control signal line 40 needs to be cut off in a sub-pixel row, and each sub-pixel 10 does not need to cut off the electrical connection between the first control signal line Lc and the third control signal line 50 or between the first control signal line Lc and the second control signal line 40, thus, the process steps are simplified.

Illustratively, if at least one sub-pixel 10 in the first sub-pixel row is damaged, and at least one sub-pixel 10 in the second sub-pixel row is damaged, while sub-pixels in other sub-pixel rows are not damaged, the first control signal line Lc is electrically disconnected from the second control signal line 40 in the first sub-pixel row, the first control signal line Lc is electrically disconnected from the second control signal line 40 in the second sub-pixel row, and the first control signal line Lc is electrically disconnected from the third control signal line 50 in other sub-pixel rows, respectively.

Optionally, fig. 11 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 11, after being electrically connected, the control terminal C1 of the first gating unit 121, the control terminal C2 of the second gating unit 122, and the control terminal C3 of the third gating unit 123 are electrically connected to a first control signal line Lc, the first control signal line Lc is electrically connected to the third control signal line 50 through an isolation resistor R, and the first control signal line Lc is directly electrically connected to the second control signal line 40; in the light emitting stage of the light emitting module, the potentials of the second control signal line 40 and the third control signal line 50 are opposite in polarity, for example, the signal transmitted by the second control signal line 40 is a low level signal, and the signal transmitted by the third control signal line 50 is a high level signal.

In this embodiment, when the second control signal line 40 is directly electrically connected to the first control signal line Lc, the low level signal transmitted by the second control signal line 40 is transmitted to the first control signal line Lc, the low level signal is transmitted on the first control signal line Lc, the first gate unit 121 electrically connected to the first control signal line Lc is turned on, the second gate unit 122 and the third gate unit 123 are turned off, and the first light emitting element 111 and the second light emitting element 112 are connected in series. By providing the isolation resistor R between the third control signal line 50 and the first control signal line Lc, even if the signal transmitted through the third control signal line 50 is a high level signal, the high level signal cannot change the signal transmitted through the first control signal line Lc, that is, a low level signal is still transmitted through the first control signal line Lc, the first gating unit 121 electrically connected to the first control signal line Lc is turned on, the second gating unit 122 and the third gating unit 123 are turned off, and the first light emitting element 111 and the second light emitting element 112 are connected in series. If it is determined that one or more sub-pixels 10 in one of the sub-pixel rows are damaged, the electrical connection between the first control signal line Lc and the second control signal line 40 in the sub-pixel row is cut off, at this time, a high level signal transmitted on the third control signal line 50 is transmitted to the first control signal line Lc through the isolation resistor R, the first gating unit 121 electrically connected with the first control signal line Lc is disconnected, the second gating unit 122 and the third gating unit 123 are turned on, and the first light emitting element 111 and the second light emitting element 112 are connected in parallel. In this way, only the electrical connection between the first control signal line Lc and the second control signal line 40 of the sub-pixel row with the damage needs to be cut off, and each sub-pixel row does not need to be cut off, so that the process steps are further simplified, and the occupied area of each sub-pixel 10 can be reduced.

Illustratively, if at least one of the sub-pixels 10 in the second sub-pixel row is damaged and the other sub-pixel rows are not damaged, the electrical connection between the first control signal line Lc and the second control signal line 40 in the second sub-pixel row only needs to be cut off, and the electrical connection between the other sub-pixel rows does not need to be cut off.

Optionally, fig. 12 is a schematic structural diagram of another sub-pixel in fig. 3, as shown in fig. 12, the display panel 100 further includes a storage module 60, an output end of the storage module 60 is electrically connected to a control end of the gating module 12, and a data end of the storage module 60 is electrically connected to a data signal end of the pixel driving circuit 13.

In this embodiment, a storage module 60 is disposed in each sub-pixel 10, and after a faulty sub-pixel 10 is determined, a corresponding signal is stored in the storage module 60 of the faulty sub-pixel 10, so that the storage module 60 outputs a corresponding level signal through its output terminal during a light emitting phase, where the level signal is, for example, a high level signal, and further the first gating unit 121 of the faulty sub-pixel is turned off, the second gating unit 122 and the third gating unit 123 are turned on, and the first light emitting element 111 and the second light emitting element 112 are connected in parallel. The storage module 60 of the non-faulty sub-pixel 10 stores a corresponding signal, so that the storage module 60 outputs a corresponding level signal through its output terminal during the light-emitting phase, the level signal is, for example, a low level signal, so that the first gating unit 121 of the non-faulty sub-pixel is turned on, the second gating unit 122 and the third gating unit 123 are turned off, and the first light-emitting element 111 and the second light-emitting element 112 are connected in series. In addition, in this embodiment, the data terminal of the storage module 60 is electrically connected to the data signal terminal of the pixel driving circuit 13, that is, after the faulty sub-pixel is determined, when the storage module 60 stores a corresponding signal, for example, the signal can be stored in the storage module 60 by the mutual cooperation of the storage module control line and the storage module data line, where the storage module control line can be multiplexed as, for example, a light-emitting control signal line or a scanning signal line of the display panel; alternatively, the memory module data lines may be multiplexed into data lines of a display panel, for example, without separately providing corresponding signal lines for the memory module 60, thereby simplifying the process steps.

Alternatively, the memory module 60 may include a device having a memory function, such as a register.

The embodiment of the present invention further provides a method for configuring light emitting elements of a display panel, where the display panel in the above embodiment is adopted in the method for configuring light emitting elements of a display panel, and the method is the same inventive concept as the above display panel, and reference may be made to the description in the above embodiment of the display panel without detailed description in this embodiment. Fig. 13 is a flowchart of a method for configuring light emitting elements of a display panel according to an embodiment of the present invention, and as shown in fig. 13, the method for configuring light emitting elements of the display panel includes:

s110, controlling the first gating unit to be conducted, and controlling the second gating unit and the third gating unit to be disconnected so as to enable the first light-emitting element and the second light-emitting element of the sub-pixel to be connected in series;

s120, performing display test on the display panel, and determining a fault sub-pixel according to a test display picture;

and S130, controlling the first gating unit corresponding to the failure sub-pixel to be disconnected, and controlling the second gating unit and the third gating unit to be connected so that the first light-emitting element and the second light-emitting element are connected in parallel.

Illustratively, the driving method of the display panel provided by the embodiment of the present invention is applied to the display panel shown in fig. 3 and fig. 4, as shown in fig. 3 and fig. 4, in the testing stage, the first gate unit 121 in all the sub-pixels 10 is turned on, the second gate unit 122 and the third gate unit 123 are turned off, that is, the first light-emitting element 111 and the second light-emitting element 112 in all the sub-pixels 10 are in a serial state, then the pixel driving circuit 13 provides the driving current for the light-emitting module 11 corresponding thereto, drives the light-emitting module 11 to emit light, then determines the sub-pixel 10 which is faulty according to the display screen, that is, the faulty sub-pixel, where the faulty sub-pixel may be a failure of one of the light-emitting elements, for example, the first light-emitting element 111 or the second light-emitting element 112, at this time, the first gate unit 121 may be turned off, the second gate unit 122 and the third gate unit 123 are turned on, the first light emitting element 111 and the second light emitting element 112 in the defective sub-pixel are connected in parallel, and at this time, even if one of the light emitting elements is damaged, the other light emitting element can emit light instead of the lost light emitting element, and display of the sub-pixel is realized. That is to say, in the display stage, the first light emitting element 111 and the second light emitting element 112 in the faulty sub-pixel are connected in parallel, but the first light emitting element 111 and the second light emitting element 112 in the non-faulty sub-pixel are connected in series, so that the high manufacturing yield can be ensured, the low power consumption requirement can be met, and the problem that the prior art cannot meet the requirements of high manufacturing yield and low power consumption at the same time is solved.

Alternatively, fig. 14 is a flowchart of a method for configuring light emitting elements of a display panel according to an embodiment of the present invention, where the method for configuring light emitting elements of a display panel is applied to the display panels shown in fig. 3 and 9 in the foregoing embodiments. As shown in fig. 9, the control terminal C1 of the first gate unit 121, the control terminal C2 of the second gate unit 122, and the control terminal C3 of the third gate unit 123 are all electrically connected to the second control signal line 40; the control terminal C1 of the first gate unit 121, the control terminal C2 of the second gate unit 122, and the control terminal C3 of the third gate unit 123 are also electrically connected to the third control signal line 50 through an isolation resistor R; in the light emitting stage of the light emitting module, the second control signal line and the third control signal line have opposite potential polarities. For example, the control terminal C1 of the first gate unit 121, the control terminal C2 of the second gate unit 122 and the control terminal C3 of the third gate unit 123 are electrically connected first and then electrically connected to the first control signal line Lc, the first control signal line Lc is electrically connected to the second control signal line 40 directly, and the first control signal line Lc is electrically connected to the third control signal line 50 through the isolation resistor R. As shown in fig. 14, the method for configuring light emitting elements of the display panel of the present embodiment includes:

s210, controlling the first gating unit to be conducted, and controlling the second gating unit and the third gating unit to be disconnected so as to enable the first light-emitting element and the second light-emitting element of the sub-pixel to be connected in series;

s220, performing display test on the display panel, and determining a fault sub-pixel according to a test display picture;

s230, controlling the first gating unit corresponding to the fault sub-pixel to be cut off from the second control signal line so as to disconnect the first gating unit; the third control signal line gates the second gate unit and the third gate unit to be turned on so that the first light emitting element and the second light emitting element are connected in parallel.

Illustratively, as shown in fig. 3 and 9, the signal transmitted by the second control signal line 40 in the light emitting phase is a low level signal, and may be electrically connected to the first control signal line Lc through a low resistance (resistance value less than 100 ohms) wire, for example. The signal transmitted by the first control signal line Lc is a low level signal, the first gate unit 121 is turned on, the second gate unit 122 and the third gate unit 123 are turned off, and at this time, the first light emitting element 111 and the second light emitting element 112 are connected in series. Even if the signal transmitted by the third control signal line 50 is at a high level, the signal transmitted by the first control signal line Lc is not affected by the signal transmitted by the third control signal line 50 due to the existence of the isolation resistor R, i.e., the signal transmitted by the first control signal line Lc cannot be raised. After the faulty sub-pixel is determined, the number of the faulty sub-pixels is generally small, so that the connection line between the first control signal line Lc and the second control signal line 40 in the faulty sub-pixel can be blown by a laser cutting scheme, as shown in fig. 9, in the light emitting stage, the high level transmitted by the third control signal line 50 is transmitted to the first control signal line Lc through the isolation resistor R, the first gating unit 121 in the faulty sub-pixel is turned off, the second gating unit 122 and the third gating unit 123 are turned on, and at this time, the first light emitting element 111 and the second light emitting element 112 are connected in parallel. That is, the high level transmitted by the third control signal line 50 is isolated by the isolation resistor, so that the low level transmitted by the second control signal line 40 is transmitted to the first control signal line Lc, and further the first gate unit 121 of the non-faulty sub-pixel is turned on, the second gate unit 122 and the third gate unit 123 are turned off, and the first light emitting element 111 and the second light emitting element 112 are connected in series. Since the number of the faulty sub-pixels is small, the second cut-off is needed to transmit the high-level signal to the first through the isolation resistor, so that only the connection in the faulty sub-pixel needs to be cut off (the number of the cut-off is small), and each sub-pixel does not need to be cut off, thereby simplifying the process steps while realizing.

Optionally, with continuing reference to fig. 3 and fig. 12, the display panel 100 further includes a storage module 60, the output terminals of the storage module 60 are respectively electrically connected to the control terminal of the gating module 12, and the data terminal of the storage module 60 is electrically connected to the data signal terminal of the pixel driving circuit, and the method further includes:

the output end of the storage module outputs a first control signal to gate the first gating unit;

and according to the display picture, the output end of the storage module outputs a second control signal to gate off the first gating unit corresponding to the position where the sub-pixel has the fault, and gate the second gating unit and the third gating unit.

In this embodiment, a storage module 60 is disposed in each sub-pixel 10, and after a faulty sub-pixel 10 is determined, a corresponding signal is stored in the storage module 60 of the faulty sub-pixel 10, so that the storage module 60 outputs a corresponding level signal through its output terminal at least in a light emitting stage, where the level signal is, for example, a high level signal, and further the first gating unit 121 of the faulty sub-pixel is turned off, the second gating unit 122 and the third gating unit 123 are turned on, and the first light emitting element 111 and the second light emitting element 123 are connected in parallel. The storage module 60 of the non-faulty sub-pixel 10 stores a corresponding signal, so that the storage module 60 outputs a corresponding level signal through its output terminal at least in the light-emitting stage, the level signal is, for example, a low level signal, so that the first gating unit 121 of the non-faulty sub-pixel is turned on, the second gating unit 122 and the third gating unit 123 are turned off, and the first light-emitting element 111 and the second light-emitting element 123 are connected in series. In addition, in this embodiment, the data terminal of the storage module 60 is electrically connected to the data signal terminal of the pixel driving circuit 13, that is, after the faulty sub-pixel is determined, when the storage module 60 stores a corresponding signal, for example, the signal can be stored in the storage module 60 by the mutual cooperation of the storage module control line and the storage module data line, where the storage module control line can be multiplexed as, for example, a light-emitting control signal line or a scanning signal line of the display panel; alternatively, the memory module data lines may be multiplexed into data lines of a display panel, for example, without separately providing corresponding signal lines for the memory module 60, thereby simplifying the process steps.

Alternatively, fig. 15 is a flowchart of a method for configuring light emitting elements of a display panel according to an embodiment of the present invention, where the method for configuring light emitting elements of a display panel is applied to the display panel shown in fig. 10 in the foregoing embodiment. As shown in fig. 10, the transistor type of the first gate cell is opposite to the transistor conductivity type of the second gate cell; the transistor type of the second gating unit is the same as the transistor conductivity type of the third gating unit (not shown in fig. 10); the control end of the first gating unit, the control end of the second gating unit and the control end of the second gating unit of each sub-pixel in the same row are electrically connected. As shown in fig. 15, the method for configuring light emitting elements of the display panel of the present embodiment includes:

s310, controlling the first gating unit to be conducted, and controlling the second gating unit and the third gating unit to be disconnected so as to enable the first light-emitting element and the second light-emitting element of the sub-pixel to be connected in series;

s320, performing display test on the display panel, and determining a fault sub-pixel according to a test display picture;

s330, controlling the first gating unit corresponding to each sub-pixel of the row where the fault sub-pixel is located to be disconnected, and controlling the second gating unit and the third gating unit to be connected, so that the first light-emitting element and the second light-emitting element corresponding to each sub-pixel of the row where the fault sub-pixel is located are connected in parallel.

In the present embodiment, as shown in fig. 10 and 5, the control terminal C1 of the first gating unit 121, the control terminal C2 of the second gating unit 122 and the control terminal C3 of the third gating unit 123 of each sub-pixel 10 in the same row are electrically connected, so that the sub-pixels 10 in a row share the second control signal line 40 and the third control signal line 50, wherein when one or more sub-pixels 10 in the row fail, the on or off state of the first gating unit 121 in the sub-pixel 10 in the row is the same, and the on or off state of the second gating unit 122 and the third gating unit 123 is the same, so that the electrical connection of the first control signal line Lc to the third control signal line 50 or to the second control signal line 40 only needs to be cut off once in a sub-pixel row without cutting off the electrical connection of the first control signal line Lc to the third control signal line 50 or to the second control signal line 40 in each sub-pixel 10, thus, the process steps are simplified.

Based on the same inventive concept, the embodiment of the invention also provides a display device, and the display device comprises any one of the display panels provided by the above embodiments. Illustratively, as shown in fig. 16, the display device 1000 includes a display panel 100. Therefore, the display device also has the advantages of the display panel in the above embodiments, and the same points can be understood by referring to the explanation of the display panel above, which is not described in detail below.

The display device 1000 provided in the embodiment of the present invention may be a mobile phone as shown in fig. 16, and may also be any electronic product with a display function, including but not limited to the following categories: the touch screen display system comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, industrial control equipment, a medical display screen, a touch interaction terminal and the like, and the embodiment of the invention is not particularly limited in this respect.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements and substitutions will now be apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel includes a plurality of sub-pixels; each sub-pixel comprises a light emitting module, a gating module and a pixel driving circuit;

the light emitting module includes a first light emitting element and a second light emitting element;

if the first gating unit is conducted, the second gating unit and the third gating unit are disconnected, and the first light-emitting element and the second light-emitting element are connected in series; if the first gating unit is disconnected, the second gating unit and the third gating unit are conducted, and the first light-emitting element and the second light-emitting element are connected in parallel;

the gating module is used for controlling the first light-emitting element and the second light-emitting element in each sub-pixel to be connected in series to determine a fault sub-pixel, and controlling the first light-emitting element and the second light-emitting element of the fault sub-pixel to be connected in parallel and the first light-emitting element and the second light-emitting element in a non-fault sub-pixel to be connected in series after the fault sub-pixel is determined.

2. The display panel according to claim 1, wherein the first gate unit is connected in series between the first light emitting element and the second light emitting element; the input end of the second gating unit is electrically connected with the cathode of the first light-emitting element; the output end of the second gating unit is electrically connected with the cathode of the second light-emitting element; the input end of the third gating unit is electrically connected with the anode of the first light-emitting element; and the output end of the third gating unit is electrically connected with the positive electrode of the second light-emitting element.

3. The display panel according to claim 2, wherein the first gate unit includes a first transistor, the second gate unit includes a second transistor, and the third gate unit includes a third transistor;

a first end of the first transistor is electrically connected to a negative electrode of the first light-emitting element, and a second end of the first transistor is electrically connected to a positive electrode of the second light-emitting element;

a first end of the second transistor is electrically connected to a negative electrode of the first light-emitting element, and a second end of the second transistor is electrically connected to a negative electrode of the second light-emitting element;

a first end of the third transistor is electrically connected to a positive electrode of the first light-emitting element, and a second end of the third transistor is electrically connected to a positive electrode of the second light-emitting element.

4. The display panel according to claim 1, wherein a transistor conductivity type of the second gate unit is the same as a transistor conductivity type of the third gate unit; and the control end of the second gating unit is electrically connected with the control end of the third gating unit.

5. The display panel according to claim 4, wherein the first gate unit and the second gate unit have opposite conductivity types; the control end of the first gating unit, the control end of the second gating unit and the control end of the third gating unit are electrically connected.

6. The display panel according to claim 5, wherein control terminals of the first gate unit, the second gate unit, and the third gate unit are electrically connected to a first control signal line.

7. The display panel according to claim 5, wherein the control terminal of the first gate unit, the control terminal of the second gate unit, and the control terminal of the third gate unit are electrically connected to a second control signal line;

the control end of the first gating unit, the control end of the second gating unit and the control end of the third gating unit are also electrically connected with a third control signal line through an isolation resistor; in a light emitting stage of the light emitting module, the second control signal line and the third control signal line have opposite potential polarities.

8. The display panel according to claim 7, wherein the second control signal line includes a negative power supply signal line; the third control signal line includes a positive power signal line.

9. The display panel according to claim 7, wherein the second control signal line comprises a low-level signal line; the third control signal line includes a high level signal line.

10. The display panel according to claim 7, wherein the second control signal line comprises a light emission control signal line; the third control signal line includes a scan signal line.

11. The display panel of claim 7, wherein the isolation resistor has a resistance of A1, A1 ≧ 10 kOmega.

12. The display panel according to claim 5, wherein the control terminals of the first gate unit, the second gate unit and the third gate unit of each sub-pixel in the same row are electrically connected.

13. The display panel according to claim 1, wherein the display panel further comprises a storage module, an output terminal of the storage module is electrically connected to the control terminal of the gate module, and a data terminal of the storage module is electrically connected to the data signal terminal of the pixel driving circuit.

14. A display device characterized by comprising the display panel according to any one of claims 1 to 13.

15. A method of arranging light emitting elements of a display panel, using the display panel according to any one of claims 1 to 13, the method comprising:

16. The method of claim 15, wherein the control terminal of the first gate unit, the control terminal of the second gate unit, and the control terminal of the third gate unit are electrically connected to a second control signal line; the control end of the first gating unit, the control end of the second gating unit and the control end of the third gating unit are also electrically connected with a third control signal line through an isolation resistor; in a light emitting stage of the light emitting module, the polarity of the potentials of the second control signal line and the third control signal line is opposite; the controlling the first gating unit corresponding to the failed sub-pixel to be turned off, and the second gating unit and the third gating unit to be turned on so that the first light emitting element and the second light emitting element are connected in parallel includes:

controlling the first gating unit corresponding to the fault sub-pixel to be cut off from the second control signal line so as to disconnect the first gating unit;

the third control signal line gates the second and third gate units to be turned on so that the first and second light emitting elements are connected in parallel.

17. The method of claim 15, wherein the display panel further comprises a memory module, the output terminals of the memory module are electrically connected to the control terminal of the gate module, the data terminal of the memory module is electrically connected to the data signal terminal of the pixel driving circuit, and the method further comprises:

according to a display picture, the output end of the storage module outputs a second control signal to gate off the first gating unit corresponding to the position where the sub-pixel has the fault, and gates the second gating unit and the third gating unit.

18. The light-emitting element arrangement method according to claim 15, wherein a transistor type of the first gate unit is opposite to a transistor conductivity type of the second gate unit; the transistor type of the second gating unit is the same as the transistor conduction type of the third gating unit; the control end of the first gating unit, the control end of the second gating unit and the control end of the third gating unit of each sub-pixel in the same row are electrically connected;

the controlling the failure sub-pixel corresponding to the first gating unit is turned off, and the second gating unit and the third gating unit are turned on to connect the first light emitting element and the second light emitting element in parallel, including:

and controlling the first gating unit corresponding to each sub-pixel of the row where the fault sub-pixel is located to be disconnected, and controlling the second gating unit and the third gating unit to be connected so that the first light-emitting element and the second light-emitting element corresponding to each sub-pixel of the row where the fault sub-pixel is located are connected in parallel.