CN113223571B - Reading method and circuit of ferroelectric memory - Google Patents
Reading method and circuit of ferroelectric memory Download PDFInfo
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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Abstract
The invention discloses a reading circuit of a ferroelectric memory, which comprises a data sensing unit, a data storage unit and a data storage unit, wherein the data sensing unit comprises two groups of data sensing circuits and corresponding data latches, the two groups of data sensing circuits are respectively used for acquiring data in two different addresses, and only the lowest bits of the two different addresses are different; the input end of the data selector is respectively connected to the output ends of the first data latch and the second data latch, and the control end of the data selector receives the last bit of the address information; and the input end of the data transmission circuit is connected to the output end of the data selector, and the data transmission circuit is used for converting the parallel signals output by the data selector into serial signals and then outputting the serial signals.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a method and a circuit for reading a ferroelectric memory.
Background
In recent years, ferroelectric memories have received increasing attention as a new type of memory with high writing speed and high number of reading and writing. Ferroelectric memory is a special process nonvolatile memory. When an electric field is applied to a ferroelectric transistor, the central atoms stay in a first low energy state along the electric field, and when an electric field reversal is applied to the same ferroelectric transistor, the central atoms move in the crystal along the direction of the electric field and stay in a second low energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, which form polarized charges under the action of an electric field. The ferroelectric domain is inverted under the electric field to form high polarized charge, the ferroelectric domain is not inverted under the electric field to form low polarized charge, and the binary stable state of the ferroelectric material enables the ferroelectric to be used as a memory.
After the electric field is removed, the central atom is kept in a low-energy state, and the state of the memory is kept and cannot disappear, so that the memory cell can be judged to be in a '1' state or a '0' state by high-polarization charge formed by inversion or low-polarization charge formed by non-inversion of the ferroelectric domain under the electric field. The inversion of ferroelectric domains does not require a high electric field, but can change the state of "1" or "0" of the memory cell with only a general operating voltage; nor does a charge pump need to generate a high voltage for data erasure, and thus there is no erasure delay. The characteristics enable the ferroelectric memory to continue to store data after power failure, and the ferroelectric memory has high writing speed, infinite writing life and difficult writing damage. Moreover, ferroelectric memories have higher writing speeds and longer read and write lives than existing nonvolatile memory technologies.
Reading of ferroelectric memory as shown in fig. 1, when reading data stored in a ferroelectric cell, the data stored in the cell is judged by the potential difference between the bit line bl and the reference line of the cell. As shown in the figure, when the stored data of the corresponding cell of bl <0>, wl0 is read, the voltage of wl0 is set at high level, so that the source-drain path of the transmission transistor connected with wl0 is conducted, which is equivalent to the fact that the storage node bl0 is directly connected to the bit line bl <0>, the corresponding reference point blref0 is connected to the reference line blref <0> according to the same principle, and at this time, the data stored in the cell can be judged by the potential difference between the bit line and the reference line. Since the magnitude of the potential difference between the bit line and the reference line is generally difficult to directly measure, in practical applications, a sensing circuit is added between the bit line and the reference line, which includes a sense amplifier and a corresponding circuit, to differentially amplify the small signals on the bit line and the reference line into identifiable standard logical values of "1" and "0". Meanwhile, according to the requirement of the read operation, after receiving the address, the data stored by the address must be read out in one clock period, so the speed requirement of the sensing circuit is high. However, the speed of the sensing circuit is limited by chip performance and manufacturing cost.
Disclosure of Invention
In view of some or all of the problems in the prior art, one aspect of the present invention is a reading circuit for a ferroelectric memory, comprising:
the data sensing unit comprises two groups of data sensing circuits and corresponding first data latches and second data latches;
the data selection unit comprises a data selector, wherein the input ends of the data selector are respectively connected to the output ends of the first data latch and the second data latch, and the control end of the data selector receives the last bit of address information;
and the data transmission unit is used for converting the parallel signals output by the data selector into serial signals and outputting the serial signals.
Further, the data transmission unit includes:
a counter circuit unit for counting according to an input clock signal to generate a count signal;
a decoder circuit unit for receiving the count signal generated by the counter circuit unit and generating a selection signal according to the count signal;
a multiplexer circuit unit which receives output data of the data selector and controls a selection switch according to the selection signal to convert the output data into a serial input signal; and
and the D trigger is connected to the output end of the multiplexer circuit unit and outputs the serial signal data under the control of a trigger signal and an inverted clock signal.
Further, the trigger signal includes:
a first trigger pulse generated by the first trigger circuit when the data in the two addresses are latched; and
the second trigger pulse is generated by the second trigger circuit when the last bit address information is received.
Further, the first trigger circuit includes a first rising edge trigger which is input as a data latch completion signal.
Further, the second trigger circuit includes:
an inverter which inputs a last-bit reception completion signal which is address information; and
a second rising edge trigger connected to the output of the inverter.
Based on the reading circuit, the invention also provides a reading method of the ferroelectric memory, which comprises the following steps:
after receiving the first 7 bits of address information, data in two addresses which are possibly corresponding to the first and second data latches are respectively latched into the first and second data latches:
if the last bit of the address information is received after the latching is completed, determining the address information according to the last bit of the received address information, and outputting the data latched in the first data latch or the second data latch as read data according to the address information; and
outputting one invalid data if the last bit of the address information is not received temporarily when the latching is completed; and after receiving the last bit of the address information, determining the address information according to the last bit of the received address information, and outputting the data latched in the first data latch or the second data latch as read data according to the address information.
Further, the outputting of the read data includes:
selecting, by the data selector, data latched in the first data latch or the second data latch;
the data is converted into serial data after passing through a data transmission circuit; and
after receiving the trigger signal, the serial data is output bit by bit.
Further, the reading method further includes:
if the last bit of the address information is received, the data latch is not completed, and one-bit invalid data is output.
The invention also provides a ferroelectric memory comprising a read circuit as described above.
The invention provides a method and a circuit for reading a ferroelectric memory, which start data reading operation after receiving the address information of the last two bits, at this time, because the lowest bit of the address information is not received temporarily, there may be two situations, namely, the lowest bit of the address information is 0 or 1, the data in the address information corresponding to the two situations are all read, and are respectively latched into different data latches, and then one of the data latches is determined to output after the lowest bit of the address information is received. In this way, the sensing circuit senses and latches data more than a clock cycle compared to a conventional read operation, which results in a relatively low performance requirement for the sensing circuit at the same read rate, even though the cost of the read circuit can be effectively controlled.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
FIG. 1 shows a read schematic of a ferroelectric memory according to one embodiment of the present invention;
fig. 2 is a schematic diagram showing a structure of a reading circuit of a ferroelectric memory according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing a structure of a data sensing unit according to an embodiment of the present invention;
fig. 4 is a schematic diagram showing the structure of a data transmission unit according to an embodiment of the present invention;
FIG. 5 shows a timing diagram of read data output of a ferroelectric memory according to one embodiment of the present invention; and
fig. 6 shows a timing diagram of trigger signal generation according to an embodiment of the present invention.
Detailed Description
In the following description, the present invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that the embodiments of the present invention describe the process steps in a specific order, however, this is merely to illustrate the specific embodiment and not to limit the order of the steps. In contrast, in various embodiments of the present invention, the order of the steps may be adjusted according to process adjustments.
The present invention may be related to memories, and in particular to ferroelectric memories. According to one embodiment of the present invention, each memory cell of the memory of the present invention comprises a transistor and a ferroelectric capacitor, wherein the transistor is a CMOS transistor comprising a gate, a source and a drain, the source or drain of the transistor being connected to one plate of the ferroelectric capacitor. The gates of the transistors of the memory cells of the same lateral row are commonly connected to the same word line wl. The sources of the transistors of the memory cells of the same vertical column are commonly connected to the same bit line bl. The ferroelectric capacitors of the memory cells are commonly connected to the same common plate line PL away from the plates of the transistors.
In order to have more sensing time to complete the reading of data, the invention provides a reading method of the ferroelectric memory, which starts the data reading operation after receiving the penultimate address information. At this time, since the lowest order bit of the address information is not received temporarily, there may be two cases in which the lowest order bit of the address information is "0" or "1", and the addresses corresponding to the lowest order bit of the address information being "0" or "1" are respectively referred to as "bank 0" and "bank 1". And respectively reading the data in the bank 0 and the bank 1 through a sensing circuit, latching the data into different data latches, and determining one of the data latches to output after receiving the lowest bit of the address information. According to the reading method, the sensing time of the sensing circuit can be one clock period more than that of a general reading mode. The embodiments of the present invention will be further described with reference to the accompanying drawings.
Fig. 2 is a schematic diagram showing a structure of a read circuit of a ferroelectric memory according to an embodiment of the present invention. As shown in fig. 2, a reading circuit of a ferroelectric memory includes a data sensing unit 201, a data selecting unit 202, and a data transmitting unit 203. The data sensing unit 201 includes two sets of data sensing circuits 2111 and 2121 and corresponding first and second data latches 2112 and 2122 for reading and latching data in the banks 0 and 1; the data selecting unit 202 is configured to select data in the first data latch 2121 and the second data latch 2122 for outputting according to a last bit of address information; and the data transmission unit 203 is configured to convert the signal output by the data selection unit into a serial signal and output the serial signal.
Fig. 3 illustrates a schematic structure of a data sensing unit according to an embodiment of the present invention. As shown in fig. 3, the data sensing unit 201 includes:
a first data sensing circuit 2111 for reading the bit line voltage bl0<7:0> in the "bank 0", and amplifying the potential difference between the bl0<7:0> and the reference line by a sense amplifier to obtain readable data sa0<7:0>;
a first data latch 2112 connected to an output terminal of the sense amplifier of the first data sensing circuit 2111 to latch the data sa0<7:0> amplified by the sense amplifier and output it under the control of a latch signal latch_sa;
a second data sensing circuit 2121 for reading the bit line voltages bl1<7:0> in the "bank 1", and amplifying the potential difference between the bl1<7:0> and the reference line by a sense amplifier to obtain readable data sa1<7:0>; and
a second data latch 2122 connected to the output of the sense amplifier of the second data sensing circuit 2121 for latching the data sa1<7:0> amplified by the sense amplifier and outputting it under the control of latch signal latch_sa.
In one embodiment of the present invention, the data selecting unit 202 includes a 2-out-of-1 data selector, wherein two input terminals in0, in1 of the data selector are respectively connected to the output terminals salat0<7:0> and salat1<7:0> of the first data latch 2112 and the second data latch 2122, and the control terminal select thereof can receive the last bit of the address information and output a corresponding path of data in salat0<7:0> and salat1<7:0> according to the value of the last bit of the address information.
Fig. 4 shows a schematic diagram of the structure of a data transmission unit according to an embodiment of the present invention. As shown in fig. 4, the data transmission unit 203 includes a parallel-input serial-output PISO unit 231 and a D flip-flop 232, wherein the PISO unit 231 is configured to receive an output salat <7:0> of the data selection unit 202 and convert the output salat into serial input data data_in under the control of a clock signal, and the D flip-flop 232 converts the serial input data data_in into an output signal data_out under the control of a trigger signal and an inverted clock signal.
In one embodiment of the present invention, the data transmission unit 203 is a parallel input serial output circuit, which includes:
and the counter circuit unit is used for counting according to an input clock signal and generating different counting signals according to different clock frequencies, wherein the input clock signal is a periodic pulse signal with fixed frequency. In this embodiment, to correspond to the output salat <7:0> of the data selection unit 202, the counter circuit unit generates three count signals <2:0>, wherein the first count signal <0> is a count signal counting one clock cycle frequency, the second count signal <1> is a count signal counting two clock cycles frequency, and the third count signal <2> is a count signal counting four clock cycles frequency. Specifically, the first count signal <0> is a pulse signal in which a high-low inversion occurs at the rising edge of the clock pulse signal of each cycle, the second count signal <1> is a pulse signal in which a high-low inversion occurs every two clock cycles, and the third count signal <2> is a pulse signal in which a high-low inversion occurs every four clock cycles. Such that the first count signal <0>, the second count signal <1> and the third count signal <2> are all low during the time period T1, such that the low state of the three count signals can be represented as a binary code of 000; in the time period T2, the first count signal <0> is at a high level, the second count signal <1> and the third count signal <2> are both at a low level, so that the level states of the three count signals can be represented as a binary code of 001, and so on, in the time period T3, the first count signal <0> is at a low level, the second count signal <1> is at a high level, and the third count signal <2> is at a low level, so that the level states of the three count signals can be represented as a binary code of 010; in the time period T4, the first count signal <0> is high, the second count signal <1> is high, the third count signal <2> is low, so that the level states of the three count signals can be represented as a binary code of 011, in the time period T5, the first count signal <0> is low, the second count signal <1> is low, the third count signal <2> is high, so that the level states of the three count signals can be represented as a binary code of 100, in the time period T6, the first count signal <0> is high, the second count signal <1> is low, the third count signal <2> is high, so that the level states of the three count signals can be represented as a binary code of 101, in the time period T7, the first count signal <0> is low, the second count signal <1> is high, the third count signal <2> is high, so that the level states of the three count signals can be represented as a binary code of 110, in the time period T8, the third count signal <1> is high, and the third count signal <1> is high. The cycle is repeated in this way. The specific circuit inside the counter circuit unit can be realized by adopting three D triggers connected in series, or can be realized in other modes;
and the decoder circuit unit is used for receiving the three counting signals <2:0> generated by the counter unit, compiling the counting signals and outputting 8-bit selection signals <7:0>. In one embodiment of the present invention, the decoder circuit unit includes three inverter circuits and eight and gate circuits. Wherein the input end of the first inverter is connected with a first counting signal <0> output by the counter circuit, and the output end of the first inverter outputs an inverted counting signal <0>. The input end of the second inverter is connected with a second counting signal <1> output by the counter circuit, and the output end of the second inverter outputs an inverted counting signal <1>. The input end of the third inverter is connected with a third counting signal <2> output by the counter circuit, and the output end of the third inverter outputs an inverted counting signal <2>. Wherein the inverse counting signal <0>, the inverse counting signal <1> and the inverse counting signal <2> are connected with three input ends of the first AND gate circuit, and the output end of the first AND gate circuit outputs the selection signal <0>. Because of the AND gate circuit, the output terminal is high only when all three input terminals of the AND gate circuit are high. The three input ends of the second AND gate circuit are respectively connected with the inverse counting signal <2>, the inverse counting signal <1> and the counting signal <0>, and the output end of the second AND gate circuit outputs the selection signal <1>. The three input ends of the third AND gate circuit are respectively connected with the inverse counting signal <2>, the counting signal <1> and the inverse counting signal <0>, and the output end of the third AND gate circuit outputs the selection signal <2>. The three input ends of the fourth AND gate circuit are respectively connected with the inverse counting signal <2>, the counting signal <1> and the counting signal <0>, and the output end of the fourth AND gate circuit outputs the selection signal <3>. The three input ends of the fifth AND gate circuit are respectively connected with the count signal <2>, the inverse count signal <1> and the inverse count signal <0>, and the output end of the fifth AND gate circuit outputs the selection signal <4>. The three input terminals of the sixth AND gate circuit are respectively connected with the count signal <2>, the inverse count signal <1> and the count signal <0>, and the output terminal of the sixth AND gate circuit outputs the selection signal <5>. The three input ends of the seventh AND gate circuit are respectively connected with the count signal <2>, the count signal <1> and the inverse count signal <0>, and the output end of the seventh AND gate circuit outputs the selection signal <6>. The three input ends of the eighth AND gate circuit are respectively connected with the counting signal <2>, the counting signal <1> and the counting signal <0>, and the output end of the eighth AND gate circuit outputs the selection signal <7>. Then, in the first time period T1, the first count signal <0> is low, the second count signal <1> is low, the third count signal <2> is low, the corresponding first inverse count signal <0> is high, the second inverse count signal <1> is high, and the third inverse count signal <2> is high, so that in the first time period T1, all the three input terminals of the first and gate circuit of the decoder circuit are high, and thus the output selection signal <0> is high. The input ends of other AND gates at least comprise one low level signal, so that the output ends of other AND gates are all low level. In the second time period T2, the first count signal <0> is high, the second count signal <1> is low, the third count signal <2> is low, the corresponding first inverse count signal <0> is low, the second inverse count signal <1> is high, and the third inverse count signal <2> is high, so that the first inverse count signals <0> at the three inputs of the first and gate circuit are low during the second time period T2, and the output selection signal <0> of the first and gate circuit is low. The first count signal <0> is high, the second inverse count signal <1> is high, and the third inverse count signal <2> is high at the three input ends of the second AND gate, so the selection signal <1> output by the output end of the second AND gate is high. The input ends of other AND gates at least comprise one low level signal, so that the output ends of other AND gates are all low level. And so on, in the third time period T3, only the selection signal <2> output from the output terminal of the third and gate is at high level, and the output terminals of the other and gates are all at low level. In the fourth period T4, only the selection signal <3> output from the output terminal of the fourth and gate is at high level, and the other and gate outputs are all at low level. In the fifth time period T5, only the selection signal <4> output from the output terminal of the fifth and gate is at the high level, and the other and gate outputs are all at the low level. In the sixth time period T6, only the selection signal <5> output from the output terminal of the sixth and gate is at the high level, and the other output terminals of the and gate are all at the low level. In the seventh time period T7, only the selection signal <6> output from the output terminal of the seventh and gate is at the high level, and the other and gate outputs are all at the low level. In the eighth time period T8, only the selection signal <7> output from the output terminal of the eighth and gate circuit is at high level, and the output terminals of the other and gate circuits are all at low level;
the multiplexer circuit unit receives the output salat <7:0> of the data selection unit 202, controls the selection switch according to the 8-bit selection signal <7:0>, and converts the output salat <7:0> of the data selection unit 202 into a serial input signal data_in which only one bit of data is output at the same time. In one embodiment of the present invention, the multiplexer in the multiplexer power unit includes 8 selection switch circuit units, taking the selection switch circuit unit where the eighth selection signal <7> and the eighth parallel input signal <7> are located as an example, the selection switch circuit unit includes a transmission gate circuit composed of two Nmos transistors and Pmos transistors that are relatively arranged in parallel, wherein the gates of the Nmos transistors are connected with the selection signal <7>, controlled by the selection signal <7>, the selection signal <7> is connected with the gates of the Pmos transistors through an inverter, and the gates of the Pmos transistors are controlled by the inverted selection signal <7>. The input of the transmission gate formed by two relatively parallel-arranged Nmos and Pmos transistors is connected to the eighth parallel input signal <7>, and the output of the transmission gate formed by two relatively parallel-arranged Nmos and Pmos transistors is connected to a common serial input signal line. Also, the first to seventh selection switch circuits each include a transmission gate circuit composed of two Nmos transistors and Pmos transistors arranged in opposite parallel. The first to seventh parallel input signals <6:0> are respectively input to the input ends of the transmission gates of the first to seventh selection switch circuit units, the output ends of the transmission gates of the first to seventh selection switch circuits are connected to a common serial input signal line, the gates of the Nmos transistors of the transmission gates of the first to seventh selection switch circuits are controlled by the corresponding first to seventh selection signals <6:0>, and the gates of the Pmos transistors of the transmission gates of the first to seventh selection switch circuits are controlled by the corresponding inverted first to seventh selection signals <6:0 >; and
and the D trigger is connected to the output end of the multiplexer circuit unit and outputs a serial output signal data_out under the control of a trigger signal and an inverted clock signal, wherein the output end of the multiplexer circuit unit refers to a serial input signal line commonly connected with the output ends of the selection switch circuit units, and the inverted clock signal is formed after the clock signal of the counter passes through the inverter. The D flip-flop operates on the rising edge of the pulse of the inverted clock signal to convert the serial input signal into the output signal.
Since in the embodiment of the present invention, the reading of the data and the receiving of the address are performed synchronously, in order to ensure that the corresponding data can be output correctly at last, the data transmission unit should output correct data after the following two operations are completed:
1. the data reading is completed, namely, the data in the 'bank 0' and the 'bank 1' are latched into the first data latch or the second data latch;
2. the address information to be read is confirmed, i.e. the last address information is received.
In one embodiment of the present invention, the completion of the two operations is identified by a first trigger pulse1 and a second trigger pulse2, respectively. Fig. 5 shows a timing diagram of read data output of a ferroelectric memory according to one embodiment of the present invention. As shown in fig. 5, after receiving the first trigger pulse1 or the second trigger pulse2, the D flip-flop 232 performs data output under the control of the inverted clock signal, that is, the trigger signal of the D flip-flop 232 includes the first trigger pulse1 and the second trigger pulse2, that is, the D flip-flop 232 is triggered twice and outputs two output signals, wherein the first output signal is a bit of invalid data, and the second output signal is complete correct data, because:
if the data latch is completed, the last bit of the address information is not received temporarily, that is, only the first trigger pulse1 is received, and the second trigger pulse2 is not received, then it cannot be determined whether the data in "bank 0" or "bank 1" needs to be selected, so that at this time, the signal to be output is a group of mixed data, which is invalid data, and the D trigger 232 is triggered by the pulse1, and outputs the most significant MSB of the mixed data; and
if the last bit of the address information is received, the data latch is not completed, that is, only the first trigger pulse2 is received, and the second trigger pulse1 is not received, then although it is determined that the data in "bank 0" or "bank 1" needs to be selected, the data in the latch is incomplete, so that the signal to be output is a group of incomplete error data, and is invalid data, and the D trigger 232 is triggered by the pulse2 and outputs the most significant bit of the error data.
Fig. 6 shows a timing diagram of trigger signal generation according to an embodiment of the present invention. As shown in fig. 6, the first trigger pulse1 is generated according to the latch signal latch_sa of the data sensing unit, when the data latch is completed, the latch signal latch_sa generates an inverted pulse, and the rising edge of the end of the inverted pulse triggers the first trigger pulse1 to identify that the data latch is completed; and the second trigger pulse2 is generated according to the receiving completion signal of the last bit of the address information, and after receiving the receiving completion signal Lastaddrin from 'input' of the last bit of the address information, first waits for a pulse Time for switch to ensure that the data selecting unit 202 has been triggered and completes the operation, and then generates the second trigger pulse2 to identify that the final data has been selected to be completed.
In one embodiment of the present invention, as shown in fig. 4, the first trigger pulse1 is generated by a first trigger circuit including a first rising edge trigger, which is inputted as a data latch completion signal, i.e., a reverse pulse generated by the latch signal latch_sa when data latching is completed.
In one embodiment of the present invention, as shown in fig. 4, the second trigger pulse1 is generated by the second trigger circuit when the last bit address information is received, and the second trigger circuit includes:
an inverter whose input is a Time for switch signal; and
a second rising edge trigger connected to the output of the inverter.
Based on the reading circuit, reading the ferroelectric memory specified address data includes:
after receiving the first 7 bits of address information, data in two addresses which are possibly corresponding to the first and second data latches are respectively latched into the first and second data latches:
if the last bit of the address information is received when the latching is completed, determining the address information according to the last bit of the received address information, and outputting the data latched in the first data latch or the second data latch as read data according to the address information, wherein when the latching is not completed, the read circuit outputs one invalid data when the last bit of the address information is received, and the invalid data is the most significant bit MSB of the data in the latch corresponding to the address information; and
and outputting one invalid data if the last bit of the address information is not received temporarily when the latching is completed, determining the address information according to the last bit of the received address information after the last bit of the address information is received, and outputting the data latched in the first data latch or the second data latch as read data according to the address information, wherein the invalid data is the most significant bit MSB of mixed data formed by the data in the first data latch and the second data latch. In one embodiment of the present invention, the outputting of the read data includes:
selecting, by the data selector, data latched in the first data latch or the second data latch according to the address information;
the data is converted into serial data after passing through a data transmission circuit; and
after receiving the trigger signal, the serial data is output bit by bit.
The invention also provides a ferroelectric memory comprising a read circuit as described above.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (9)
1. A read circuit of a ferroelectric memory, comprising:
the data sensing unit comprises two groups of data sensing circuits and corresponding first data latches and second data latches, wherein the two groups of data sensing circuits are respectively used for acquiring data in two different addresses, only the lowest bits of the two different addresses are different, and the two groups of data sensing circuits are configured to latch the data in the two corresponding addresses into the first data latches and the second data latches after 7 bits of address information are received;
a data selecting unit including a data selector having input terminals connected to output terminals of the first and second data latches, respectively, and a control terminal receiving a last bit of address information, the data selecting unit being configured to determine address information according to the last bit of the address information and output data latched in the first or second data latch as read data according to the address information when latching is completed and the last bit of the address information has been received;
and a data transmission unit configured to convert the parallel signal outputted from the data selector into a serial signal and output the serial signal.
2. The reading circuit of claim 1, wherein the data transmission unit comprises:
a counter circuit unit configured to be capable of counting according to an input clock signal, generating a count signal;
a decoder circuit unit configured to be able to receive the count signal generated by the counter circuit unit and generate a selection signal according to the count signal;
a multiplexer circuit unit configured to be able to receive output data of the data selector and control a selection switch according to the selection signal, converting the output data into a serial input signal; and
and a D flip-flop connected to an output terminal of the multiplexer circuit unit and configured to be able to output the serial signal data under control of a trigger signal and an inverted clock signal.
3. The read circuit of claim 2, wherein the trigger signal comprises:
the first trigger pulse is generated by the first trigger circuit when the data sensing unit completes data latching; and
the second trigger pulse is generated by the second trigger circuit when the last bit address information is received.
4. The read circuit of claim 3 wherein the first trigger circuit comprises a first rising edge flip-flop that inputs a data latch complete signal.
5. The read circuit of claim 3, wherein the second trigger circuit comprises:
an inverter which inputs a last-bit reception completion signal which is address information; and
a second rising edge trigger connected to the output of the inverter.
6. A reading method of a ferroelectric memory, characterized in that it is applied to a reading circuit according to any one of claims 1 to 5, and comprises the steps of:
after the first 7 bits of address information are received, data in two corresponding addresses are respectively latched into a first data latch and a second data latch:
if the last bit of the address information is received after the latching is completed, determining the address information according to the last bit of the received address information, and outputting the data latched in the first data latch or the second data latch as read data according to the address information; and
outputting one-bit invalid data if the last bit of the address information is not received temporarily when the latching is completed, determining the address information according to the last bit of the received address information after the last bit of the address information is received, and outputting the data latched in the first data latch or the second data latch as read data according to the address information.
7. The reading method of claim 6, wherein the outputting of the read data comprises:
selecting, by the data selector, data latched in the first data latch or the second data latch;
converting the data into serial data via a data transmission circuit; and
after receiving the trigger signal, outputting the serial data bit by bit.
8. The reading method of claim 6, further comprising:
and outputting one-bit invalid data if the data latch is not completed when the last bit of the address information is received.
9. A ferroelectric memory comprising a read circuit as claimed in any one of claims 1 to 5.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01133289A (en) * | 1987-11-18 | 1989-05-25 | Toshiba Corp | Non-volatile semiconductor memory |
| CN205881465U (en) * | 2016-07-25 | 2017-01-11 | 西安紫光国芯半导体有限公司 | Dynamic RAM)'s fast decoder |
| CN112290922A (en) * | 2020-11-09 | 2021-01-29 | 无锡拍字节科技有限公司 | Parallel input and serial output circuit and memory using the same |
| US10971202B1 (en) * | 2020-04-15 | 2021-04-06 | Sandisk Technologies Llc | Low latency data transfer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100527569B1 (en) * | 2003-05-09 | 2005-11-09 | 주식회사 하이닉스반도체 | Non-volatile ferroelectric memory and controlling device thereof |
| US10997097B2 (en) * | 2019-06-04 | 2021-05-04 | Western Digital Technologies, Inc. | Enabling high speed command address interface for random read |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01133289A (en) * | 1987-11-18 | 1989-05-25 | Toshiba Corp | Non-volatile semiconductor memory |
| CN205881465U (en) * | 2016-07-25 | 2017-01-11 | 西安紫光国芯半导体有限公司 | Dynamic RAM)'s fast decoder |
| US10971202B1 (en) * | 2020-04-15 | 2021-04-06 | Sandisk Technologies Llc | Low latency data transfer |
| CN112290922A (en) * | 2020-11-09 | 2021-01-29 | 无锡拍字节科技有限公司 | Parallel input and serial output circuit and memory using the same |
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