CN115440270B - Data transmission circuit, data processing circuit and memory - Google Patents
Data transmission circuit, data processing circuit and memory Download PDFInfo
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- CN115440270B CN115440270B CN202110609883.6A CN202110609883A CN115440270B CN 115440270 B CN115440270 B CN 115440270B CN 202110609883 A CN202110609883 A CN 202110609883A CN 115440270 B CN115440270 B CN 115440270B
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 49
- 238000012545 processing Methods 0.000 title claims abstract description 31
- 230000015654 memory Effects 0.000 title claims abstract description 22
- 238000012795 verification Methods 0.000 claims abstract description 112
- 238000003860 storage Methods 0.000 claims abstract description 28
- 238000013500 data storage Methods 0.000 claims abstract description 17
- 238000012546 transfer Methods 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 19
- 239000004065 semiconductor Substances 0.000 description 14
- 241001504505 Troglodytes troglodytes Species 0.000 description 11
- 230000004044 response Effects 0.000 description 8
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- 230000006870 function Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
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- 230000001360 synchronised effect Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
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Abstract
The embodiment of the application relates to a data transmission circuit, a data processing circuit and a memory, wherein the data transmission circuit comprises: the data writing circuit is used for transmitting data to be stored to a global data line group, the global data line group comprises a first global data line and a second global data line, the first global data line and the second global data line which are arranged in pairs transmit data which are mutually opposite in phase, and the data to be stored is transmitted to the data storage unit for storage through the global data line group; the verification write circuit is used for transmitting verification data to the global data line group connected with the verification storage unit so as to store the verification data, and the verification data corresponds to the data to be stored; the data write circuit and the check write circuit are used for synchronously transmitting data to the corresponding global data line group, and the driving capability of the check write circuit is stronger than that of the data write circuit.
Description
Technical Field
The embodiment of the application relates to the technical field of memories, in particular to a data transmission circuit, a data processing circuit and a memory.
Background
A semiconductor memory is a memory which is accessed using a semiconductor circuit, and among them, a dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used in various fields with its fast memory speed and high integration. In order to obtain higher data read-write reliability, a verification-related circuit needs to be arranged in the semiconductor memory to verify whether the read data is accurate, but the introduction of the verification-related circuit may cause the read-write speed of the memory to be slow, and the performance of the semiconductor memory is affected.
Disclosure of Invention
The embodiment of the application provides a data transmission circuit, a data processing circuit and a memory, which can optimize the read-write speed of the memory.
A data transmission circuit, comprising:
The data writing circuit is used for transmitting data to be stored to a global data line group, the global data line group comprises a first global data line and a second global data line, the first global data line and the second global data line which are arranged in pairs transmit data which are mutually opposite in phase, and the data to be stored is transmitted to the data storage unit for storage through the global data line group;
the verification write circuit is used for transmitting verification data to the global data line group connected with the verification storage unit so as to store the verification data, and the verification data corresponds to the data to be stored;
the data write circuit and the check write circuit are used for synchronously transmitting data to the corresponding global data line group, and the driving capability of the check write circuit is stronger than that of the data write circuit.
In one embodiment, the circuit structures of the data write circuit and the verification write circuit are both first circuits, but the electrical parameters of the corresponding devices in the data write circuit and the verification write circuit are not completely the same, so that the driving capability of the verification write circuit is stronger than that of the data write circuit.
In one embodiment, the first circuit includes:
The first driving module is connected with the first global data line and is used for responding to a write enabling signal, generating and transmitting a first write signal to the first global data line according to a data signal to be written, wherein the level state of the first write signal is the same as that of the data to be written;
The second driving module is connected with the second global data line and is used for responding to a write enabling signal, generating and transmitting a second write signal to the second global data line according to a data signal to be written, and the level state of the second write signal is opposite to that of the data to be written;
the driving capability of the first driving module of the verification write circuit is stronger than that of the first driving module of the data write circuit, and the driving capability of the second driving module of the verification write circuit is stronger than that of the second driving module of the data write circuit.
In one embodiment, the first driving module includes:
The control end of the first pull-up transistor is used for receiving the inverted data signal to be written, and the first end of the first pull-up transistor is connected with a power supply voltage end;
The control end of the first pull-down transistor is used for receiving the inverted data signal to be written, the first end of the first pull-down transistor is connected with the grounding end, and the second end of the first pull-down transistor is connected with the second end of the first pull-up transistor;
the channel width-to-length ratio of the first pull-up transistor in the verification write circuit is larger than that of the first pull-up transistor in the data write circuit, and the channel width-to-length ratio of the first pull-down transistor in the verification write circuit is larger than that of the first pull-down transistor in the data write circuit.
In one embodiment, the threshold voltage of the first pull-up transistor in the verify write circuit is less than the threshold voltage of the first pull-up transistor in the data write circuit.
In one embodiment, the threshold voltage of the first pull-down transistor in the verify write circuit is less than the threshold voltage of the first pull-down transistor in the data write circuit.
In one embodiment, the data transfer circuit is configured with a precharge phase and a data write phase, and the first drive module further comprises:
a logic operation unit connected with the first pull-up transistor and the first pull-down transistor respectively, and used for responding to a write enable signal in the data writing stage to generate the inverted data signal to be written;
And the first NOT gate is connected with the logic operation unit and is used for controlling the logic operation unit to output a low-level signal in the precharge stage.
In one embodiment, the logic operation unit includes:
The two input ends of the first AND gate are respectively used for receiving the data signals to be written and the write enabling signals in a one-to-one correspondence manner;
And one input end of the first NOR gate is connected with the output end of the first AND gate, the other input end of the first NOR gate is used for receiving an inverted pre-charge signal, the pre-charge signal is used for switching the data transmission circuit to a pre-charge stage or a data writing stage, and the output end of the first NOR gate is connected with the control end of the first pull-up transistor.
In one embodiment, the output terminal of the first nor gate is further connected to the control terminal of the first pull-down transistor.
In one embodiment, the logic operation unit further includes:
the two input ends of the first NAND gate are respectively used for receiving the precharge signal and the write enable signal in a one-to-one correspondence;
And one input end of the second NOR gate is connected with the output end of the first NAND gate, the other input end of the second NOR gate is used for receiving the data signal to be written, and the output end of the second NOR gate is connected with the control end of the first pull-down transistor.
In one embodiment, the data write circuit and the verify write circuit respectively transmit data to corresponding global data line groups in response to the same write enable signal.
In one embodiment, the method further comprises:
the data reading circuit is used for acquiring data to be read from the global data line group connected with the data storage unit so as to read the data to be read;
The verification reading circuit is used for acquiring verification data from the global data line group connected with the verification storage unit so as to read the stored verification data, and the stored verification data corresponds to the data to be read;
wherein the driving capability of the verification reading circuit is equal to the driving capability of the data reading circuit.
In one embodiment, the circuit structures of the data reading circuit and the verification reading circuit are both second circuits, and the electrical parameters of the corresponding devices in the data reading circuit and the verification reading circuit are the same.
In one embodiment, the first global data line is further used for transmitting a first read signal, the second global data line is further used for transmitting a second read signal, the level state of the first read signal is the same as the data to be read, the level state of the second read signal is opposite to the data to be read, and the second circuit includes:
the signal processing module is respectively connected with the first global data line and the second global data line and is used for responding to the read enabling signal and generating a read driving signal according to the first read signal and the second read signal;
and the reading driving module is connected with the signal processing module and is used for outputting the read data to be read according to the reading driving signal.
A data processing circuit, comprising:
A data transmission circuit as described above;
And the verification generating circuit is connected with the verification writing circuit and is used for acquiring the data to be stored, generating corresponding verification data according to the data to be stored and transmitting the verification data to the verification writing circuit.
A memory, comprising: a data storage unit, a check storage unit and a data processing circuit as described above.
The data transmission circuit, the data processing circuit and the memory, the data transmission circuit includes: the data writing circuit is used for transmitting data to be stored to a global data line group, the global data line group comprises a first global data line and a second global data line, the first global data line and the second global data line which are arranged in pairs transmit data which are mutually opposite in phase, and the data to be stored is transmitted to the data storage unit for storage through the global data line group; the verification write circuit is used for transmitting verification data to the global data line group connected with the verification storage unit so as to store the verification data, and the verification data corresponds to the data to be stored; the data write circuit and the check write circuit are used for synchronously transmitting data to the corresponding global data line group, and the driving capability of the check write circuit is stronger than that of the data write circuit. By setting the driving capability of the verification write circuit to be stronger than that of the data write circuit, the transmission speed of verification data can be made to be greater than that of data to be stored, so that the time for generating the verification data in the embodiment of the application is compensated, and the data writing speed of the memory is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is one of the block diagrams of a data processing circuit according to an embodiment;
FIG. 2 is one of the block diagrams of the first circuit of an embodiment;
FIG. 3 is a second block diagram of a first circuit according to an embodiment;
FIG. 4 is a third block diagram of a first circuit according to an embodiment;
FIG. 5 is a fourth block diagram of a first circuit of an embodiment;
FIG. 6 is a fifth block diagram of a first circuit of an embodiment;
FIG. 7 is a timing diagram of writing data to be stored and verification data according to an embodiment;
FIG. 8 is a second block diagram of a data processing circuit according to an embodiment;
FIG. 9 is one of the block diagrams of the second circuit of an embodiment;
FIG. 10 is a second circuit diagram of a second circuit of an embodiment.
Description of element numbers:
And a data transmission circuit: 10; and a data writing circuit: 100; and a verification write circuit: 200; a first circuit: 300; a first driving module: 310; a logic operation unit: 311; a first AND gate: 3111; a first nor gate: 3112; a first NAND gate: 3113; second nor gate: 3114; a first NOT gate: 3121; and a second driving module: 320. A second NOT gate: 3201; and a second AND gate: 3202; third nor gate: 3203; fourth nor gate: 3204; third NOT gate: 3301; a data storage unit: 400; and (3) checking a storage unit: 500; a data reading circuit: 600; and a verification reading circuit: 700; a second circuit: 800; and a signal processing module: 810, a step of performing step 810; and a reading driving module: 820, a base; a precharge module: 830; and a check generation circuit: 20.
Detailed Description
In order to facilitate an understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. The embodiments of the application may, however, be embodied in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the application belong. The terminology used in the description of the embodiments of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, the first global data line YIO may be referred to as the second global data line YIO _n, and similarly, the second global data line YIO _n may be referred to as the first global data line YIO without departing from the scope of the application. Both the first global data line YIO and the second global data line YIO _n are global data lines, but they are not the same global data line.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. In the description of the present application, the meaning of "several" means at least one, such as one, two, etc., unless specifically defined otherwise.
Fig. 1 is one of the block diagrams of the data processing circuit of an embodiment, referring to fig. 1, in this embodiment, the data processing circuit includes a data transmission circuit 10 and a check generation circuit 20.
The check generation circuit 20 is configured to receive data to be stored, and generate check data according to the data to be stored. The check data is generated and stored in the data writing stage to determine whether an error occurs in the data reading stage, that is, whether an error occurs in the data reading and writing process of the data by determining whether the data read in the data storage unit 400 is identical to the data to be stored. The verification generating circuit 20 can be used for verifying data information of a plurality of storage arrays, so that the number of the verification generating circuits 20 is optimized, and a small-volume semiconductor memory is further provided. It is to be understood that the check generating circuit 20 may have any circuit configuration having a check data generating function, and the present embodiment is not limited to a specific type of the check generating circuit 20, and may have at least one of a parity check function, an error correction check function, and the like.
The memory array includes a plurality of data memory cells 400 for storing data and a plurality of check memory cells 500 for implementing a memory function of the semiconductor memory. The data storage unit 400 is used for storing data to be stored, which is externally input to the memory, and the verification storage unit 500 is used for storing verification data generated according to the data to be stored. Specifically, the memory cell further comprises a storage capacitor and a transistor, wherein the control end of the transistor is connected with the word line, the first end of the transistor is connected with the storage capacitor, and the second end of the transistor is connected with the bit line. When the word line control transistor is turned on, the storage capacitor is turned on with the bit line, so that reading and writing of data information are realized, namely, when the data information is read, the storage capacitor transmits the stored data information to the bit line; when writing data information, the bit line transmits the data information to be written to the storage capacitor.
The data transfer circuit 10 includes a data write circuit 100 and a verify write circuit 200. The data transmission circuit 10 is respectively connected to the check generating circuit 20 and the storage array, and is configured to transmit the data to be stored to the data storage unit 400 and transmit the check data to the check storage unit 500. Specifically, the data writing circuit 100 is configured to transmit data to be stored to a global data line group, where the global data line group includes a first global data line YIO and a second global data line YIO _n, and the first global data line YIO and the second global data line YIO _n that are arranged in pairs transmit data that are mutually inverted, and the data to be stored is transmitted to the data storage unit 400 for storage through the global data line group. The check writing circuit 200 is configured to transmit check data to the global data line group connected to the check storage unit 500, so as to store the check data, where the check data corresponds to the data to be stored.
The data writing circuit 100 and the check writing circuit 200 are used for synchronously transmitting data to the corresponding global data line group, and it should be clear that the synchronous transmission in this embodiment is not limited to the fact that two data must be written at the same time, and synchronous transmission means that the check data and the data to be stored with corresponding relations complete transmission in the same data writing period. For example, the writing process of the check data and the data to be stored may be performed in response to the same enable signal, so as to implement a synchronous transmission function, for example, the data writing circuit 100 and the check writing circuit 200 respectively transmit data to the corresponding global data line group in response to the same write enable signal WrEn, so that, on one hand, the number of signals required may be saved, and on the other hand, the writing synchronism of the data to be stored and the check data may be improved. In this embodiment, the driving capability of the verification write circuit 200 is stronger than the driving capability of the data write circuit 100, wherein the driving capability of the write circuit can be characterized by a write current, and therefore, the write current of the verification write circuit 200 of this embodiment is greater than the write current of the data write circuit 100.
The data to be stored can be directly written into the data storage unit 400 through the data writing circuit 100, and the verification data needs to be generated according to the data to be stored, so that the time for the verification data to reach the verification writing circuit 200 is necessarily later than the time for the data to be stored to reach the data writing circuit 100, and correspondingly, the time for the verification data to be written into the verification storage unit 500 is slightly later than the corresponding writing time of the data to be stored, thereby causing the problem of poor data writing synchronism and further increasing the writing speed. In this embodiment, by setting the verification write circuit 200 with strong driving capability, the duration of data writing by the verification write circuit 200 can be shortened, so that the time consumed in the process of generating verification data is effectively compensated, and the stored data writing speed is optimized.
In one embodiment, the circuit structures of the data write circuit 100 and the verification write circuit 200 are the first circuit 300, that is, it can be understood that the respective elements in the circuits of the data write circuit 100 and the verification write circuit 200 correspond to each other and have the same connection relationship. However, the electrical parameters of the corresponding devices in the data write circuit 100 and the verification write circuit 200 are not identical, so that the driving capability of the verification write circuit 200 is stronger than that of the data write circuit 100. The corresponding devices refer to two devices which are located at the same position in the two circuits and have the same connection relationship, and the types of the corresponding devices can be, but are not limited to, MOS transistors, triodes, diodes and the like, and it is understood that the devices in the embodiments of the present application are not limited to a single element, that is, the devices formed by connecting a plurality of elements together are also included. In this embodiment, by setting the data write circuit 100 and the verification write circuit 200 with the same circuit structure, the parameter optimization difficulty of the semiconductor memory can be reduced, so that the difficulty in the mask design process and the memory manufacturing process is reduced, and the preparation yield of the semiconductor memory is further improved.
Fig. 2 is one of the block diagrams of the first circuit 300 according to an embodiment, referring to fig. 2, in this embodiment, the first circuit 300 includes a first driving module 310 and a second driving module 320. It should be noted that, the Data signal Data to be written shown in the drawings in the embodiments of the present application refers to Data to be stored that needs to be actually stored for the Data writing circuit 100, and refers to verification Data generated according to the Data to be stored for the verification writing circuit 200.
The first driving module 310 is connected to the first global Data line YIO, and is configured to generate and transmit a first write signal to the first global Data line YIO according to a Data signal Data to be written in response to the write enable signal WrEn, where a level state of the first write signal is the same as the Data to be written. The second driving module 320 is connected to the second global Data line YIO _n, and is configured to generate and transmit a second write signal to the second global Data line YIO _n according to the Data signal Data to be written in response to the write enable signal WrEn, where a level state of the second write signal is opposite to the Data to be written. The first global data line YIO and the second global data line YIO _n are used for transmitting the same data to be written, but the level states of the first global data line YIO and the second global data line YIO _n are opposite, and the reliability of the data in the transmission process can be effectively improved through a double-line signal transmission mode, so that the accurate data to be written is written into the corresponding data storage unit 400, and the accurate check data is synchronously written into the corresponding check storage unit 500.
Wherein, the driving capability of the first driving module 310 of the verification write circuit 200 is stronger than the driving capability of the first driving module 310 of the data write circuit 100, and the driving capability of the second driving module 320 of the verification write circuit 200 is stronger than the driving capability of the second driving module 320 of the data write circuit 100. In the present embodiment, the circuit structures of the verification write circuit 200 and the data write circuit 100 are the same, and thus, the first driving module 310 of the verification write circuit 200 and the first driving module 310 of the data write circuit 100 may be understood as corresponding devices, and similarly, the second driving module 320 of the verification write circuit 200 and the second driving module 320 of the data write circuit 100 may be understood as corresponding devices. By the arrangement of the first driving module 310 and the second driving module 320 in this embodiment, the data transmission speed of the first driving module 310 of the verification write circuit 200 can be faster than the data transmission speed of the first driving module 310 of the data write circuit 100, and the data transmission speed of the second driving module 320 of the verification write circuit 200 can be faster than the data transmission speed of the second driving module 320 of the data write circuit 100, so that the data transmission duration of the verification write circuit 200 is shortened as a whole, and the writing speed of the memory is optimized.
Fig. 3 is a second block diagram of a first circuit 300 according to an embodiment, referring to fig. 3, in the present embodiment, the first circuit 300 includes a transistor T0, a control terminal of the transistor T0 is used for receiving a precharge signal EQ, a first terminal of the transistor T0 is connected to the first global data line YIO, a second terminal of the transistor T0 is connected to the second global data line YIO _n, and the transistor T0 is used for precharging the first global data line YIO and the second global data line YIO _n under the control of the precharge signal EQ, so as to increase the data writing speed. The data transmission circuit 10 is configured with a precharge phase and a data writing phase, taking the transistor T0 as a PMOS transistor for example, in the precharge phase, the precharge signal EQ is at a low level, the transistor T0 is turned on, the first global data line YIO and the second global data line YIO _n are connected, and the voltages on the two data lines become equal through charge sharing, so as to precharge the first global data line YIO and the second global data line YIO _n; in the data writing stage, the precharge signal EQ is at a high level, the transistor T0 is turned off, the first global data line YIO and the second global data line YIO _n are disconnected, the first global data line YIO receives the signal output by the first driving module 310, and the second global data line YIO _n receives the signal output by the second driving module 320, thereby realizing the transmission of the data to be written.
The first driving module 310 includes a first pull-up transistor T1 and a first pull-down transistor T2, where the first pull-up transistor T1 and the first pull-down transistor T2 have different conduction types, one is turned on at a high level, and the other is turned on at a low level. Specifically, the first pull-up transistor T1 is turned on at a low level, the control terminal of the first pull-up transistor T1 is configured to receive the inverted Data signal Data to be written, and the first terminal of the first pull-up transistor T1 is connected to the supply voltage terminal. The first pull-down transistor T2 is turned on at a high level, a control terminal of the first pull-down transistor T2 is configured to receive the inverted Data signal Data to be written, a first terminal of the first pull-down transistor T2 is connected to a ground terminal, and a second terminal of the first pull-down transistor T2 is connected to a second terminal of the first pull-up transistor T1. Specifically, in the Data writing stage, the write enable signal WrEn is at a high level, and the first driving module 310 can implement Data writing according to the Data signal, for example, when the Data signal is at a high level, the signals received by the control terminal of the first pull-up transistor T1 and the control terminal of the second pull-up transistor T3 are both low level signals, the first pull-up transistor T1 is turned on, and the first pull-down transistor T2 is turned off, so that the first write signal is pulled up to a high level, so that the signal on the first global Data line YIO is the same as the band write Data signal.
The channel width-to-length ratio of the first pull-up transistor T1 in the verification write circuit 200 is greater than the channel width-to-length ratio of the first pull-up transistor T1 in the data write circuit 100, and the channel width-to-length ratio of the first pull-down transistor T2 in the verification write circuit 200 is greater than the channel width-to-length ratio of the first pull-down transistor T2 in the data write circuit 100. It will be appreciated that the larger the channel width to length ratio of the transistor, the larger the write current thereof, and accordingly the stronger the driving capability, therefore, the driving capability of the first pull-up transistor T1 of the verify write circuit 200 is stronger than the driving capability of the first pull-up transistor T1 of the data write circuit 100, and the driving capability of the first pull-down transistor T2 of the verify write circuit 200 is stronger than the driving capability of the first pull-down transistor T2 of the data write circuit 100, thereby improving the data transmission speed of the verify write circuit 200 and further improving the writing speed of the semiconductor memory.
In one embodiment, the threshold voltage of the first pull-up transistor T1 in the verify write circuit 200 is less than the threshold voltage of the first pull-up transistor T1 in the data write circuit 100. It will be appreciated that the larger the channel width to length ratio of the transistor, the larger the write current thereof, and accordingly the stronger the driving capability, therefore, the driving capability of the first pull-up transistor T1 of the verify write circuit 200 is stronger than the driving capability of the first pull-up transistor T1 of the data write circuit 100, and the data transfer speed of the verify write circuit 200 is faster than the data transfer speed of the data write circuit 100, thereby improving the writing speed of the semiconductor memory. Alternatively, the threshold voltages of the transistors may be changed by adjusting the doping concentrations, i.e., different doping concentrations are used to form the first pull-up transistor T1 of the verify write circuit 200 and the first pull-up transistor T1 of the data write circuit 100, respectively, to achieve different threshold voltages.
In one embodiment, the threshold voltage of the first pull-down transistor T2 in the verify write circuit 200 is less than the threshold voltage of the first pull-down transistor T2 in the data write circuit 100. Similarly to the above description, the larger the channel width to length ratio of the transistor, the larger the write current thereof, and accordingly the stronger the driving capability, and therefore the driving capability of the first pull-down transistor T2 of the verify write circuit 200 is stronger than the driving capability of the first pull-down transistor T2 of the data write circuit 100, the data transfer speed of the verify write circuit 200 is faster than the data transfer speed of the data write circuit 100, thereby improving the writing speed of the semiconductor memory. Alternatively, the threshold voltages of the transistors may be changed by adjusting the doping concentrations, that is, different doping concentrations are used to form the first pull-down transistor T2 of the verify write circuit 200 and the first pull-down transistor T2 of the data write circuit 100, respectively, to achieve different threshold voltages.
Fig. 4 is a third block diagram of the first circuit 300 according to an embodiment, referring to fig. 4, in this embodiment, the first driving module 310 further includes a logic operation unit 311 and a first not gate 3121. The logic operation unit 311 is respectively connected to the first pull-up transistor T1 and the first pull-down transistor T2, and is configured to generate the inverted Data signal Data to be written in response to the write enable signal WrEn during the Data writing stage. The first not gate 3121 is connected to the logic operation unit 311 for controlling the logic operation unit 311 to output a low level signal in the precharge phase. In this embodiment, the precharge signal EQ further acts on the first driving module 310, and when the precharge signal EQ is at a low level, the high-level inversion precharge signal EQ is transmitted to the logic operation unit 311 under the action of the first not gate 3121, so as to control the logic operation unit 311 to keep the level state of the output signal unchanged during the precharge phase, thereby improving the stability and reliability of the circuit.
With continued reference to fig. 4, the logic operation unit 311 includes a first and gate 3111 and a first nor gate 3112. The two input terminals of the first and gate 3111 are respectively configured to receive the Data signal Data to be written and the write enable signal WrEn in a one-to-one correspondence, and the write enable signal WrEn is at a high level during the Data writing stage, so that the signal output by the first and gate 3111 follows the Data signal input by the input terminal. One input terminal of the first nor gate 3112 is connected to the output terminal of the first and gate 3111, the other input terminal of the first nor gate 3112 is configured to receive an inverted precharge signal EQ for switching the data transfer circuit 10 to a precharge phase or a data write phase, and the output terminal of the first nor gate 3112 is connected to the control terminal of the first pull-up transistor T1. Further, the output end of the first nor gate 3112 may be connected to the control end of the first pull-down transistor T2, so that the first pull-up transistor T1 and the first pull-down transistor T2 are controlled simultaneously based on one signal, and the number of signal traces is saved. In the precharge phase, the precharge signal EQ is low, the signal output from the first nor gate 3121 is high, and if one input terminal of the first nor gate 3112 is high, the signal output from the first nor gate 3112 must be low, so that the first write signal received by the control terminals of the first pull-up transistor T1 and the first pull-down transistor T2 is kept unchanged. In the Data write phase, both precharge signal EQ and write enable signal WrEn are high, thereby making the signal on first global Data line YIO correspond to the Data signal.
Fig. 5 is a block diagram of a first circuit 300 according to an embodiment, referring to fig. 5, in this embodiment, the logic operation unit 311 further includes a first nand gate 3113 and a second nor gate 3114. The two input terminals of the first nand gate 3113 are respectively configured to receive the precharge signal EQ and the write enable signal WrEn in a one-to-one correspondence. One input end of the second nor gate 3114 is connected to the output end of the first nand gate 3113, the other input end of the second nor gate 3114 is used for receiving the Data signal Data to be written, and the output end of the second nor gate 3114 is connected to the control end of the first pull-down transistor T2. The first pull-up transistor T1 is controlled by the first nor gate 3112, and the control method is as in the previous embodiment, and will not be described herein. In the precharge phase, the precharge signal EQ is low, the signal output from the first nand gate 3113 is high, and if one input terminal of the second nor gate 3114 is high, the signal output from the same is necessarily low, so that the first write signal received by the control terminals of the first pull-up transistor T1 and the first pull-down transistor T2 is kept unchanged. In the Data write phase, both precharge signal EQ and write enable signal WrEn are high, thereby making the signal on first global Data line YIO correspond to the Data signal. In this embodiment, the control reliability of the first pull-up transistor T1 and the first pull-down transistor T2 can be effectively improved by controlling the first pull-up transistor T1 and the first pull-down transistor T2 in one-to-one correspondence with each other through two logic gates.
Fig. 6 is a fifth block diagram of the first circuit 300 according to an embodiment, referring to fig. 6, in this embodiment, the second driving circuit includes a second pull-up transistor T3 and a second pull-down transistor T4. The first pull-up transistor T1 is turned on at a low level, a control terminal of the first pull-up transistor T1 is configured to receive the inverted Data signal Data to be written, and a first terminal of the first pull-up transistor T1 is connected to a power supply voltage terminal. The first pull-down transistor T2 is turned on at a high level, a control terminal of the first pull-down transistor T2 is configured to receive the inverted Data signal Data to be written, a first terminal of the first pull-down transistor T2 is connected to a ground terminal, and a second terminal of the first pull-down transistor T2 is connected to a second terminal of the first pull-up transistor T1. The channel width-to-length ratio of the first pull-up transistor T1 in the verification write circuit 200 is greater than the channel width-to-length ratio of the first pull-up transistor T1 in the data write circuit 100, and the channel width-to-length ratio of the first pull-down transistor T2 in the verification write circuit 200 is greater than the channel width-to-length ratio of the first pull-down transistor T2 in the data write circuit 100.
In some embodiments, the threshold voltage of the first pull-up transistor T1 in the verify write circuit 200 is less than the threshold voltage of the first pull-up transistor T1 in the data write circuit 100. In other embodiments, the threshold voltage of the first pull-down transistor T2 in the verify write circuit 200 is less than the threshold voltage of the first pull-down transistor T2 in the data write circuit 100.
Further, the second driving module 320 further includes a second not gate 3201, a second and gate 3202, a third nor gate 3203, and a fourth nor gate 3204, wherein an input end of the second not gate 3201 is used for connecting a Data signal Data to be written, two input ends of the second and gate 3202 are respectively used for connecting an output end of the second not gate 3201 and a write enable signal WrEn in a one-to-one correspondence manner, two input ends of the third nor gate 3203 are respectively used for connecting an output end of the second and gate 3202 and an inverted precharge signal EQ in a one-to-one correspondence manner, an output end of the third nor gate 3203 is connected with a control end of the second pull-up transistor T3, two input ends of the fourth nor gate 3204 are respectively used for connecting an output end of the first nor gate 3113 and an inverted Data signal Data to be written in a one-to-one correspondence manner, and an output end of the fourth nor gate 3204 is connected with a control end of the second pull-down transistor T4. Fig. 7 is a timing chart of writing data to be stored and verification data according to an embodiment, in which the data writing circuit 100 and the verification writing circuit 200 both employ the first circuit 300 of the embodiment of fig. 6, and referring to fig. 7, based on the first circuit 300 of the embodiment of fig. 6, the duration tdp required for verification data writing is smaller than the duration td required for data writing to be stored, thereby improving the writing speed of the semiconductor memory.
Fig. 8 is a second block diagram of the data processing circuit according to an embodiment, referring to fig. 8, in this embodiment, the signal processing further includes a data reading circuit 600 and a verification reading circuit 700. The Data reading circuit 600 is configured to obtain Data to be read Data from the global Data line group connected to the Data storage unit 400, so as to read the Data to be read Data; the check reading circuit 700 is configured to obtain check Data from the global Data line group connected to the check storage unit 500, so as to read the stored check Data, where the stored check Data corresponds to the Data to be read. Wherein the driving capability of the verify-read circuit 700 is equal to the driving capability of the data-read circuit 600. In the Data reading stage, since the read Data can be verified based on the verification Data after the read operation of the Data to be read Data is completed, the reading speeds of the Data reading circuit 600 and the verification reading circuit 700 are equivalent, and the reading speed of the semiconductor memory is not affected, but in the embodiment, the design difficulty and the manufacturing difficulty of the reading circuit can be reduced by adopting the verification reading circuit 700 and the Data reading circuit 600 with the same driving capability, so that the manufacturing yield of the semiconductor memory is improved.
In one embodiment, the circuit structures of the data reading circuit 600 and the verification reading circuit 700 are the second circuit 800, and the electrical parameters of the corresponding devices in the data reading circuit 600 and the verification reading circuit 700 are the same. Specifically, fig. 9 is one of the block diagrams of the second circuit 800 according to an embodiment, referring to fig. 9, in this embodiment, the first global Data line YIO is further used for transmitting a first read signal, the second global Data line YIO _n is further used for transmitting a second read signal, the level state of the first read signal is the same as the Data to be read, the level state of the second read signal is opposite to the Data to be read, and the second circuit 800 includes a signal processing module 810 and a read driving module 820. The signal processing module 810 is respectively connected to the first global data line YIO and the second global data line YIO _n, and is configured to generate a read driving signal according to a first read signal and a second read signal in response to a read enable signal YIO _en. The read driving module 820 is connected to the signal processing module 810, and is configured to output the read Data to be read according to the read driving signal.
Fig. 10 is a second circuit diagram of a second circuit 800 according to an embodiment, referring to fig. 10, in the present embodiment, the signal processing module 810 includes transistors T5 to T11. The first end of the transistor T5 is connected to the first global data line YIO, the first end of the transistor T6 is connected to the second global data line YIO _n, the control end of the transistor T5 and the control end of the transistor T6 both receive the column strobe signal YIO _sel, and when the column strobe signal YIO _sel is at a low level, the transistor T5 and the transistor T6 are turned on, so that signals on the first global data line YIO and the second global data line YIO _n are synchronously transmitted to the corresponding signal receiving node a and signal receiving node B, respectively. The control terminal of the transistor T11 is for receiving the read enable signal YIO _en to control the data transmission circuit 10 to be in the data reading stage.
The transistors T7 to T10 together form a positive feedback circuit, so as to increase the response speed to the received signal, and realize rapid increase or decrease of the signal, so that the reading speed of the signal is improved, specifically, the control terminal of the transistor T7 and the control terminal of the transistor T9 are respectively connected with the control terminal of the transistor T6, the control terminal of the transistor T8 and the control terminal of the transistor T10 are respectively connected with the control terminal of the transistor T5, the first terminal of the transistor T7 and the first terminal of the transistor T8 are respectively connected with the power supply terminal, the second terminal of the transistor T7 is connected with the first terminal of the transistor T9, the second terminal of the transistor T8 is connected with the first terminal of the transistor T10, and the second terminal of the transistor T9 and the second terminal of the transistor T10 are respectively connected to the first terminal of the transistor T11. It will be appreciated that the positive feedback circuit in the embodiment of fig. 10 is for illustration only and is not intended to limit the scope of the present application, as other positive feedback circuits having the same function are within the scope of the present application.
The read driving module 820 is connected to a node between the transistor T7 and the transistor T9, thereby outputting a signal corresponding to the Data to be read. The read driving module 820 includes a third pull-up transistor T12 and a third pull-down transistor T13, a control terminal of the third pull-up transistor T12 and a control terminal of the third pull-down transistor T13 are respectively connected to a node between the transistor T7 and the transistor T9, a first terminal of the third pull-up transistor T12 is connected to a power supply terminal, a second terminal of the third pull-up transistor T12 is connected to a first terminal of the third pull-down transistor T13, and a second terminal of the third pull-down transistor T13 is grounded via the transistor T16.
With continued reference to fig. 10, in one embodiment, the data transmission circuit 10 further includes a precharge module 830, where the precharge module 830 is configured to precharge the signal receiving node a connected to the transistor T5 and the signal receiving node B connected to the transistor T6 before the data is read. The first end of the transistor T19 is connected to the power supply end, the second end of the transistor T19 is connected to the signal receiving node a, the first end of the transistor T20 is connected to the power supply end, the second end of the transistor T20 is connected to the signal receiving node B, the first end of the transistor T21 is connected to the signal receiving node a, the second end of the transistor T21 is connected to the signal receiving node B, and the control ends of the three transistors simultaneously receive the precharge signal EQ, thereby realizing fast precharge of the two receiving nodes.
Further, the data transmission circuit further includes a reset module, the reset module specifically includes transistors T14 to T18, a control terminal of the transistor T14 and a control terminal of the transistor T15 are connected to the signal receiving node B, a first terminal of the transistor T14 is connected to the power supply terminal, a second terminal of the transistor T14 is connected to the first terminal of the transistor T15, a second terminal of the transistor T15 is grounded via the transistor T17, a control terminal of the transistor T17 and a control terminal of the transistor T18 are used for receiving the reset signal Rst, a first terminal of the transistor T18 is connected to the power supply terminal, and a second terminal of the transistor T18 is connected to the second terminal of the transistor T14.
The embodiment of the present application further provides a data processing circuit as shown in fig. 1, where the data processing circuit includes the data transmission circuit 10 and the check generating circuit 20 as described above, and the check generating circuit 20 is connected to the check writing circuit 200, and is configured to obtain the data to be written, generate corresponding check data according to the data to be written, and transmit the check data to the check writing circuit 200. It can be appreciated that the data transmission circuit 10 of the present embodiment can refer to the foregoing embodiments, and will not be described herein, and based on the foregoing data transmission circuit 10, the present application provides a data processing circuit with a relatively high processing speed and a relatively high transmission speed.
The embodiment of the application also provides a memory, which comprises a data storage unit 400, a verification storage unit 500 and a data processing circuit as described above. It can be understood that the data processing circuit of the present embodiment can refer to the foregoing embodiment, and will not be described herein.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few implementations of the present examples, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that various modifications and improvements can be made to the present application without departing from the spirit of the embodiments of the application. Accordingly, the protection scope of the patent of the embodiments of the application shall be subject to the appended claims.
Claims (16)
1. A data transmission circuit, comprising:
The data writing circuit is used for transmitting data to be written to the global data line group, the global data line group comprises a first global data line and a second global data line, the first global data line and the second global data line which are arranged in pairs transmit data which are mutually opposite in phase, and the data to be written is transmitted to the data storage unit for storage through the global data line group;
The verification writing circuit is used for transmitting verification data to the global data line group connected with the verification storage unit so as to store the verification data, and the verification data corresponds to the data to be written;
the data write circuit and the check write circuit are used for synchronously transmitting data to the corresponding global data line group, and the driving capability of the check write circuit is stronger than that of the data write circuit.
2. The data transmission circuit of claim 1, wherein the circuit structures of the data write circuit and the verification write circuit are both first circuits, but the electrical parameters of the corresponding devices in the data write circuit and the verification write circuit are not identical, so that the driving capability of the verification write circuit is stronger than the driving capability of the data write circuit.
3. The data transmission circuit of claim 2, wherein the first circuit comprises:
The first driving module is connected with the first global data line and is used for responding to a write enabling signal, generating and transmitting a first write signal to the first global data line according to a data signal to be written, wherein the level state of the first write signal is the same as that of the data to be written;
The second driving module is connected with the second global data line and is used for responding to a write enabling signal, generating and transmitting a second write signal to the second global data line according to a data signal to be written, and the level state of the second write signal is opposite to that of the data to be written;
the driving capability of the first driving module of the verification write circuit is stronger than that of the first driving module of the data write circuit, and the driving capability of the second driving module of the verification write circuit is stronger than that of the second driving module of the data write circuit.
4. A data transmission circuit according to claim 3, wherein the first drive module comprises:
The control end of the first pull-up transistor is used for receiving the inverted data signal to be written, and the first end of the first pull-up transistor is connected with a power supply voltage end;
The control end of the first pull-down transistor is used for receiving the inverted data signal to be written, the first end of the first pull-down transistor is connected with the grounding end, and the second end of the first pull-down transistor is connected with the second end of the first pull-up transistor;
the channel width-to-length ratio of the first pull-up transistor in the verification write circuit is larger than that of the first pull-up transistor in the data write circuit, and the channel width-to-length ratio of the first pull-down transistor in the verification write circuit is larger than that of the first pull-down transistor in the data write circuit.
5. The data transmission circuit of claim 4, wherein a threshold voltage of a first pull-up transistor in the verify write circuit is less than a threshold voltage of a first pull-up transistor in the data write circuit.
6. The data transmission circuit of claim 4, wherein a threshold voltage of a first pull-down transistor in the verify write circuit is less than a threshold voltage of a first pull-down transistor in the data write circuit.
7. The data transfer circuit of claim 4, wherein the data transfer circuit is configured with a precharge phase and a data write phase, the first drive module further comprising:
a logic operation unit connected with the first pull-up transistor and the first pull-down transistor respectively, and used for responding to a write enable signal in the data writing stage to generate the inverted data signal to be written;
And the first NOT gate is connected with the logic operation unit and is used for controlling the logic operation unit to output a low-level signal in the precharge stage.
8. The data transmission circuit according to claim 7, wherein the logic operation unit includes:
The two input ends of the first AND gate are respectively used for receiving the data signals to be written and the write enabling signals in a one-to-one correspondence manner;
And one input end of the first NOR gate is connected with the output end of the first AND gate, the other input end of the first NOR gate is used for receiving an inverted pre-charge signal, the pre-charge signal is used for switching the data transmission circuit to a pre-charge stage or a data writing stage, and the output end of the first NOR gate is connected with the control end of the first pull-up transistor.
9. The data transmission circuit of claim 8, wherein the output of the first nor gate is further coupled to the control terminal of the first pull-down transistor.
10. The data transmission circuit of claim 8, wherein the logic operation unit further comprises:
the two input ends of the first NAND gate are respectively used for receiving the precharge signal and the write enable signal in a one-to-one correspondence;
And one input end of the second NOR gate is connected with the output end of the first NAND gate, the other input end of the second NOR gate is used for receiving the data signal to be written, and the output end of the second NOR gate is connected with the control end of the first pull-down transistor.
11. A data transfer circuit according to claim 3, wherein the data write circuit and the verify write circuit are responsive to the same write enable signal to transfer data to respective sets of global data lines.
12. A data transmission circuit according to claim 3, further comprising:
the data reading circuit is used for acquiring data to be read from the global data line group connected with the data storage unit so as to read the data to be read;
The verification reading circuit is used for acquiring verification data from the global data line group connected with the verification storage unit so as to read the stored verification data, and the stored verification data corresponds to the data to be read;
wherein the driving capability of the verification reading circuit is equal to the driving capability of the data reading circuit.
13. The data transmission circuit of claim 12, wherein the circuit structures of the data reading circuit and the verification reading circuit are both second circuits, and the electrical parameters of the corresponding devices in the data reading circuit and the verification reading circuit are the same.
14. The data transmission circuit of claim 13, wherein the first global data line is further configured to transmit a first read signal, wherein the second global data line is further configured to transmit a second read signal, wherein the first read signal has a level state that is the same as the data to be read, wherein the second read signal has a level state that is opposite to the data to be read, and wherein the second circuit comprises:
the signal processing module is respectively connected with the first global data line and the second global data line and is used for responding to the read enabling signal and generating a read driving signal according to the first read signal and the second read signal;
and the reading driving module is connected with the signal processing module and is used for outputting the read data to be read according to the reading driving signal.
15. A data processing circuit, comprising:
a data transmission circuit as claimed in any one of claims 1 to 14;
And the verification generating circuit is connected with the verification writing circuit and is used for acquiring the data to be written, generating corresponding verification data according to the data to be written and transmitting the verification data to the verification writing circuit.
16. A memory, comprising: a data storage unit, a verification storage unit and a data processing circuit as claimed in claim 15.
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| JP2010156225A (en) * | 2008-12-26 | 2010-07-15 | Toyota Motor Corp | Vehicular engine output control device |
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| KR950010595Y1 (en) * | 1993-01-15 | 1995-12-21 | 금성일렉트론 주식회사 | Control circuit of dram parity |
| JP2013073663A (en) * | 2011-09-29 | 2013-04-22 | Elpida Memory Inc | Semiconductor device |
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| JP2010156225A (en) * | 2008-12-26 | 2010-07-15 | Toyota Motor Corp | Vehicular engine output control device |
| CN107818802A (en) * | 2016-09-13 | 2018-03-20 | 东芝存储器株式会社 | Semiconductor device and accumulator system |
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