CN113221498B - Method for reducing metal area - Google Patents
Method for reducing metal area Download PDFInfo
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- CN113221498B CN113221498B CN202110459064.8A CN202110459064A CN113221498B CN 113221498 B CN113221498 B CN 113221498B CN 202110459064 A CN202110459064 A CN 202110459064A CN 113221498 B CN113221498 B CN 113221498B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention discloses a method for reducing metal area, which comprises the following steps: the first step, the large metal block is subjected to graph segmentation, and the method comprises the following steps: subtracting the pattern of the through holes or the contact holes included in the large metal block from the original pattern of the large metal block, and then dividing the original pattern of the large metal block from which the pattern of the through holes or the contact holes is subtracted into a plurality of block patterns. Step two, sequentially verifying and classifying each block graph, comprising the following steps: subtracting the block pattern from the original pattern of the large metal block to form an intermediate pattern; if the patterns of the metal wires on the periphery of the middle pattern and the large metal block are kept to be of an integral structure, verifying that the block patterns are of a first type, and otherwise, verifying that the block patterns are of a second type; step three, carrying out graphic integration, which comprises the following steps: and integrating all the second type of block patterns and patterns of the areas provided with the through holes or the contact holes in the original patterns to form a new pattern of the large metal block. The invention can automatically reduce the area of the large metal block, save time and labor cost and improve efficiency.
Description
Technical Field
The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for reducing metal area.
Background
In the layout design process, it is sometimes necessary to implement placement of more patterns, such as vias, within a limited space. As shown in fig. 1A, an enlarged view of a region where a large metal block exists in the conventional layout, and a metal line 102 and a via 103 exist in a region shown in a layout 101A corresponding to fig. 1A, where the via 103 is used to realize connection between different metal layers. There is a large metal block in the area shown by the dashed circle 104, which would have a width greater than the width of the metal line 102. In some design rules of the process, when the area of the large metal block is larger than a certain value, the placement of the through holes needs to be increased, for example, in one process, more than 2 through holes 103 need to be drilled in the region of the large metal block with the area larger than 0.3 micrometers×0.3 micrometers.
FIG. 1B is an enlarged view of the layout of FIG. 1A with vias added near the large metal blocks; it can be seen that a through hole 103 is added in the area indicated by the dashed circle 104.
In addition, in the actual situation, too dense a circuit may occur, and two through holes cannot be drilled, so that the area of the large metal block needs to be reduced to meet the requirement of the design rule.
In the existing method, the correction of the layout, such as increasing the through holes or reducing the area of large metal blocks, is completed manually, which is time-consuming and labor-consuming, because the number of patterns in the layout is numerous, and the number of large metal blocks needing correction is thousands.
As shown in fig. 2A, which is a conventional thumbnail of a layout, as can be seen from the layout 101c of fig. 2A, many graphics with dense hemp are provided on the layout 101c, and a specific graphic structure cannot be displayed in the thumbnail, which is only used for representing the numerous graphics in the layout 101 c.
As shown in fig. 2B, the layout 101d shows only the large metal blocks that need to be corrected, and as shown in fig. 2B, many figures of the milbex are shown in fig. 2B, and a specific figure structure cannot be shown in the thumbnail, which is only used to show the large metal blocks that need to be corrected in the layout 101 d.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for reducing the metal area, which can automatically reduce the area of a large metal block, save time and labor cost and improve efficiency.
In order to solve the technical problems, the method for reducing the metal area provided by the invention comprises the following steps:
The method comprises the steps of firstly, carrying out graph segmentation on a large metal block needing area reduction, wherein the width of the large metal block is larger than that of a metal wire on a layout, and a through hole or a contact hole is arranged in the region of the large metal block.
The graph segmentation includes: subtracting the area provided with the through holes or the contact holes in the large metal block from the original pattern of the large metal block, and then dividing the original pattern of the large metal block subtracted with the area provided with the through holes or the contact holes into a plurality of block patterns.
Step two, sequentially carrying out verification classification on each block graph, wherein the verification step of each block graph comprises the following steps:
Subtracting the block pattern from the original pattern of the large metal block and forming an intermediate pattern of the large metal block.
If the middle pattern of the large metal block and the pattern of the metal wire on the periphery of the large metal block are kept in an integral structure, verifying the block pattern as a first type; and otherwise, verifying the block graph as a second type.
Step three, carrying out graphic integration, which comprises the following steps: and integrating all the block patterns of the second type and patterns of the areas where the through holes or the contact holes are arranged in the original patterns of the large metal blocks to form new patterns of the large metal blocks, and removing all the block patterns of the first type in the new patterns of the large metal blocks to reduce the area of the large metal blocks.
In the first step, the number of through holes or contact holes required to be arranged in the area of the large metal block is larger than the number of through holes or contact holes arranged in the large metal block according to the rule of design rules.
In the third step, according to the rule of design rule, the number of through holes or contact holes required to be arranged in the area of the large metal block after the pattern integration is smaller than or equal to the number of through holes or contact holes arranged in the large metal block.
A further improvement is that before the first step, the method further comprises: and picking out the original graph of the large metal block from the layout data.
A further improvement is that the original graph of the large metal block is automatically selected from the layout data through SIZING functions.
A further improvement is that SIZING functions are implemented in the c++ language.
In a further improvement, the SIZING function picks out the original patterns of all the large metal blocks included in the layout data.
A further improvement is to circularly carry out the first to third steps until the area of all the large metal blocks is reduced.
In the first step, the original pattern subtracting area of the large metal block further comprises an overlapping area generated by an overlay error between the through hole or the contact hole and the large metal block.
Further, the number of contact holes or through holes provided in the region where the area of the large metal block is larger than 0.3 μm×0.3 μm is 2 or more as specified by the design rule.
In a further improvement, the contact hole is arranged at the bottom of the first metal layer and is positioned at the top of the gate structure, the source region or the drain region of the semiconductor device.
A further improvement is that the through holes are arranged between the metal layers above the first metal layer.
The further improvement is that the pattern of the through hole is square, and the pattern of the contact hole is square.
In a further improvement, the side length of the through hole is smaller than the width of the metal wire, and the side length of the contact hole is smaller than the width of the metal wire.
A further improvement is that the via hole or the contact hole is also provided in the metal line.
In the second step, when the block pattern is verified as the second type, the connection between the middle pattern of the large metal block and the pattern of the metal line on the periphery of the large metal block is broken or the width of the connection is reduced.
The invention can automatically realize the steps of dividing the large metal block into a plurality of block patterns, then verifying and classifying the block patterns to determine whether the block patterns can be removed from the large metal block, and then integrating the patterns to form the large metal block with reduced area.
In addition, for one layout, a plurality of large metal blocks are often arranged, and the invention can automatically reduce all the large metal blocks in the layout, so the invention can greatly save time and labor cost and greatly improve efficiency.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1A is an enlarged view of a region of a prior art layout where large metal blocks are present;
FIG. 1B is an enlarged view of the layout of FIG. 1A with through holes added near the large metal block;
FIG. 2A is a prior art layout thumbnail;
FIG. 2B is a diagram of the location of the large metal block of FIG. 2A;
FIG. 3 is a flow chart of a method of reducing metal area according to an embodiment of the present invention;
FIG. 4A is a diagram of metal lines near a large metal block in a layout of a method of an embodiment of the present invention;
FIG. 4B is a graphic of a large metal block selected from FIG. 4A;
FIG. 4C is a graph after graph segmentation of the large metal block of FIG. 4B;
FIG. 4D is an intermediate graph formed during verification of a second class of tile graphs in the method of an embodiment of the present invention;
FIG. 4E is an intermediate graph formed during verification of a first type of tile graph in a method in accordance with an embodiment of the present invention.
Detailed Description
FIG. 3 is a flow chart of a method for reducing metal area according to an embodiment of the invention; the method for reducing the metal area comprises the following steps:
Before the subsequent step one, the method comprises the following steps: the original pattern of the large metal block 202 is picked from the layout data. FIG. 4A is a diagram of a metal line 201 near a large metal block 202 in the layout of the method of an embodiment of the present invention; as shown in fig. 4A, a large metal block 202 is provided on the metal line 201, and 2 contact holes 203 and 1 via 204 are provided on the large metal block 202.
Preferably, the original pattern of the large metal block 202 is automatically selected from the layout data by SIZING functions. SIZING functions are implemented in the c++ language. SIZING functions can be implemented using functions already in the layout tool, or otherwise programmed; the SIZING function can select the desired large metal block 202 based on the size of the metal.
The SIZING function picks out all of the original patterns of the large metal block 202 that are included in the layout data.
For the pattern of FIG. 4A, large metal pieces 202 may be selected; figure 4B shows the pattern of large metal pieces 202 individually selected from figure 4A.
The first step is to divide the large metal block 202 with the area required to be reduced, wherein the width of the large metal block 202 is larger than the width of the metal line 201 on the layout, and the region of the large metal block 202 is provided with a through hole 204 or a contact hole 203.
The graph segmentation includes: the original pattern of the large metal block 202 is subtracted from the area of the large metal block 202 where the through hole 204 or the contact hole 203 is provided, and then the original pattern of the large metal block 202 from which the area of the through hole 204 or the contact hole 203 is subtracted is divided into a plurality of block patterns.
In the embodiment of the present invention, the area subtracted from the original pattern of the large metal block 202 further includes an overlapping area between the through hole 204 or the contact hole 203 and the large metal block 202 due to an overlay error. This does not adversely affect the formation of the via 204 or the contact hole 203 due to an overlay error after the large metal block 202 is reduced.
As shown in fig. 4C, which is a graph obtained by graph-dividing the large metal block 202 of fig. 4B, it can be seen that the large metal block 202 is divided into 9 block-divided graphs of marks 2021, 2022 to 2029.
Step two, sequentially carrying out verification classification on each block graph, wherein the verification step of each block graph comprises the following steps:
Subtracting the block pattern from the original pattern of the large metal block 202 and forming an intermediate pattern of the large metal block 202.
If the middle pattern of the large metal block 202 and the pattern of the metal line 201 on the peripheral side of the large metal block 202 remain in an integral structure, the block pattern is verified as a first type; and otherwise, verifying the block graph as a second type. In the embodiment of the present invention, when the block pattern is verified as the second type, the connection between the middle pattern of the large metal block 202 and the pattern of the metal line 201 on the peripheral side of the large metal block 202 is broken or the width of the connection is reduced.
FIG. 4D is a schematic illustration showing an intermediate graph formed during verification of a second class of block graphs in the method of the present invention; in fig. 4D, the block pattern to be verified is a block pattern corresponding to the mark 2021, the intermediate pattern formed by subtracting the block pattern 2021 from the large metal block 202 is denoted by the mark 202a, and it can be seen that at the dashed circle 301, the intermediate pattern 202a and the metal line 201 are not connected, so that they are not in a unitary structure, and therefore the block pattern 2021 is classified into the second type.
FIG. 4E is a diagram illustrating an intermediate pattern formed during verification of a first type of block pattern in the method according to the embodiment of the present invention; in fig. 4E, the block pattern is a block pattern corresponding to the mark 2022, the intermediate pattern obtained by subtracting the block pattern 2022 is denoted by the mark 202b, it can be seen that the intermediate pattern 202b and the metal lines 201 of the two layers can still form a complete connection, so that the pattern structure after removing the block pattern 2022 is still an overall structure, and the block pattern 2022 is classified as the first type.
The verification of each of the block patterns corresponding to the marks 2023, 2024 to 2029 is similar to the verification of the block patterns 2021 and 2022, and finally the block patterns 2021, 2022 to 2029 can be classified into two types, wherein the block patterns 2021, 2027 and 2028 are classified into the second type, and the block patterns 2022 to 2026 and 2029 are classified into the first type.
Step three, carrying out graphic integration, which comprises the following steps: and integrating all the block patterns of the second type and the patterns of the areas where the through holes 204 or the contact holes 203 are arranged in the original patterns of the large metal block 202 to form a new pattern of the large metal block 202, and removing all the block patterns of the first type in the new pattern of the large metal block 202 to reduce the area of the large metal block 202.
In the first embodiment of the present invention, according to the rule of design, the number of through holes 204 or contact holes 203 required to be disposed in the area of the large metal block 202 is greater than the number of through holes 204 or contact holes 203 disposed in the large metal block 202. After the area of the large metal block 202 is reduced, there are: in the third step, according to the rule of design rule, the number of through holes 204 or contact holes 203 required to be set in the area of the large metal block 202 after the pattern integration is smaller than or equal to the number of through holes 204 or contact holes 203 set in the large metal block 202. Therefore, the area of the large metal block 202 is reduced without adding the through hole 204 or the contact hole 203. In one or more processes, the number of the contact holes 203 or the through holes 204 provided in the region where the area of the large metal block 202 is larger than 0.3 μm×0.3 μm is 2 or more as specified by the design rule.
The first to third steps are to automatically shrink one large metal block 202. Since one layout has a plurality of large metal blocks 202, the area of all the large metal blocks 202 is reduced by circularly performing the first to third steps.
The contact hole 203 is disposed at the bottom of the first metal layer, and the contact hole 203 is located at the top of the gate structure, the source region, or the drain region of the semiconductor device.
The vias 204 are disposed between the metal layers above the first metal layer.
The pattern of the via 204 is square, and the pattern of the contact hole 203 is square.
The side length of the through hole 204 is smaller than the width of the metal line 201, and the side length of the contact hole 203 is smaller than the width of the metal line 201.
The via 204 or the contact hole 203 is also provided on the metal line 201.
The embodiment of the invention obtains a plurality of block patterns by carrying out pattern segmentation on the large metal block 202, then verifies and classifies the block patterns to determine whether the block patterns can be removed from the large metal block 202, and then carries out pattern integration to form the large metal block 202 with reduced area.
In addition, for a layout, a plurality of large metal blocks 202 are often arranged, and the embodiment of the invention can automatically reduce all the large metal blocks 202 in the layout, so that the embodiment of the invention can greatly save time and labor cost and greatly improve efficiency.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (16)
1. A method of reducing a metal area comprising the steps of:
Firstly, carrying out graph segmentation on a large metal block needing area reduction, wherein the width of the large metal block is larger than that of a metal wire on a layout, and a through hole or a contact hole is arranged in the region of the large metal block;
The graph segmentation includes: subtracting the area provided with the through holes or the contact holes in the large metal block from the original pattern of the large metal block, and then dividing the original pattern of the large metal block subtracted with the area provided with the through holes or the contact holes into a plurality of block patterns;
Step two, sequentially carrying out verification classification on each block graph, wherein the verification step of each block graph comprises the following steps:
Subtracting the block pattern from the original pattern of the large metal block and forming an intermediate pattern of the large metal block;
If the middle pattern of the large metal block and the pattern of the metal wire on the periphery of the large metal block are kept in an integral structure, verifying the block pattern as a first type; otherwise, verifying the block graph as a second class;
step three, carrying out graphic integration, which comprises the following steps: and integrating all the block patterns of the second type and patterns of the areas where the through holes or the contact holes are arranged in the original patterns of the large metal blocks to form new patterns of the large metal blocks, and removing all the block patterns of the first type in the new patterns of the large metal blocks to reduce the area of the large metal blocks.
2. The method of reducing metal area of claim 1, wherein: in the first step, according to the rule of design rule, the number of through holes or contact holes required to be arranged in the area of the large metal block is larger than the number of through holes or contact holes arranged in the large metal block.
3. The method of reducing metal area of claim 2, wherein: and thirdly, according to the rule of design rules, the number of through holes or contact holes required to be arranged in the area of the large metal block after the pattern integration is smaller than or equal to the number of through holes or contact holes arranged in the large metal block.
4. The method of reducing metal area of claim 1, wherein: before the first step, the method further comprises: and picking out the original graph of the large metal block from the layout data.
5. The method of reducing metal area of claim 4, wherein: and automatically picking out the original graph of the large metal block from the layout data through SIZING functions.
6. The method of reducing metal area of claim 5, wherein: SIZING functions are implemented in the c++ language.
7. The method of reducing metal area of claim 5, wherein: and the SIZING function picks out the original graphs of all the large metal blocks included in the layout data.
8. The method of reducing metal area of claim 5, wherein: and circularly carrying out the first step to the third step until the area of all the large metal blocks is reduced.
9. The method of reducing metal area of claim 1, wherein: in the first step, the original pattern subtracting area of the large metal block further comprises an overlapping area between the through hole or the contact hole and the large metal block due to an overlay error.
10. A method of reducing metal area as defined in claim 2 or 3, wherein: the number of contact holes or through holes provided in the region where the area of the large metal block is larger than 0.3 μm×0.3 μm is 2 or more as specified by the design rule.
11. The method of reducing metal area of claim 1, wherein: the contact hole is arranged at the bottom of the first metal layer and is positioned at the top of the grid structure, the source region or the drain region of the semiconductor device.
12. The method of reducing metal area of claim 11, wherein: the first metal layer comprises a plurality of metal layers, and the through holes are arranged among the metal layers above the first metal layer.
13. The method of reducing metal area of claim 1, wherein: the pattern of the through hole is square, and the pattern of the contact hole is square.
14. The method of reducing metal area of claim 13, wherein: the side length of the through hole is smaller than the width of the metal wire, and the side length of the contact hole is smaller than the width of the metal wire.
15. The method of reducing metal area of claim 14, wherein: the metal line is also provided with the through hole or the contact hole.
16. The method of reducing metal area of claim 1, wherein: in the second step, when the block pattern is verified to be of the second type, the connection between the middle pattern of the large metal block and the pattern of the metal wire on the periphery of the large metal block is broken or the width of the connection part is reduced.
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| CN202110459064.8A CN113221498B (en) | 2021-04-27 | 2021-04-27 | Method for reducing metal area |
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| CN119784779B (en) * | 2025-03-11 | 2025-06-03 | 合肥晶合集成电路股份有限公司 | Layout metal hole arrangement method, layout metal hole arrangement system, layout metal hole arrangement equipment and storage medium |
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| CN102855360A (en) * | 2012-09-11 | 2013-01-02 | 中国科学院微电子研究所 | Optimization design method of nano-process metal layer layout |
| CN103941550A (en) * | 2014-03-24 | 2014-07-23 | 上海华力微电子有限公司 | Intellectualized selective target size adjusting method |
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| JP2005228999A (en) * | 2004-02-13 | 2005-08-25 | Sharp Corp | Semiconductor integrated circuit layout pattern correcting apparatus, semiconductor integrated circuit layout pattern correcting method, semiconductor integrated device manufacturing method, semiconductor integrated circuit layout pattern correcting program, and readable recording medium |
| US8703507B1 (en) * | 2012-09-28 | 2014-04-22 | Freescale Semiconductor, Inc. | Method and apparatus to improve reliability of vias |
| CN104952076B (en) * | 2015-06-18 | 2017-10-31 | 哈尔滨工程大学 | Image partition method based on piecemeal similarity measurement |
| CN106444273B (en) * | 2016-10-10 | 2020-01-10 | 上海华力微电子有限公司 | Method for adding and processing small-size redundant graph of metal wire layer |
| CN106874543B (en) * | 2017-01-04 | 2020-06-09 | 上海华虹宏力半导体制造有限公司 | LEF graph processing method of layout |
| CN108763723A (en) * | 2018-05-23 | 2018-11-06 | 上海华力微电子有限公司 | A kind of redundant pattern adding method |
| CN109101756B (en) * | 2018-08-31 | 2023-06-16 | 上海华力微电子有限公司 | Redundant graph adding method |
| CN109614705B (en) * | 2018-12-12 | 2023-06-16 | 上海华力集成电路制造有限公司 | Method for generating auxiliary pattern of metal layer device |
| CN111025841B (en) * | 2019-12-30 | 2023-07-25 | 上海集成电路研发中心有限公司 | A Method for Optimizing the Process Window of Metal Line Optical Proximity Correction |
| CN111596528B (en) * | 2020-05-25 | 2023-02-03 | 上海华力集成电路制造有限公司 | Polycrystalline silicon cutting pattern adding method |
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| CN102855360A (en) * | 2012-09-11 | 2013-01-02 | 中国科学院微电子研究所 | Optimization design method of nano-process metal layer layout |
| CN103941550A (en) * | 2014-03-24 | 2014-07-23 | 上海华力微电子有限公司 | Intellectualized selective target size adjusting method |
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