CN113192981B - A kind of preparation method of TFT substrate, display device and TFT substrate - Google Patents

Abstract

The invention provides a TFT substrate, a display device and a preparation method of the TFT substrate, wherein the TFT array substrate is provided with a double-layer storage capacitor structure, so that the pixel area is reduced, the PPI of a display panel is improved, and the flexibility of layout design is improved on the premise of ensuring the certain capacity of the storage capacitor of a TFT device and the reliability of the TFT device; in addition, by arranging the auxiliary metal layer between the first metal layer and the third metal layer, the insulating layers above and below the auxiliary metal layer can be simultaneously patterned through one-time patterning process, so that one mask plate can be saved, the processes of exposure, etching, stripping and the like of one patterning process can be reduced, and the processing cost of the TFT array substrate can be saved; the display device provided by the invention adopts the TFT array substrate, so that the pixel distribution density of the display device is greatly improved and the display picture is clearer under the same display size.

Description

A kind of preparation method of TFT substrate, display device and TFT substrate

This case is a divisional application based on the invention patent with the application date of 2018-03-21, the application number 201810234371.4, and the title "A TFT array substrate, display device, and method for preparing a TFT array substrate".

technical field

The invention relates to the field of display technology, in particular to a TFT substrate, a display device and a preparation method of the TFT substrate.

Background technique

Since the display screen always has high-definition requirements, this requires the pixel area to be continuously reduced to increase the pixel distribution density (PPI). In recent years, the improvement of the pixel density (PPI) of the display panel is generally limited by the size and wiring pitch of the thin film transistor (TFT) in the pixel structure, and the PPI can be improved by reducing the size of the TFT and the wiring pitch. For example, the method of sharing electrodes is used to reduce the wiring pitch to achieve the effect of improving PPI. However, the continuous reduction of the pixel area will inevitably lead to the increase of the complexity of the process, the continuous reduction of the storage capacity of the TFT device, and even make it difficult to guarantee the reliability of the TFT device.

Contents of the invention

The technical problem to be solved by the present invention is to provide a TFT substrate, a display device, and a method for preparing the TFT substrate. The TFT array substrate has a double-layer storage capacitor structure, which can reduce the pixel area, improve the PPI of the display panel, and increase the flexibility of layout design while ensuring a constant capacity of the storage capacitor of the TFT device and ensuring the reliability of the TFT device.

In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is:

A TFT array substrate comprising a first metal layer, an active layer, a third metal layer and an auxiliary metal layer; the first metal layer forms a gate, the third metal layer forms a source and a drain, the active layer between the source and the drain is a channel region; the third metal layer is located above the first metal layer, the auxiliary metal layer is located between the first metal layer and the third metal layer, and the first metal layer, the third metal layer and the auxiliary metal layer are separated by an insulating layer; The insulating layer between the layers forms a first storage capacitor; the third metal layer, the auxiliary metal layer, and the insulating layer sandwiched between the third metal layer and the auxiliary metal layer form a second storage capacitor.

Another technical scheme that the present invention adopts is:

A display device includes the above-mentioned TFT array substrate.

Another technical scheme that the present invention adopts is:

A method for preparing a TFT array substrate, comprising the steps of:

Step 1: sequentially forming a gate, a gate insulating layer, an active layer and an etching barrier layer on the substrate, the gate being formed by a first metal layer;

Step 2: forming an auxiliary metal layer on the etching barrier layer;

Step 3: forming a passivation layer on the etching barrier layer and the auxiliary metal layer;

Step 4: Simultaneously pattern the passivation layer and the etching barrier layer through a patterning process to form a first via hole and a second via hole connected to the active layer;

Step 5: forming a third metal layer on the passivation layer, the third metal layer is connected to the active layer through the first via hole and the second via hole; the third metal layer forms a source electrode and a drain electrode at the first via hole and the second via hole respectively.

The beneficial effects of the present invention are:

In the TFT array substrate provided by the present invention, an auxiliary metal layer is added between the first metal layer forming the gate and the third metal layer forming the source and drain, and a double-layer storage capacitor structure is formed between the three metal layers, so that the pixel area can be reduced, the PPI of the display panel can be improved, and the flexibility of layout design can be increased under the premise of ensuring a certain storage capacity of the TFT device and the reliability of the TFT device; in addition, the auxiliary metal layer is arranged between the first metal layer and the third metal layer, so that the insulating layers above and below the auxiliary metal layer can be patterned simultaneously through a patterning process. , which can save a mask, reduce the exposure, etching and stripping process of a patterning process, and save the process cost.

Description of drawings

FIG. 1 is a schematic structural diagram of a TFT array substrate according to Embodiment 1 of the present invention;

FIG. 2 is a process diagram of steps 1-4 of a method for preparing a TFT array substrate according to Embodiment 2 of the present invention;

FIG. 3 is a process diagram of steps 5-7 of a method for preparing a TFT array substrate according to Embodiment 2 of the present invention;

FIG. 4 is a process diagram of steps 8-10 of a method for preparing a TFT array substrate according to Embodiment 2 of the present invention;

FIG. 5 is an equivalent circuit diagram of an AMOLED display device according to Embodiment 3 of the present invention;

FIG. 6 shows a wiring design layout of an AMOLED display device according to Embodiment 3 of the present invention;

FIG. 7 is a schematic structural diagram of a double-layer capacitor of an AMOLED display device according to Embodiment 3 of the present invention;

Label description:

1. Substrate; 2. First metal layer; 3. Gate insulating layer; 4. Active layer; 5. Etching barrier layer; 6. Auxiliary metal layer; 7. Passivation layer; 8. First via hole; 9. Second via hole; 10. Third metal layer; 11. Source electrode; 12. Drain electrode; 13. Planarization layer; 14. Third via hole;

Detailed ways

In order to describe the technical content, achieved goals and effects of the present invention in detail, the following descriptions will be made in conjunction with the embodiments and accompanying drawings.

The most critical idea of the present invention is: an auxiliary metal layer is added between the first metal layer forming the gate and the third metal layer forming the source and drain, and a double-layer storage capacitor structure is formed between the three metal layers, so that the pixel area can be reduced and the PPI can be improved while ensuring a certain storage capacitor capacity of the TFT device; in addition, the auxiliary metal layer is arranged between the first metal layer and the third metal layer, so that the insulating layers above and below the auxiliary metal layer can be patterned simultaneously through a single patterning process.

The present invention provides a TFT array substrate, comprising a first metal layer, an active layer, a third metal layer and an auxiliary metal layer; the first metal layer forms a gate, the third metal layer forms a source and a drain, and the active layer between the source and drain is a channel region; the third metal layer is located above the first metal layer, the auxiliary metal layer is located between the first metal layer and the third metal layer, and the first metal layer, the third metal layer and the auxiliary metal layer are separated by an insulating layer; The insulating layer between the auxiliary metal layers constitutes a first storage capacitor; the third metal layer, the auxiliary metal layer and the insulating layer sandwiched between the third metal layer and the auxiliary metal layer constitute a second storage capacitor.

As can be seen from the foregoing description, the beneficial effects of the present invention are:

In the TFT array substrate provided by the present invention, an auxiliary metal layer is added between the first metal layer forming the gate and the third metal layer forming the source and drain, and a double-layer storage capacitor structure is formed between the three metal layers, so that the pixel area can be reduced, the PPI of the display panel can be improved, and the flexibility of layout design can be increased under the premise of ensuring a certain storage capacity of the TFT device and the reliability of the TFT device; in addition, the auxiliary metal layer is arranged between the first metal layer and the third metal layer, so that the insulating layers above and below the auxiliary metal layer can be patterned simultaneously through a patterning process. , which can save a mask, reduce the exposure, etching and stripping process of a patterning process, and save the process cost.

Further, the TFT array substrate includes a substrate, a gate formed by a first metal layer disposed on the substrate, a gate insulating layer disposed on the substrate and the gate, an active layer disposed on the gate insulating layer, an etching barrier layer disposed on the active layer and the gate insulating layer, an auxiliary metal layer disposed on the etching barrier layer, a passivation layer disposed on the etching barrier layer and the auxiliary metal layer, first via holes passing through the passivation layer and the etching barrier layer and respectively corresponding to the upper sides of the active layer and a second via hole, a third metal layer disposed on the passivation layer, the third metal layer is respectively connected to the active layer through the first via hole and the second via hole; the third metal layer forms a source electrode and a drain electrode at the first via hole and the second via hole respectively.

Further, the TFT array substrate further includes a planarization layer provided on the source, drain and passivation layer, a third via hole passing through the planarization layer and corresponding to above the drain, an anode provided on the planarization layer and connected to the drain through the third via hole, and a fourth insulating layer provided on the planarization layer and the anode, and a fourth via hole is provided on the fourth insulating layer corresponding to the position above the anode.

Wherein, the material of each insulating layer may be one or more of silicon oxide SiO _x , silicon nitride SiN _x , silicon oxynitride SiON, and aluminum oxide Al ₂ O ₃ .

Further, the anode has an ITO/Ag/ITO sandwich layer structure.

Further, the active layer is formed of an amorphous oxide (IGZO) film material containing indium, gallium and zinc.

Further, the first metal layer, the auxiliary metal layer and the third metal layer all have a Mo/Al/Mo sandwich layer structure. Certainly, the first metal layer, the auxiliary metal layer and the third metal layer may also be metal layers formed of metals or alloys such as Mo, Mo/Al/Nd/Mo or Au/Ti.

The present invention also provides a display device, comprising the above-mentioned TFT array substrate. The display device may be any device with a display function such as a TV, a display panel, a monitor, a tablet computer, a mobile phone, a navigator, a camera or a video camera.

As can be seen from the foregoing description, the beneficial effects of the present invention are:

The display device provided by the present invention adopts the above-mentioned TFT array substrate. Under the same display size, the pixel distribution density of the display device is greatly improved, and the display screen is clearer.

The present invention also provides a method for preparing a TFT array substrate, comprising the following steps:

Step 1: sequentially forming a gate, a gate insulating layer, an active layer and an etching barrier layer on the substrate, the gate being formed by a first metal layer;

Step 2: forming an auxiliary metal layer on the etching barrier layer;

Step 3: forming a passivation layer on the etching barrier layer and the auxiliary metal layer;

Step 4: Simultaneously pattern the passivation layer and the etching barrier layer through a patterning process to form a first via hole and a second via hole connected to the active layer;

Step 5: forming a third metal layer on the passivation layer, the third metal layer is connected to the active layer through the first via hole and the second via hole; the third metal layer forms a source electrode and a drain electrode at the first via hole and the second via hole respectively.

Further, after the step 5, the following steps are also included:

forming a planarization layer on the passivation layer, source and drain;

performing patterning on the planarization layer to form a third via hole; the third via hole passes through the planarization layer and is connected to the drain;

forming an anode on the planarization layer, the anode is connected to the drain through the third via hole;

and depositing a fourth insulating layer on the planarization layer and the anode, patterning the fourth insulating layer, and forming a fourth via hole on the fourth insulating layer corresponding to the position above the anode.

The metal layers can be formed by methods such as physical vapor deposition or sputtering, and the insulating layers can be formed by methods such as chemical vapor deposition or sputtering.

Further, the step of forming the active layer is: depositing an IGZO thin film on the gate insulating layer by physical vapor deposition, and then forming the required active layer pattern through exposure, etching and stripping processes.

Please refer to Fig. 1, embodiment one of the present invention is:

A TFT array substrate, comprising a substrate 1, a gate formed by a first metal layer 2 disposed on the substrate 1, a gate insulating layer 3 disposed on the substrate 1 and the gate, an active layer 4 disposed on the gate insulating layer 3, an etching barrier layer 5 disposed on the active layer 4 and the gate insulating layer 3, an auxiliary metal layer 6 disposed on the etching barrier layer 5, a passivation layer 7 disposed on the etching barrier layer 5 and the auxiliary metal layer 6, passing through the passivation layer 7 and the etching barrier layer 5 And respectively corresponding to the first via hole 8 and the second via hole 9 above the two sides of the active layer 4, and the third metal layer 10 arranged on the passivation layer 7, the third metal layer 10 is respectively connected to the active layer 4 through the first via hole 8 and the second via hole 9; the third metal layer 10 forms a source electrode 11 and a drain electrode 12 at the first via hole 8 and the second via hole 9 respectively; Storage capacitor: the third metal layer 10 , the auxiliary metal layer 6 and the insulating layer sandwiched between the third metal layer 10 and the auxiliary metal layer 6 form a second storage capacitor.

The TFT array substrate also includes a planarization layer 13 arranged on the source electrode 11, drain electrode 12 and passivation layer 7, a third via hole 14 passing through the planarization layer 13 and corresponding to the top of the drain electrode 12, an anode 15 arranged on the planarization layer 13 and connected to the drain electrode 12 through the third via hole 14, and a fourth insulating layer 16 arranged on the planarization layer 13 and the anode 15. The fourth via hole 17 .

The anode 15 has an ITO/Ag/ITO sandwich layer structure.

The active layer 4 is formed of IGZO film material.

The first metal layer 2, the auxiliary metal layer 6 and the third metal layer 10 all have a Mo/Al/Mo sandwich layer structure.

Please refer to Fig. 2 to Fig. 4, embodiment two of the present invention is:

A method for preparing a TFT array substrate, comprising the steps of:

Step 1: Evaporate the first metal layer (M1) 2 on the substrate 1 by physical vapor deposition (PVD), generally with a Mo/AL/Mo sandwich layer structure, expose (photo) after coating the photoresist, form the required pattern according to the mask (MASK) design, and then etch the first metal layer (M1) 2 to form the pattern of the gate (GE);

Step 2: Evaporating a gate insulating layer (GI) 3 on the substrate treated in step 1 by chemical vapor deposition (CVD);

Step 3: Evaporate an IGZO film on the substrate treated in step 2 by PVD method, and go through exposure (photo), etching (etch) and stripping (stripe) processes; finally form the required pattern of the active layer (SE) 4;

Step 4: Evaporating an etching stopper layer (ES) 5 on the substrate treated in step 3 by CVD;

Step 5: An auxiliary metal layer (M2) 6 is vapor-deposited on the substrate processed in step 4, generally having a Mo/AL/Mo sandwich layer structure, exposed (photo) after coating the photoresist, and the required pattern is formed according to the mask plate (MASK), and then the auxiliary metal layer (M2) 6 is etched (etch) to form the wiring pattern of the auxiliary metal layer 6;

Step 6: Evaporate a passivation layer (PV) 7 on the substrate treated in step 5, and use a mask plate (MASK) to simultaneously perform exposure (photo), etching (etch) and stripping (stripe) processes on the passivation layer (PV) 7 and the etching stopper layer (ES) 5; form a first via hole 8 and a second via hole 9 connecting the active layer (SE) 4;

Step 7: Evaporate the third metal layer (M3) 10 on the substrate treated in step 6, generally Mo/AL/Mo sandwich layer structure, expose (photo) after photoresist coating, form the required pattern according to the mask plate (MASK) design, then etch the third metal layer (M3) 10 to form the wiring pattern of the third metal layer (M3) 10; the third metal layer (M3) 10 is formed at the first via hole 8 and the second via hole 9 respectively A source 11 and a drain 12 connected to the active layer (SE) 4;

Step 8: Evaporate a planarization layer (OC) 13 on the substrate treated in step 7 by CVD, and go through exposure (photo), etching (etch) and stripping (stripe) processes after photoresist coating to form a third via hole 14 connected to the drain electrode 12;

Step 9: On the substrate treated in step 8, an anode metal layer is vapor-deposited by PVD method, which is generally an ITO/Ag/ITO sandwich layer structure, exposed (photo) after photoresist coating, and the required pattern is formed according to the mask plate (MASK) design, and then the wiring pattern of the anode (anode) 15 is formed through etching (etch) and stripping (stripe) processes, and the anode metal layer is connected to the drain electrode 12 at the third via hole 14;

Step 10: Evaporate a fourth insulating layer (PDL) 16 on the substrate treated in step 8 by CVD, and after photoresist coating, go through exposure (photo), etching (etch) and stripping (stripe) processes, and form a fourth via hole 17 on the fourth insulating layer (PDL) 16 corresponding to the position above the anode (anode) 15.

Please refer to Fig. 5 to Fig. 7, embodiment three of the present invention is:

An active matrix driven organic light emitting diode (AMOLED) display device, including the TFT array substrate in Embodiment 1. Its equivalent circuit diagram is shown in FIG. 5 , and a storage capacitor C ₁ is sandwiched between the thin film transistor T1 and the thin film transistor T2 . Both the thin film transistors T1 and T2 are the transistors described in the first embodiment. The thin film transistor T1 is a signal switching transistor, which is used to transmit and cut off the data signal; the thin film transistor _T2 is a driving transistor, which is connected to the organic light emitting diode; the storage capacitor C1 is the first metal layer 2, the auxiliary metal layer 6 and the insulating layer between the two, and the third metal layer 10, the auxiliary metal layer 6 and the insulating layer between the two constitute a double-layer capacitor. Specifically, the gate of the signal switching transistor T1 receives the scanning signal V _gate , the source receives the data signal V _data , and the drain is connected to the gate of the driving transistor T2; the source of the driving transistor T2 is connected to the power supply VDD, and the drain is connected to the anode of the organic light emitting diode; the cathode of the organic light emitting diode is grounded; the storage capacitor _C1 is connected between the drain of the signal switching transistor T1 and the source of the driving transistor T2.

As shown in FIG. 6, it is the layout design layout of the AMOLED display device in this embodiment, which mainly has the following advantages:

1. The VDD wiring of the power supply not only adopts the third metal layer (M3) 10 vertical wiring, but also uses the auxiliary metal layer (M2) 6 horizontal wiring. This design can increase the voltage uniformity of VDD at different positions in the display device, and reduce the VDD impedance and the voltage difference (IR_drop) at different positions;

2. If the first metal layer (M1) 2 or the third metal layer (M3) 10 are used for routing at B in Figure 6, in order to prevent the short circuit caused by the too close distance of the same layer wires, it is necessary to increase the spacing between the same layer wires, which will inevitably increase the width of the layout; and this embodiment adopts the auxiliary metal layer (M2) 6 routing, there is no short circuit problem, and the layout area is reduced;

3. The capacitor C1 in Figure 6 is the first metal layer (M1) 2, the auxiliary metal layer (M2) 6 and the insulating layer between the two, and the third metal layer (M3) 10, the auxiliary metal layer (M2) 6 and the insulating layer between the two to form a double-layer capacitor (as shown in Figure 7). Under the same capacitance, the capacitance area will be reduced by half.

Therefore, under the same display size, the layout design of the AMOLED display device can be more flexible, the pixel distribution density is greatly improved, and the display picture is clearer.

In summary, in the TFT array substrate provided by the present invention, an auxiliary metal layer is added between the first metal layer forming the gate and the third metal layer forming the source and drain, and a double-layer storage capacitor structure is formed between the three metal layers. In this way, the pixel area can be reduced, the PPI of the display panel can be improved, and the flexibility of layout design can be increased while ensuring the storage capacity of the TFT device. The patterning process is completed at the same time, which can save a mask, reduce the exposure, etching and stripping processes of a patterning process, and save the process cost of the TFT array substrate;

The display device provided by the present invention adopts the above-mentioned TFT array substrate. Under the same display size, the pixel distribution density of the display device is greatly improved, and the display screen is clearer.

The above description is only an embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent transformations made by using the description of the present invention and the contents of the drawings, or directly or indirectly used in related technical fields, are all included in the scope of patent protection of the present invention.

Claims (9)

1. A TFT substrate, characterized in that, comprises a first metal layer, an active layer, a third metal layer and an auxiliary metal layer; the first metal layer forms a gate, the third metal layer forms a source and a drain, and the active layer between the source and the drain is a channel region; the third metal layer is located above the first metal layer, and the auxiliary metal layer is located between the first metal layer and the third metal layer, and is separated by an insulating layer between the first metal layer, the third metal layer and the auxiliary metal layer; The insulating layer between the metal layer and the auxiliary metal layer forms a first storage capacitor; the third metal layer, the auxiliary metal layer, and the insulating layer sandwiched between the third metal layer and the auxiliary metal layer form a second storage capacitor; It also includes a substrate, a gate formed of a first metal layer disposed on the substrate, a gate insulating layer disposed on the substrate and the gate, an active layer disposed on the gate insulating layer, an etching barrier layer disposed on the active layer and the gate insulating layer, an auxiliary metal layer disposed on the etching barrier layer, a passivation layer disposed on the etching barrier layer and the auxiliary metal layer, a first via hole and a second via hole passing through the passivation layer and the etching barrier layer and respectively corresponding to the upper sides of the active layer, A third metal layer on the passivation layer, the third metal layer is respectively connected to the active layer through the first via hole and the second via hole; the third metal layer forms a source electrode and a drain electrode at the first via hole and the second via hole respectively; The material of the gate insulating layer is one or two of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. 2. The TFT substrate according to claim 1, further comprising a planarization layer disposed on the source, drain and passivation layer, passing through the planarization layer and corresponding to a third via above the drain, an anode disposed on the planarization layer and connected to the drain through the third via hole, and a fourth insulating layer disposed on the planarization layer and the anode, the fourth insulating layer being provided with a fourth via at a position corresponding to the anode. 3. The TFT substrate according to claim 2, wherein the anode has an ITO/Ag/ITO sandwich structure. 4. The TFT substrate according to claim 1, wherein the active layer is formed of IGZO thin film material. 5. The TFT substrate according to any one of claims 1 to 4, wherein the first metal layer, the auxiliary metal layer and the third metal layer all have a Mo/Al/Mo sandwich layer structure. 6. A display device, characterized in that it comprises the TFT substrate according to any one of claims 1-5. 7. A preparation method for a TFT substrate, comprising the steps of: Step 1: sequentially forming a gate, a gate insulating layer, an active layer and an etching barrier layer on the substrate, the gate being formed by a first metal layer; Step 2: forming an auxiliary metal layer on the etching barrier layer by physical vapor deposition; Step 3: forming a passivation layer on the etching barrier layer and the auxiliary metal layer; Step 4: Simultaneously pattern the passivation layer and the etching barrier layer through a patterning process to form a first via hole and a second via hole connected to the active layer; Step 5: forming a third metal layer on the passivation layer, the third metal layer is connected to the active layer through the first via hole and the second via hole; the third metal layer forms a source electrode and a drain electrode at the first via hole and the second via hole respectively. 8. The preparation method of the TFT substrate according to claim 7, characterized in that, after the step 5, the following steps are also included: forming a planarization layer on the passivation layer, source and drain; performing patterning on the planarization layer to form a third via hole; the third via hole passes through the planarization layer and is connected to the drain; forming an anode on the planarization layer, the anode is connected to the drain through the third via hole; and depositing a fourth insulating layer on the planarization layer and the anode, performing patterning on the fourth insulating layer, and forming a fourth via hole on the fourth insulating layer corresponding to the position above the anode. 9. according to the preparation method of claim 7 or 8 described TFT substrates, it is characterized in that, the step of forming active layer is: deposit IGZO thin film by physical vapor deposition method on gate insulating layer, then form required active layer pattern through exposure, etching and stripping process.