CN101799603A - TFT-LCD (Thin Film Transistor Liquid Crystal Display) array substrate and manufacture method thereof - Google Patents

Abstract

The invention relates to a TFT-LCD array substrate and a manufacturing method thereof. The array substrate includes gate lines and data lines formed on the substrate. Pixel electrodes and thin film transistors are formed in pixel regions defined by the gate lines and data lines. storage electrode. Further, the storage electrode is provided on the same layer as the data line, and the storage electrode is connected to the gate line through a gate insulating layer via hole opened on the gate insulating layer film. The storage electrode segments are arranged above the gate lines on both sides of the data lines. In the present invention, by arranging the storage electrode above the gate line, the storage capacitance per unit area is increased without blocking the pixel area, so the aperture ratio and display brightness are effectively improved, and the display quality is improved as a whole.

Description

TFT-LCD array substrate and manufacturing method thereof

technical field

The invention relates to a thin film transistor liquid crystal display structure and a manufacturing method thereof, in particular to a TFT-LCD array substrate and a manufacturing method thereof.

Background technique

Thin Film Transistor Liquid Crystal Display (TFT-LCD for short) has the characteristics of small size, low power consumption, and no radiation, and occupies a dominant position in the current flat panel display market.

TFT-LCD is mainly composed of an array substrate and a color filter substrate in a box, wherein thin-film transistors and pixel electrodes arranged in a matrix are formed on the array substrate, and each pixel electrode is controlled by a thin-film transistor. When the thin film transistor is turned on, the pixel electrode is charged during the turn-on time, and after the charging is completed, the voltage of the pixel electrode will be maintained until recharging in the next scan. Generally speaking, the liquid crystal capacitance is not large, and the voltage of the pixel electrode cannot be maintained only by the liquid crystal capacitance. Therefore, a storage capacitor is provided in the existing designs to maintain the voltage of the pixel electrode. Usually, the main types of storage capacitors are: storage capacitor on the gate line (Cson Gate), storage capacitor on the common electrode line (Cson Common) and combined structure. The combined structure means that a part of the storage capacitor is on the gate scanning line, and the other A part is on the common electrode line. However, regardless of the type, in the prior art, a gate metal layer film is used as one electrode plate of the storage capacitor, and a gate insulating layer film and a passivation layer film are interposed between the pixel electrode as the other electrode plate of the storage capacitor. It can be seen from the calculation formula of the storage capacitor that the size of the storage capacitor per unit area is inversely proportional to the distance between the two electrode plates, because the gate insulating film and the passivation layer are interposed between the two electrode plates of the storage capacitor in the existing TFT-LCD array substrate. A thin film, the distance between the two electrode plates is relatively large, so the storage capacitance per unit area is relatively small.

Contents of the invention

The object of the present invention is to provide a TFT-LCD array substrate and its manufacturing method, which can not only effectively increase the storage capacitance per unit area, but also have the advantages of high aperture ratio and high display brightness.

In order to achieve the above object, the present invention provides a TFT-LCD array substrate, including gate lines and data lines formed on the substrate, pixel electrodes and thin film transistors are formed in the pixel area defined by the gate lines and data lines, the A storage electrode forming a storage capacitor together with the pixel electrode is formed above the gate line.

The storage electrodes are arranged on the same layer as the data lines.

The storage electrode is connected to the gate line through a gate insulating layer via hole opened on the gate insulating layer film.

The storage electrode segments are arranged above the gate lines on both sides of the data lines.

A shielding strip is also formed in the pixel area, and the shielding strip is arranged on the same layer as the storage electrode and connected to the storage electrode.

In order to achieve the above object, the present invention also provides a method for manufacturing a TFT-LCD array substrate, comprising:

Step 1, depositing a gate metal layer thin film on the substrate, and forming a pattern including a gate line and a gate electrode through a patterning process;

Step 2. Deposit a gate insulating layer film, a semiconductor layer film, and a doped semiconductor layer film on the substrate that has completed step 1, and form a pattern including an active layer and a gate insulating layer via through a patterning process. The gate insulating layer via hole located above the grid line;

Step 3. Deposit a source-drain metal layer thin film on the substrate that completed step 2, and form a pattern including a data line, a source electrode, a drain electrode, a TFT channel region, and a storage electrode through a patterning process, and the storage electrode is located on the data line above the gate lines on both sides, and connected to the gate lines through holes in the gate insulating layer;

Step 4, depositing a passivation layer thin film on the substrate that has completed step 3, and forming a pattern including a passivation layer via hole through a patterning process, and the passivation layer via hole is located above the drain electrode;

Step 5, depositing a transparent conductive film on the substrate completed in step 4, and forming a pattern including a pixel electrode through a patterning process, and the pixel electrode is connected to the drain electrode through the passivation layer via hole.

Said step 2 includes:

A plasma-enhanced chemical vapor deposition method is used to sequentially deposit a gate insulating layer film, a semiconductor layer film and a doped semiconductor layer film;

A half-tone or gray-tone mask is used to form a pattern including an active layer and a gate insulating layer via hole through a patterning process, and the gate insulating layer via hole is located above the gate line.

The forming of the pattern including the via holes in the active layer and the gate insulating layer through a patterning process by using a half-tone or gray-tone mask includes:

Coating a layer of photoresist on the doped semiconductor layer film;

Use a half-tone or gray-tone mask to expose the photoresist to form a photoresist completely removed area, a photoresist completely reserved area, and a photoresist half-retained area; the photoresist fully reserved area corresponds to the area where the active layer pattern is located , the photoresist completely removed area corresponds to the area where the gate insulating layer via hole pattern is located, and the photoresist semi-retained area corresponds to the area other than the above pattern; after the development treatment, the photoresist thickness in the photoresist completely reserved area does not change, The photoresist in the photoresist complete removal area is completely removed, and the photoresist thickness in the photoresist semi-retained area is reduced;

The doped semiconductor layer film, the semiconductor layer film and the gate insulating layer film in the photoresist completely removed region are completely etched away by the first etching process to form a gate insulating layer via hole pattern;

Remove the photoresist in the semi-retained area of the photoresist through an ashing process, exposing the doped semiconductor layer film in this area;

The doped semiconductor layer film and the semiconductor layer film in the semi-retained area of the photoresist are completely etched away by the second etching process to form an active layer pattern;

Strip remaining photoresist.

The step 3 includes: depositing the source-drain metal layer thin film by magnetron sputtering or thermal evaporation, and patterning the source-drain metal layer thin film by using a common mask through a patterning process to form data lines, source electrodes, drain electrodes, and TFTs. A channel region and a storage electrode pattern, wherein the storage electrode is located above the gate line on both sides of the data line, and is connected to the gate line through a via hole in the gate insulating layer.

In the step 3, a pattern of shielding strips is formed at the same time, and the shielding strips are connected to the storage electrodes.

The invention provides a TFT-LCD array substrate and a manufacturing method thereof. The storage electrodes are arranged above the gate lines, and the storage electrodes are arranged on the same layer as the data lines, source electrodes and drain electrodes, and are formed in the same patterning process. The electrode and the pixel electrode form the two electrode plates of the storage capacitor. Compared with the existing storage capacitor structure in which a gate insulating layer film and a passivation layer film are interposed between two electrode plates, the distance between the two electrode plates of the storage capacitor in the present invention is only the thickness of the passivation layer, thus improving the unit area storage capacitor. Since the storage electrode is arranged above the gate line and does not block the pixel area, the invention effectively improves the aperture ratio and display brightness, and improves the display quality as a whole. Further, since the storage electrode of the present invention is arranged above the gate line, an appropriate storage capacitor can be designed by changing the area of the storage electrode according to actual needs, thus ensuring sufficient storage capacitor margin and effectively reducing the jump voltage ΔV _p , to improve display quality.

Description of drawings

Fig. 1 is the plan view of a pixel unit of TFT-LCD array substrate of the present invention;

Fig. 2 is the sectional view of A1-A1 direction in Fig. 1;

Fig. 3 is the sectional view of B1-B1 direction in Fig. 1;

4 is a plan view of a pixel unit after the first patterning process of the TFT-LCD array substrate of the present invention;

Fig. 5 is the sectional view of A2-A2 direction in Fig. 4;

Fig. 6 is the sectional view of B2-B2 in Fig. 4;

7 is a plan view of a pixel unit after the second patterning process of the TFT-LCD array substrate of the present invention;

8 is a cross-sectional view of A3-A3 after exposure and development in the second patterning process of the TFT-LCD array substrate of the present invention;

9 is a cross-sectional view of B3-B3 after exposure and development in the second patterning process of the TFT-LCD array substrate of the present invention;

Fig. 10 is the sectional view of B3-B3 after the first etching process in the second patterning process of the TFT-LCD array substrate of the present invention;

11 is a cross-sectional view of A3-A3 after the ashing process in the second patterning process of the TFT-LCD array substrate of the present invention;

12 is a cross-sectional view of B3-B3 after the ashing process in the second patterning process of the TFT-LCD array substrate of the present invention;

13 is a cross-sectional view of A3-A 3 after the second etching process in the second patterning process of the TFT-LCD array substrate of the present invention;

14 is a cross-sectional view of B3-B3 after the second etching process in the second patterning process of the TFT-LCD array substrate of the present invention;

15 is a sectional view of A3-A3 after the second patterning process of the TFT-LCD array substrate of the present invention;

16 is a plan view of a pixel unit after the third patterning process of the TFT-LCD array substrate of the present invention;

Figure 17 is a sectional view of A4-A4 direction in Figure 16;

Fig. 18 is a sectional view of B4-B4 direction in Fig. 16;

19 is a plan view of a pixel unit after the fourth patterning process of the TFT-LCD array substrate of the present invention;

Figure 20 is a sectional view of A5-A5 direction in Figure 19;

Figure 21 is a sectional view of B5-B5 direction in Figure 19;

Fig. 22 is a flow chart of the manufacturing method of the TFT-LCD array substrate of the present invention;

FIG. 23 is a flow chart of a specific embodiment of the manufacturing method of the TFT-LCD array substrate of the present invention.

Explanation of reference signs:

1-substrate; 2-gate electrode; 3-gate insulating film;

4-semiconductor layer film; 5-doped semiconductor layer film; 6-source electrode;

7-drain electrode; 8-passivation layer film; 9-pixel electrode;

10-gate line; 11-data line; 12-gate insulating layer via hole;

13-storage electrode; 14-passivation layer via; 30-photoresist.

Detailed ways

The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

Fig. 1 is a plan view of a pixel unit of the TFT-LCD array substrate of the present invention, Fig. 2 is a sectional view along A1-A1 in Fig. 1 , and Fig. 3 is a sectional view along B1-B1 in Fig. 1 . As shown in Figures 1 to 3, the main structure of the TFT-LCD array substrate of the present invention includes gate lines 10, data lines 11, pixel electrodes 9, thin film transistors and storage electrodes 13 formed on the substrate 1, and the gate lines perpendicular to each other 10 and the data line 11 define the pixel area, the thin film transistor and the pixel electrode 9 are formed in the pixel area, the gate line 10 is used to provide the turn-on signal to the thin film transistor, the data line 11 is used to provide the data signal to the pixel electrode 9, and the storage electrode 13 It is used to form a storage capacitor together with the pixel electrode 9 . In the present invention, the storage electrode 13 is disposed above the gate line 10 and in the same layer as the data line 11 . Specifically, the TFT-LCD array substrate of the present invention includes a gate line 10 and a gate electrode 2 formed on the substrate 1, and the gate electrode 2 is connected to the gate line 10; a gate insulating layer film 3 is formed on the gate electrode 2 and the gate line 10 and Covering the entire substrate 1, a gate insulating layer via hole 12 is opened on the gate insulating layer film 3, and at least one gate insulating layer via hole 12 is arranged at the position of the gate line 10 for allowing the storage electrode 13 to pass through the gate insulating layer via hole 12 and the gate electrode. The line 10 is connected; the active layer (semiconductor layer film 4 and doped semiconductor layer film 5) is formed on the gate insulating layer film 3 and is positioned above the gate electrode 2; one end of the source electrode 6 is formed on the active layer, and the other end Connect with the data line 11, one end of the drain electrode 7 is formed on the active layer, and the other end is connected with the pixel electrode 9 through the passivation layer via hole 14 offered on the passivation layer film 8, between the source electrode 6 and the drain electrode 7 Form the TFT channel region, the doped semiconductor layer film (ohmic contact layer) 5 in the TFT channel region is completely etched away, exposing the semiconductor layer film 4; the storage electrode 13 and the data line 11, the source electrode 6 and the drain electrode 7 The same layer, and located above the gate line 10, the storage electrode 13 is connected to the gate line 10 through the gate insulating layer via hole 12 opened on the gate insulating layer film 3; the passivation layer film 8 is formed on the data line 11, the source electrode 6, the leakage current On the electrode 7 and the storage electrode 13 and covering the entire substrate 1, a passivation layer via hole 14 connecting the drain electrode 7 to the pixel electrode 9 is opened at the position of the drain electrode 7; the pixel electrode 9 is formed on the passivation layer film 8, and the pixel The electrode 9 is connected to the drain electrode 7 through the passivation layer via hole 14 .

4 to 21 are schematic diagrams of the manufacturing process of the TFT-LCD array substrate of the present invention, which can further illustrate the technical solution of the present invention. In the following description, the patterning process referred to in the present invention includes photoresist coating, masking, exposure , etching and other processes, the photoresist takes positive photoresist as an example.

4 is a plan view of a pixel unit after the first patterning process of the TFT-LCD array substrate of the present invention, FIG. 5 is a cross-sectional view of A2-A2 in FIG. 4 , and FIG. 6 is a cross-sectional view of B2-B2 in FIG. 4 . First, magnetron sputtering or thermal evaporation is used to deposit a gate metal layer film on a substrate 1 (such as a glass substrate or a quartz substrate). The gate metal layer film can be made of Cr, W, Ti, Ta, Mo, Al, Cu, etc. Metals or alloys, composite layer films composed of multiple metal layer films can also be used. A pattern including the gate line 10 and the gate electrode 2 is formed through a patterning process by using a common mask (also called a monotone mask), as shown in FIGS. 4 to 6 .

7 is a plan view of a pixel unit after the second patterning process of the TFT-LCD array substrate of the present invention, and FIG. 8 is a cross-sectional view of A3-A3 direction after exposure and development in the second patterning process of the TFT-LCD array substrate of the present invention. 9 is a cross-sectional view along the B3-B3 direction after exposure and development in the second patterning process of the TFT-LCD array substrate of the present invention. On the substrate with the structural pattern shown in Figure 4, the gate insulating layer film 3, the semiconductor layer film 4 and the doped semiconductor layer film 5 (also known as the ohmic contact layer) are sequentially deposited by using the plasma enhanced chemical vapor deposition (PECVD) method. The gate insulating layer film 3 can be selected from oxide, nitride or oxynitride compound, and the corresponding reaction gas can be a mixed gas of SiH ₄ , NH ₃ , N ₂ or a mixed gas of SiH ₂ Cl ₂ , NH ₃ , N ₂ ; _The reaction _gas corresponding to the thin film 4 can be a mixed gas of _{SiH 4} and H ₂ or a mixed gas of SiH ₂ Cl ₂ and H ₂ ; Mixed gas or mixed gas of SiH ₂ Cl ₂ , PH ₃ , H ₂ . Subsequently, a layer of photoresist 30 is coated on the doped semiconductor layer thin film 5 and exposed with a half-tone or gray-tone mask to make the photoresist form a fully exposed area A, an unexposed area B and a half-exposed area C. The unexposed area B corresponds to the area where the pattern of the active layer is located, the fully exposed area A corresponds to the area where the via hole pattern of the gate insulating layer is located, and the half-exposed area C corresponds to the area other than the above pattern. After the development process, the thickness of the photoresist in the unexposed area B does not change, forming a completely reserved area of photoresist, the photoresist in the fully exposed area A is completely removed, forming a completely removed area of photoresist, and the photoresist in the half-exposed area C is completely removed. The thickness of the resist is reduced to form a semi-retained region of the photoresist, as shown in FIG. 8 and FIG. 9 .

10 is a cross-sectional view along B3-B3 after the first etching process in the second patterning process of the TFT-LCD array substrate of the present invention. The doped semiconductor layer film 5, the semiconductor layer film 4 and the gate insulating layer film 3 in the fully exposed area A are completely etched away by the first etching process to form a gate insulating layer via hole 12 pattern, and the gate insulating layer via hole 12 The gate lines 10 are exposed, as shown in FIG. 10 .

Figure 11 is a sectional view of A3-A3 after the ashing process in the second patterning process of the TFT-LCD array substrate of the present invention, and Figure 12 is a B3-A3 after the ashing process in the second patterning process of the TFT-LCD array substrate of the present invention Sectional view of direction B3. Through the ashing process, the photoresist in the semi-exposed region C is removed, exposing the doped semiconductor layer thin film 5 in this region, as shown in FIG. 11 and FIG. 12 . Since the thickness of the photoresist in the unexposed area B is greater than the thickness of the photoresist in the semi-exposed area C, after the ashing process, the unexposed area B is still coated with a certain thickness of photoresist 30 .

Fig. 13 is a cross-sectional view of A3-A3 after the second etching process in the second patterning process of the TFT-LCD array substrate of the present invention, and Fig. 14 is the second patterning process of the TFT-LCD array substrate of the present invention. Cross-sectional view of B3-B3 direction after etching process. The doped semiconductor layer film 5 and the semiconductor layer film 4 in the semi-exposed region C are completely etched away by the second etching process to form an active layer pattern, the active layer includes the semiconductor layer film 4 and the doped semiconductor layer film 5, As shown in Figure 13 and Figure 14.

FIG. 15 is a cross-sectional view along the A3-A3 direction of the TFT-LCD array substrate of the present invention after the second patterning process. Finally, the remaining photoresist is stripped off to complete the second patterning process of the TFT-LCD array substrate of the present invention, as shown in FIG. 7 , FIG. 14 and FIG. 15 . After the second patterning process of the present invention, the active layer is formed above the gate electrode 2 , and the gate insulating layer via hole 12 is formed above the gate line 10 . The specific shape of the gate insulating layer via hole 12 may also be various, such as square, circular and so on. In practical applications, multiple gate insulating layer via structures may be provided above the gate line 10 , and this embodiment only illustrates the structure using two gate insulating layer via holes.

16 is a plan view of a pixel unit after the third patterning process of the TFT-LCD array substrate of the present invention, FIG. 17 is a sectional view along the A4-A4 direction in FIG. 16 , and FIG. 18 is a sectional view along the B4-B4 direction in FIG. 16 . On the substrate with the structural pattern shown in Figure 7, magnetron sputtering or thermal evaporation is used to deposit the source-drain metal layer thin film. The source-drain metal layer thin film can be made of metals such as Cr, W, Ti, Ta, Mo, Al, Cu, etc. Or an alloy, and a composite layer film composed of a plurality of metal layer films can also be used. Use a common mask to pattern the source-drain metal layer film through a patterning process to form data lines 11, source electrodes 6, drain electrodes 7, TFT channel regions and storage electrodes 13 patterns, wherein one end of the source electrode 6 is located on the active layer. , the other end is connected to the data line 11, one end of the drain electrode 7 is located on the active layer, and is set opposite to the source electrode 6, a TFT channel region is formed between the source electrode 6 and the drain electrode 7, and the TFT channel region between The doped semiconductor layer film 5 is completely etched away, and part of the thickness of the semiconductor layer film 4 is etched away, exposing the semiconductor layer film 4; the storage electrode 13 is arranged on both sides of the data line 11 in segments, and is located at the gate line 10 Above, it is connected to the gate line 10 through the via hole 12 in the gate insulating layer, as shown in FIG. 16 , FIG. 17 and FIG. 18 . In practical application, this patterning process can also form a shielding strip structure at the same time, and the shielding strip is used to further shield the light in the light leakage area. Further, the shielding strip can also be connected with the storage electrode as a whole. The shape and size of the storage electrode 13 can be designed according to actual needs.

19 is a plan view of a pixel unit after the fourth patterning process of the TFT-LCD array substrate of the present invention, FIG. 20 is a sectional view along the A5-A5 direction in FIG. 19 , and FIG. 21 is a sectional view along the B5-B5 direction in FIG. 19 . On the substrate with the structural pattern shown in Figure 16, a passivation layer film 8 is deposited by PECVD. The passivation layer film 8 can be oxide, nitride or oxynitride compound, and the corresponding reaction gas can be a mixed gas of SiH ₄ , NH ₃ , N ₂ or a mixed gas of SiH ₂ Cl ₂ , NH ₃ , N ₂ . The passivation layer film 8 is patterned by a patterning process using a common mask to form a passivation layer via hole 14, which is located above the drain electrode 7, as shown in FIG. 19 , FIG. 20 and FIG. 21 . In this patterning process, patterns such as gate line interface vias in the gate line interface area (gate line PAD) and data line interface vias in the data line interface area (data line PAD) are also formed at the same time. The above-mentioned process of forming gate line interface via holes and data line interface via hole patterns through the patterning process has been widely used in the current patterning process, and will not be repeated here.

Finally, on the substrate with the above-mentioned structural patterns, magnetron sputtering or thermal evaporation is used to deposit a transparent conductive film. The transparent conductive film can be made of indium tin oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide. Materials, other metals and metal oxides can also be used. The pixel electrode 9 is formed through a patterning process by using a common mask, and the pixel electrode 9 is connected to the drain electrode 7 through the passivation layer via hole 14, as shown in FIGS. 1-3 .

The five-time patterning process described above is only one implementation method for preparing the TFT-LCD array substrate of the present invention. In actual use, the present invention can also be realized by increasing or decreasing the number of patterning processes and selecting different materials or combinations of materials. For example, the second patterning process of the TFT-LCD array substrate of the present invention can be completed by the second patterning process using a common mask, that is, the active layer pattern is formed by a patterning process using a common mask once, and the patterning of the active layer is formed by a patterning process using a common mask once. The patterning process forms gate insulating layer via holes, which will not be repeated here.

The invention provides a TFT-LCD array substrate. The storage electrode is arranged above the gate line, and the storage electrode is arranged on the same layer as the data line, source electrode and drain electrode, and is formed in the same patterning process. The storage electrode and the pixel electrode The two electrode plates that form the storage capacitor. Compared with the existing storage capacitor structure in which a gate insulating layer film and a passivation layer film are sandwiched between two electrode plates, the distance between the two electrode plates of the storage capacitor in the present invention is only the thickness of the passivation layer film, thus improving the storage capacitor per unit area. Since the storage electrode is arranged above the gate line and does not block the pixel area, the invention effectively improves the aperture ratio and display brightness, and improves the display quality as a whole.

When the TFT-LCD is working, due to the parasitic capacitance between the source electrode and the gate electrode, and between the drain electrode and the gate electrode, a jump voltage ΔV _p will be generated at the moment when the charging of the pixel electrode ends. The expression of the jump voltage for: Among them, V _gh is the turn-on voltage of the gate electrode, V _gl is the turn-off voltage of the gate electrode, C _lc is the liquid crystal capacitance, C _gs is the parasitic capacitance, and C _s is the storage capacitance. Studies have shown that the existence of the jump voltage ΔV _p will change the polarity of the pixel electrode, which will lead to the inconsistency of the voltage difference between positive and negative polarities, resulting in flicker phenomenon in the display screen, which seriously affects the display quality. Therefore, the design The smaller the jump voltage ΔV _p required to be generated, the better. Since the storage electrode of the present invention is arranged above the gate line, a suitable storage capacitor C _s can be designed by changing the area of the storage electrode according to actual needs, thus ensuring sufficient storage capacitor margin and effectively reducing the jump voltage ΔV _p , to improve display quality.

Fig. 22 is a flow chart of the manufacturing method of the TFT-LCD array substrate of the present invention, including:

Step 1, depositing a gate metal layer thin film on the substrate, and forming a pattern including a gate line and a gate electrode through a patterning process;

Step 2. Deposit a gate insulating layer film, a semiconductor layer film, and a doped semiconductor layer film on the substrate that has completed step 1, and form a pattern including an active layer and a gate insulating layer via through a patterning process. The gate insulating layer via hole located above the grid line;

Step 3. Deposit a source-drain metal layer thin film on the substrate that completed step 2, and form a pattern including a data line, a source electrode, a drain electrode, a TFT channel region, and a storage electrode through a patterning process, and the storage electrode is located on the data line above the gate lines on both sides, and connected to the gate lines through holes in the gate insulating layer;

Step 4, depositing a passivation layer thin film on the substrate that has completed step 3, and forming a pattern including a passivation layer via hole through a patterning process, and the passivation layer via hole is located above the drain electrode;

Step 5, depositing a transparent conductive film on the substrate completed in step 4, and forming a pattern including a pixel electrode through a patterning process, and the pixel electrode is connected to the drain electrode through the passivation layer via hole.

In the above technical solution of the present invention, since the storage electrode is arranged above the gate line, and the storage electrode is arranged on the same layer as the drain electrode, the source electrode and the data line, the storage capacitance per unit area is increased. Since the storage electrode is arranged above the gate line and does not block the pixel area, the invention effectively improves the aperture ratio and display brightness, and improves the display quality as a whole.

Fig. 23 is a flowchart of a specific embodiment of the method for manufacturing a TFT-LCD array substrate according to the present invention. In the technical solution shown in Fig. 22, the step 2 includes:

Step 11, using a plasma enhanced chemical vapor deposition method, sequentially depositing a gate insulating layer film, a semiconductor layer film and a doped semiconductor layer film on the substrate that has completed step 1;

Step 12, coating a layer of photoresist on the doped semiconductor layer film;

Step 13: Exposing the photoresist with a half-tone or gray-tone mask to form a photoresist completely removed area, a photoresist completely reserved area, and a photoresist half-retained area; the photoresist completely reserved area corresponds to the active layer The area where the pattern is located, the area where the photoresist is completely removed corresponds to the area where the via hole pattern of the gate insulating layer is located, and the semi-retained area of the photoresist corresponds to the area other than the above pattern; after the development treatment, the thickness of the photoresist in the area where the photoresist is completely retained No change, the photoresist in the photoresist completely removed area is completely removed, and the photoresist thickness in the photoresist semi-retained area is reduced;

Step 14, completely etching away the doped semiconductor layer film, semiconductor layer film and gate insulating layer film in the photoresist completely removed region by the first etching process to form a gate insulating layer via hole pattern;

Step 15, removing the photoresist in the semi-retained area of the photoresist by an ashing process, exposing the doped semiconductor layer film in this area;

Step 16, completely etching away the doped semiconductor layer film and the semiconductor layer film in the semi-retained area of the photoresist by a second etching process to form an active layer pattern;

Step 17, stripping off the remaining photoresist.

This embodiment is a technical solution for simultaneously forming the active layer and the gate insulating layer through a patterning process using a multi-step etching process. The preparation process has been introduced in detail in the technical solutions shown in Figures 7-15 above , which will not be repeated here.

In actual use, step 2 of the TFT-LCD array substrate manufacturing method of the present invention can be completed by a patterning process using a common mask plate twice, that is, the active layer pattern is formed by a patterning process using a common mask plate once, and the active layer pattern is formed by using a common mask plate once. The template patterning process forms gate insulating layer via holes.

In step 1 of the present invention, at first adopt the method for magnetron sputtering or thermal evaporation, on the substrate (such as glass substrate or quartz substrate) deposition gate metal layer thin film, gate metal layer thin film can adopt Cr, W, Ti, Ta, Mo , Al, Cu and other metals or alloys, and a composite layer film composed of multiple metal layer films can also be used. A pattern including gate lines and gate electrodes is formed through a patterning process using a common mask.

In step 3 of the present invention, adopt the method for magnetron sputtering or thermal evaporation, deposit source-drain metal layer film, source-drain metal layer film can adopt metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, also A composite layer film composed of a plurality of metal layer films may be used. Use a common mask to pattern the source-drain metal layer film through a patterning process to form data lines, source electrodes, drain electrodes, TFT channel regions, and storage electrode patterns. One end of the source electrode is located on the active layer, and the other end is connected to the data line. Wire connection, one end of the drain electrode is located on the active layer, opposite to the source electrode, a TFT channel region is formed between the source electrode and the drain electrode, and the doped semiconductor layer film between the TFT channel region is completely etched away , and etch away part of the thickness of the semiconductor layer film to expose the semiconductor layer film; the storage electrode is located above the gate line on both sides of the data line, and is connected to the gate line through a gate insulating layer via hole. In practical applications, this patterning process can also form a pattern of shielding strips at the same time, and the shielding strips are used to further shield the light in the light leakage area. Further, the shielding strips can also be connected with the storage electrodes as a whole. The shape and size of the storage electrode can be designed according to actual needs.

In step 4 of the present invention, the passivation layer film is deposited by PECVD method. The passivation layer film can be oxide, nitride or oxynitride compound, and the corresponding reaction gas can be a mixed gas of SiH ₄ , NH ₃ , N ₂ or a mixed gas of SiH ₂ Cl ₂ , NH ₃ , N ₂ . The passivation layer film is patterned through a patterning process by using a common mask to form a passivation layer via hole, wherein the passivation layer via hole is located above the drain electrode. In this patterning process, patterns such as gate line interface via holes in the gate line interface area and data line interface via holes in the data line interface area are also formed at the same time. The above-mentioned process of forming gate line interface via holes and data line interface via hole patterns through a patterning process has been widely used in current patterning processes.

In step 5 of the present invention, adopt the method for magnetron sputtering or thermal evaporation, deposit transparent conductive film, transparent conductive film can adopt materials such as indium tin oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide, also can adopt Other metals and metal oxides. A common mask is used to form a pixel electrode through a patterning process, and the pixel electrode is connected to the drain electrode through a passivation layer via hole.

Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present invention without limitation, although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be Modifications or equivalent replacements can be made without departing from the spirit and scope of the technical solutions of the present invention.

Claims (10)

1. A TFT-LCD array substrate, comprising gate lines and data lines formed on the substrate, forming pixel electrodes and thin film transistors in the pixel area defined by the gate lines and data lines, characterized in that the gate lines A storage electrode forming a storage capacitor together with the pixel electrode is formed above. 2. The TFT-LCD array substrate according to claim 1, wherein the storage electrode and the data line are arranged in the same layer. 3. The TFT-LCD array substrate according to claim 1, wherein the storage electrode is connected to the gate line through a gate insulating layer via hole opened on the gate insulating layer film. 4. The TFT-LCD array substrate according to claim 3, wherein the storage electrode segments are arranged above the gate lines on both sides of the data lines. 5. The TFT-LCD array substrate according to claim 1, wherein a shading strip is also formed in the pixel region, and the shading strip is arranged on the same layer as the storage electrode and connected to the storage electrode . 6. A method for manufacturing a TFT-LCD array substrate, comprising: Step 1, depositing a gate metal layer thin film on the substrate, and forming a pattern including a gate line and a gate electrode through a patterning process; Step 2. Deposit a gate insulating layer film, a semiconductor layer film, and a doped semiconductor layer film on the substrate that has completed step 1, and form a pattern including an active layer and a gate insulating layer via through a patterning process. The gate insulating layer via hole located above the grid line; Step 3. Deposit a source-drain metal layer thin film on the substrate that completed step 2, and form a pattern including a data line, a source electrode, a drain electrode, a TFT channel region, and a storage electrode through a patterning process, and the storage electrode is located on the data line above the gate lines on both sides, and connected to the gate lines through holes in the gate insulating layer; Step 4, depositing a passivation layer thin film on the substrate that has completed step 3, and forming a pattern including a passivation layer via hole through a patterning process, and the passivation layer via hole is located above the drain electrode; Step 5, depositing a transparent conductive film on the substrate completed in step 4, and forming a pattern including a pixel electrode through a patterning process, and the pixel electrode is connected to the drain electrode through the passivation layer via hole. 7. The TFT-LCD array substrate manufacturing method according to claim 6, wherein said step 2 comprises: A plasma-enhanced chemical vapor deposition method is used to sequentially deposit a gate insulating layer film, a semiconductor layer film and a doped semiconductor layer film; A half-tone or gray-tone mask is used to form a pattern including an active layer and a gate insulating layer via hole through a patterning process, and the gate insulating layer via hole is located above the gate line. 8. The method for manufacturing a TFT-LCD array substrate according to claim 7, wherein said forming a pattern comprising active layer and gate insulating layer vias through a patterning process using a halftone or gray tone mask comprises: Coating a layer of photoresist on the doped semiconductor layer film; Use a half-tone or gray-tone mask to expose the photoresist to form a photoresist completely removed area, a photoresist completely reserved area, and a photoresist half-retained area; the photoresist fully reserved area corresponds to the area where the active layer pattern is located , the photoresist completely removed area corresponds to the area where the gate insulating layer via hole pattern is located, and the photoresist semi-retained area corresponds to the area other than the above pattern; after the development treatment, the photoresist thickness in the photoresist completely reserved area does not change, The photoresist in the photoresist complete removal area is completely removed, and the photoresist thickness in the photoresist semi-retained area is reduced; The doped semiconductor layer film, the semiconductor layer film and the gate insulating layer film in the photoresist completely removed region are completely etched away by the first etching process to form a gate insulating layer via hole pattern; Remove the photoresist in the semi-retained area of the photoresist through an ashing process, exposing the doped semiconductor layer film in this area; The doped semiconductor layer film and the semiconductor layer film in the semi-retained area of the photoresist are completely etched away by the second etching process to form an active layer pattern; Strip remaining photoresist. 9. The method for manufacturing a TFT-LCD array substrate according to claim 6, wherein said step 3 comprises: depositing a source-drain metal layer thin film by magnetron sputtering or thermal evaporation, and patterning by using a common mask The process patterns the source-drain metal layer thin film to form data lines, source electrodes, drain electrodes, TFT channel regions, and storage electrode patterns. The storage electrodes are located above the gate lines on both sides of the data lines, and are connected to each other through the gate insulating layer via holes. Grid connection. 10 . The method for manufacturing a TFT-LCD array substrate according to claim 6 , wherein in step 3, a pattern of shielding strips is formed at the same time, and the shielding strips are connected to the storage electrodes. 11 .

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