CN113141182B - Analog-to-digital converter device and capacitance weight correction method - Google Patents

Abstract

The analog-to-digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes a plurality of first capacitors, a capacitor to be calibrated, and a plurality of compensation capacitors. The digital logic circuit performs a correction procedure on the capacitor to be calibrated to correct the weight value of the capacitor to be calibrated according to a decision signal, and converts the input signal into a plurality of bits through the capacitor array after executing the correction procedure. The comparator circuit compares the test signal generated by the plurality of first capacitors and the capacitor to be calibrated in response to the correction procedure with a predetermined voltage to generate the decision signal. The digital logic circuit further selects at least one of the plurality of compensation capacitors according to the weight value to adjust the digital code corresponding to the corrected weight value to an integer that conforms to the expression of the plurality of bits.

Description

Analog-to-digital converter device and capacitance weight correction method

Technical Field

The present application relates to analog-to-digital converters, and more particularly, to a successive approximation register-based analog-to-digital converter with capacitance weight correction.

Background technique

Analog-to-digital converters have been widely used in various electronic devices to generate digital signals for subsequent signal processing. In the prior art, various correction mechanisms are used to improve the resolution of analog-to-digital converters. For example, the correction mechanism is used to correct the digital weight corresponding to the capacitor or current source to generate a corresponding digital code. However, in the above technology, if the digital code is not a value that can be expressed by the expected number of bits of the analog-to-digital converter, the resolution of the analog-to-digital converter will be reduced. If the number of bits of the analog-to-digital converter is increased in order to express the digital code, the circuit cost will increase significantly.

Summary of the invention

In some embodiments, the analog-to-digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes a plurality of first capacitors, a capacitor to be calibrated, and a plurality of compensation capacitors. The digital logic circuit is used to perform a correction procedure on the capacitor to be calibrated to correct the weight value of the capacitor to be calibrated according to a decision signal, and convert the input signal into a plurality of bits through the capacitor array after executing the correction procedure. The comparator circuit is used to compare the test signal generated by the plurality of first capacitors and the capacitor to be calibrated in response to the correction procedure with a predetermined voltage to generate the decision signal. The digital logic circuit is further used to select at least one of the plurality of compensation capacitors according to the weight value to adjust a digital code corresponding to the corrected weight value to an integer that conforms to the expression of the plurality of bits.

In some embodiments, a capacitor weight correction method includes the following operations: executing a calibration procedure on a capacitor to be calibrated of an analog-to-digital converter device to calibrate a weight value of the capacitor to be calibrated according to a decision signal, wherein the analog-to-digital converter device converts an input signal into multiple bits; comparing multiple first capacitors of the analog-to-digital converter device with a test signal and a predetermined voltage generated by the capacitor to be calibrated in response to the calibration procedure to generate the decision signal; and selecting at least one of multiple compensation capacitors according to the weight value to adjust a digital code corresponding to the corrected weight value to an integer that conforms to the expression of the multiple bits.

The features, implementation and effects of the present application will be described in detail as follows with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram showing an analog-to-digital converter device according to some embodiments of the present application;

FIG2 is a schematic diagram showing the compensation capacitor unit in FIG1 according to some embodiments of the present application; and

FIG. 3 is a flow chart showing a capacitance weight correction method according to some embodiments of the present application.

Comply with the description:

100 Analog-to-digital converter device

110 Capacitor Array

112 Least Significant Capacitor Unit

114 Most significant bit capacitor unit

116 Compensation capacitor unit

118A, 118B Switching Circuit

120 Comparator Circuit

130 Digital Logic Circuits

C ₀ ～C _n-1 capacitance

CD Dummy Capacitor

D ₀ ～D _n-1

DOUT digital code

S1 switch

_SC1 , _SC2 control signal

S _D decision signal

S _T test signal

VCM Predetermined voltage

VIN Input Signal

VREF1, VREF2 reference voltage

C,2C,4C,8C,2n-1C Capacitance

0.25C, 0.125C, 0.0625C Capacitance

300 Capacitance Weight Correction Method

S310, S320, S330 Operation

S311, S312, S313 Steps

Detailed ways

All words used herein have their usual meanings. The above words are applicable to the definitions in commonly used dictionaries. The use examples of any word discussed herein included in the content of this application are only illustrative and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

As used herein, “coupled” or “connected” may refer to two or more components being in direct physical or electrical contact with each other, or being in indirect physical or electrical contact with each other, or may refer to two or more components operating or moving with each other.

As used herein, the term "circuit" may be a device that is connected in a certain manner by at least one transistor and/or at least one active and passive component to process a signal. As used herein, the term "and/or" includes any combination of one or more of the listed associated items.

In this document, the terms "first", "second", "third", etc. are used to describe and distinguish various components. Therefore, the first component in this document may also be referred to as the second component without departing from the original meaning of this application.

For ease of understanding, similar components in the various drawings will be designated by the same reference numerals.

1 is a schematic diagram showing an analog-to-digital converter (ADC) device 100 according to some embodiments of the present application. In some embodiments, the ADC device 100 is a successive approximation register (SAR) ADC.

The ADC device 100 includes a capacitor array 110, a comparator circuit 120, and a digital logic circuit 130. In general operation, one end of the capacitor array 110 receives a predetermined voltage VCM (or common mode voltage) through a switch S1, and the other end of the capacitor array 110 samples an input signal VIN. The digital logic circuit 130 can control the capacitor array 110 according to a decision signal _SD output by the comparator circuit 120. In this way, the capacitor array 110 and the comparator circuit 120 work together to convert the sampled input signal VIN into n bits D ₀ ～D _n-1 . n is a positive integer, and the n bits D ₀ ～D _n-1 can define a digital code DOUT. For example, if n is 5, the digital code DOUT can be any integer from 0 to 31 (i.e., 00000 to 11111).

Before performing the above conversion, the digital logic circuit 130 performs a calibration procedure to calibrate the weight values of the capacitors to be calibrated in the capacitor array 110. After performing the calibration procedure, the digital logic circuit 130 performs the above conversion via the capacitor array 110. In some embodiments, the calibration procedure is called foreground calibration.

The capacitor array 110 includes a least significant bit (LSB) capacitor unit 112, a most significant bit (MSB) capacitor unit 114, a compensation capacitor unit 116, a switching circuit 118A and a switching circuit 118B. The LSB capacitor unit 112 includes a dummy capacitor _CD and a plurality of capacitors _C0 - _C2 . The MSB capacitor unit 114 includes a plurality of capacitors _C3 -Cn _-1 , which are capacitors to be calibrated. The smallest of the LSB capacitor units 112 are the dummy capacitor _CD- and the capacitor _C0 , and the capacitance of each of the two capacitors is set to a unit capacitor C. The capacitance of the plurality of capacitors _C1 -Cn _-1- is sequentially set to 2 times (i.e., the preset weight value of the capacitor _C1 ) of the unit capacitor C (i.e., 2C), 4 times of the unit capacitor C (i.e., 4C), ..., to ^2n-1 times of the unit capacitor C (i.e., ^2n-1C ). In the calibration process, the digital logic circuit 130 obtains the weight value of a capacitor to be calibrated (e.g., capacitor _C3 ) through the LSB capacitor unit 112. The compensation capacitor unit 116 adjusts the weight value of the capacitor to be calibrated based on the control of the digital logic circuit 130. An exemplary configuration of the compensation capacitor unit 116 can be referred to the example of FIG. 2 described below.

The switching circuit 118A includes a plurality of switches for selectively transmitting the input signal VIN, the reference voltage VREF1 or the voltage VREF2 (e.g., a ground voltage or a negative reference voltage) to the dummy capacitor _CD and the plurality of capacitors _C0 to Cn _-1 according to the plurality of control signals SC1 generated by the digital logic circuit 130. The switching circuit 118B includes a plurality of switches for selectively coupling at least one compensation capacitor in the compensation capacitor unit 116 in parallel to the corresponding capacitor to _be calibrated (e.g., capacitor _C3 ) according to the plurality of control signals _SC2 generated by the digital logic circuit 130, so as to adjust the digital code corresponding to the calibrated weight value of the capacitor to be calibrated to an integer that can be expressed by the bits _D0 to _Dn-1 . The above-mentioned calibration procedure and the operation of adjusting the weight value will be described later with reference to FIG. 3.

FIG. 2 is a schematic diagram showing the compensation capacitor unit 116 in FIG. 1 according to some embodiments of the present application. The compensation capacitor unit 116 includes a plurality of compensation capacitors, such as a plurality of compensation capacitors with a capacitance of 0.25C, a plurality of compensation capacitors with a capacitance of 0.125C, and a plurality of compensation capacitors with a capacitance of 0.0625C. In some embodiments, the capacitance of the plurality of compensation capacitors is set to be less than or equal to 0.25 times the unit capacitance C, but the present application is not limited thereto. These compensation capacitors are selectively coupled in parallel to the capacitor to be calibrated in the MSB capacitor unit 114 through the switching circuit 118B.

FIG3 is a flow chart showing a capacitance weight correction method 300 according to some embodiments of the present application. In some embodiments, the capacitance weight correction method 300 may be executed by the digital logic circuit 130 of FIG1. In some embodiments, the digital logic circuit 130 may be implemented by a digital circuit, a state machine, and/or a logic circuit that executes the capacitance weight correction method 300, but the present application is not limited thereto.

In operation S310, a calibration procedure is performed on the capacitor to be calibrated to calibrate the weight value of the capacitor to be calibrated. In operation S320, it is determined whether the digital code corresponding to the calibrated weight value conforms to the integer that can be expressed by multiple bits generated by the ADC device. If not, operation S330 is performed. If so, the compensation capacitor is not selected and the capacitor weight correction method 300 is stopped. In some embodiments, in operation S320, after determining that the digital code corresponding to the calibrated weight value conforms to the integer that can be expressed by multiple bits generated by the ADC device, operation S311 can be performed again to calibrate another capacitor to be calibrated.

The capacitor _C3 is taken as an example to be calibrated. The predetermined voltage VCM is set to half of the reference voltage VREF1, and the capacitance of the capacitor _C3 should ideally be the same as the sum of the capacitances of the LSB capacitor units 112 (i.e., C+C+2C+4C=8C). The test signal _ST is a divided voltage generated by the LSB capacitor unit 112 and the capacitor _C3 according to the reference voltage VREF1. Before calibration, the digital logic circuit 130 outputs a plurality of control signals _SC1- to control the capacitor _C3 to receive the reference voltage VREF1 through the switching circuit 118A, and to control the dummy capacitor _CD and the plurality of capacitors _C0 - _C2 to receive the reference voltage VREF2. During the initial calibration, the digital logic circuit 130 switches the corresponding one of the plurality of control signals _SC1 to control the capacitor _C3 to receive the reference voltage VREF1 to receive the reference voltage VREF2 through the switching circuit 118A, so as to generate the test signal _ST (step S311). Under this condition, the test signal _ST should ideally be half of the reference voltage VREF1. If the weight value of the capacitor _C3 has an error (i.e., _C3 is not equal to 8C), the test signal _ST will be different from half of the reference voltage VREF1. By comparing the test signal _ST with the predetermined voltage VCM, the comparator circuit 120 can output a corresponding decision signal _SD (step S312). In the next calibration, the digital logic circuit 130 changes a corresponding one of the plurality of control signals _SC1 in response to the decision signal _SD , so that the capacitor _C2- switches from receiving the reference voltage VREF2 to receiving the reference voltage VREF1 (step S311). In this way, the test signal _ST will change, so the comparator circuit 120 generates a new decision signal _SD again (step S312). Similarly, when the digital logic circuit 130 detects that the decision signal _SD toggles between logic value 1 and logic value 0, the digital logic circuit 130 may average the control signals _SC1 triggering the above switching situations to calculate the weight value of the capacitor _C3 (step S313).

The digital logic circuit 130 calculates the error between the weight value and the preset weight value of the capacitor C ₃ to correct the weight value. For example, if the effective number of bits (ENOB) of the ADC device 100 is 11 (i.e., n=11), the ADC device 100 is expected to generate 11 bits D ₀ ～D ₁₀ . Under the setting of the binary system, the preset weight value of the capacitor C ₃ is 8 (i.e., the capacitor C 3 should ideally be 8C), and the digital code corresponding to the capacitor C ₃ before correction is 16 (in terms of differential signal). If the weight value of the capacitor C ₃ is 7, the digital logic circuit 130 can correct the weight value of the capacitor C ₃ according to the error between the default weight value and the weight value. According to the corrected weight value, the digital code corresponding to the capacitor C ₃ is 14, and the digital code 14 is an integer that can be expressed by the 11 bits D ₀ ～D _10. Under this condition, the digital logic circuit 130 stops the correction process (or continues to correct the next capacitor to be corrected). Similarly, if the weight value of capacitor _C3 is 8.5, the digital code corresponding to capacitor _C3 according to the calibrated weight value is 17, and the digital code 17 is an integer that can be expressed by 11 bits _D0 - _D10 . Under this condition, the digital logic circuit 130 can stop the calibration process (or continue to calibrate the next capacitor to be calibrated).

The above-mentioned weight calibration operation is for example only, and the present application is not limited thereto. In some embodiments, the digital logic circuit 130 may store the error and the corrected weight value as a lookup table to facilitate subsequent analog-to-digital conversion. In some embodiments, the detailed operation of the above-mentioned weight calibration may refer to the relevant literature (A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS, Symp. VLSI Circuits, June 2015.).

In some cases, the digital code corresponding to the weight value of capacitor C ₃ is not an integer that can be expressed by 11 bits D ₀ ~ D _10. In this case, the ENOB of the ADC device 100 will be reduced. For example, if the weight value of capacitor C ₃ is calculated to be 8.25, the digital code corresponding to the weight value of capacitor C ₃ is 16.5, which is not an integer that can be expressed by 11 bits D ₀ ~ D _10. In this way, the digital logic circuit 130 will determine that the digital code that capacitor C ₃ may correspond to is 16 or 17. If this weight value is not adjusted, the ENOB will be reduced from 11 bits to 10.5 bits. Under this condition, the digital logic circuit 130 will perform operation S330 to adjust this weight value.

Continuing to refer to FIG. 3 , in operation S330 , at least one of the compensation capacitors is selected according to the weight value of the capacitor to be calibrated to adjust the weight value of the capacitor to be calibrated. In the above example, the weight value of capacitor C ₃ is 8.25. The digital logic circuit 130 can output a plurality of control signals S _C2 to select at least one compensation capacitor from the compensation capacitor unit 116 via the switching circuit 118B, and couple the at least one compensation capacitor in parallel with capacitor C ₃ to correct the weight value of capacitor C _3. In this example, the digital logic circuit 130 can select a compensation capacitor with a capacitance of 0.25C to correct the weight value of capacitor C ₃ from 8.25 to 8.5. Thus, according to the corrected weight value, the digital code corresponding to capacitor C ₃ is 17, which can be an integer that can be expressed by 11 bits D ₀ to D ₁₀ .

Through the above operation, the digital logic circuit 130 can determine whether the digital code corresponding to the corrected weight value is an integer that can be expressed by 11 bits. If not, the digital logic circuit 130 can further use the compensation capacitor to correct the weight value to correct the digital code to an integer that can be expressed by 11 bits. In this way, the effective number of bits of the ADC device 100 can be avoided from being reduced. Under the setting of the binary system, the value less than 1 and greater than 0 in the weight value of the capacitor to be calibrated is y. If y is less than 0.5, the digital logic circuit 130 will use the compensation capacitor to correct y to 0.5 (for example, 8.25 is corrected to 8.5, where 8.25 is the weight value and y is 0.25). If y is greater than 0.5, the digital logic circuit 130 will use the compensation capacitor to correct the weight value to the positive integer closest to this weight value (for example, 8.625 is corrected to 9, where 8.625 is the weight value and y is 0.625).

In some related technologies, in order to express the above digital code 16.5, the ENOB of the ADC device can be increased by 1 bit. However, if the ENOB of the ADC device is increased, the cost of the back-end circuit for processing the output of the ADC device will be greatly increased. Compared with the above technology, the ADC device 100 in some embodiments of the present application can correct the weight value through the compensation capacitor unit 116 so that the digital code is corrected to an integer that can be expressed by the original bit. In this way, the ENOB of the ADC device 100 can be maintained at the original value, so the cost of the back-end circuit will not be increased.

The number of circuits and/or the number of bits in the above-mentioned diagrams are only used for examples. According to different actual needs, the number of circuits (such as capacitors) and/or the number of bits used in each diagram can be adjusted accordingly. The above examples are illustrated by using binary system, but the present application is not limited to this. In some embodiments, the ADC device 100 and the capacitor weight correction method 300 can also be applied to non-binary operations.

In summary, the ADC device and capacitance weight correction method provided in some embodiments of the present application can use the compensation capacitor to correct the weight value of the capacitance to be calibrated without affecting the original resolution of the ADC device and without increasing the cost of the back-end circuit.

Although the embodiments of the present application are described above, these multiple embodiments are not intended to limit the present application. A person having ordinary knowledge in the technical field may make changes to the technical features of the present application based on the explicit or implicit contents of the present application. All such changes may fall within the scope of patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be based on the scope defined in the claims of this specification.

Claims (10)

1. An analog-to-digital converter apparatus, characterized in that the analog-to-digital converter apparatus comprises:

The capacitor array comprises a plurality of first capacitors, a plurality of capacitors to be calibrated and a plurality of compensation capacitors;

The digital logic circuit is used for executing a correction program on the capacitor to be corrected so as to correct the weight value of the capacitor to be corrected according to a decision signal, and converting an input signal into a plurality of bits through the capacitor array after executing the correction program; and

A comparator circuit for comparing the test signals generated by the first capacitors and the capacitors to be calibrated in response to the calibration procedure with a predetermined voltage to generate the decision signal,

Wherein the digital logic circuit is further configured to select at least one of the plurality of compensation capacitors according to the weight value to adjust a digital code corresponding to the corrected weight value to an integer conforming to the plurality of bit expressions.

2. The analog-to-digital converter device of claim 1, wherein the digital logic circuit is configured to output a plurality of first control signals according to the decision signal to control the capacitor to be calibrated to switch from receiving a first reference voltage to receiving a second reference voltage, and to sequentially control the plurality of first capacitors to switch from receiving the second reference voltage to receiving the first reference voltage to generate the test signal.

3. The analog-to-digital converter apparatus of claim 2, wherein the digital logic circuit is configured to average the plurality of first control signals according to the decision signal to calculate the weight value and to confirm whether the digital code meets the integer to select the at least one of the plurality of compensation capacitances.

4. The analog-to-digital converter device of claim 3, wherein if the weight value does not match the integer, the digital logic circuit is configured to output a second plurality of control signals to control the at least one of the plurality of compensation capacitors to be coupled in parallel to the capacitor to be calibrated.

5. The analog-to-digital converter device according to claim 1, wherein a smallest of the plurality of first capacitances is a unit capacitance, and the plurality of compensation capacitances are each set to be less than or equal to 0.25 times the unit capacitance.

6. The analog-to-digital converter device of claim 1, wherein if the weight value is less than 1 and the value greater than 0 is less than 0.5, the digital logic circuit is configured to select the at least one of the plurality of compensation capacitors to adjust the value to 0.5.

7. The analog-to-digital converter device of claim 1, wherein if the weight value is less than 1 and greater than 0 is greater than 0.5, the digital logic circuit is configured to select the at least one of the plurality of compensation capacitors to adjust the weight value to the nearest positive integer.

8. A method of capacitance weight correction, the method comprising:

Executing a correction program on a capacitor to be corrected of an analog-digital converter device to correct a weight value of the capacitor to be corrected according to a decision signal, wherein the analog-digital converter device converts an input signal into a plurality of bits;

Comparing a plurality of first capacitances of the analog-to-digital converter device with a test signal generated by the capacitance to be calibrated in response to the calibration procedure with a predetermined voltage to generate the decision signal; and

At least one of a plurality of compensation capacitors is selected according to the weight value, so that the digital code corresponding to the corrected weight value is adjusted to be an integer conforming to the expression of the plurality of bits.

9. The capacitance weight correction method of claim 8, wherein selecting the at least one of the plurality of compensation capacitances according to the weight value comprises:

if the value of the weight value is less than 1 and the value of the weight value greater than 0 is less than 0.5, selecting at least one of the plurality of compensation capacitors to adjust the value to 0.5.

10. The capacitance weight correction method of claim 8, wherein selecting the at least one of the plurality of compensation capacitances according to the weight value comprises:

And if the value of the weight value smaller than 1 and larger than 0 is larger than 0.5, selecting at least one of the compensation capacitors to adjust the weight value to a positive integer closest to the weight value.