CN109428595B - Continuous approximation analog-to-digital conversion correcting device - Google Patents
Continuous approximation analog-to-digital conversion correcting device Download PDFInfo
- Publication number
- CN109428595B CN109428595B CN201710717605.6A CN201710717605A CN109428595B CN 109428595 B CN109428595 B CN 109428595B CN 201710717605 A CN201710717605 A CN 201710717605A CN 109428595 B CN109428595 B CN 109428595B
- Authority
- CN
- China
- Prior art keywords
- digital
- capacitor
- comparison
- output
- comparison result
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1023—Offset correction
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a continuous approximation type analog-to-digital conversion correcting device which can correct a digital output. One embodiment of the calibration apparatus includes a successive approximation register analog-to-digital converter (SAR ADC) and a digital circuit. The SAR ADC is used to generate a digital output. The digital circuit corrects the digital output according to a predetermined correction when the digital output matches a metastable state output. The metastable state output is associated with a metastable state binary comparison sequence, the metastable state binary comparison sequence comprises K continuous comparison results, the K comparison results sequentially comprise a first comparison result, a second comparison result and M continuous comparison results, the first comparison result is the same as the second comparison result, the M comparison results are the same, and the first comparison result is different from each of the M comparison results. Thereby solving the meta-stable problem with low complexity and low power consumption.
Description
Technical Field
The present invention relates to a calibration device, and more particularly, to a calibration device for analog-to-digital conversion.
Background
In recent years, the architecture of successive approximation register analog-to-digital converter (SAR ADC) has been widely used due to lower complexity and better power consumption performance. However, the operation of the SAR ADC is closely related to the output of the comparator, and the comparator may output an erroneous comparison result due to the two input signals being too close, which may further cause the subsequent comparison result to be erroneous and the output result of the SAR ADC to deviate from the correct result excessively, which is generally referred to as the SAR ADC having metastability.
To solve the metastable state problem of the SAR ADC, the prior art provides the following two solutions:
(1) a timer is used to determine whether the comparison time of the comparator is too long, so as to determine whether the two input signals being compared are too close to each other and a metastable state occurs. The above solutions have a problem of limited application. This solution can be found in the following documents: akira Shikata, Student members, IEEE, Ryota Sekimoto, Student members, IEEE, Tadahiro Kuroda, Fellow, IEEE, and Hiroki Ishikuro, members, IEEE, "A0.5V 1.1MS/sec 6.3fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40nm CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.47, NO.4, APRIL 2012.
(2) Adjusting the decision state transition point of the comparator output and adjusting the decision state transition point of the bit value input by the digital-to-analog converter of the SAR ADC. The above solution has the problem that it cannot constitute a closed loop correction. This solution can be found in the following documents: Hyeok-Ki Hong, Student Member, IEEE, Wan Kim, Student Member, IEEE, Hyun-Wook Kang, Sun-Jae Park, Michael Choi, Ho-Jin Park, and Seung-Tak Ryu, Senior Member, IEEE, "A Decision-Error-Tolerant 45nm CMOS 7b 1GS/s Nonbinry 2b/Cycle SAR ADC", IEEE JOURNAL OF SOLID-STATISTE CUITS, VOL.50, NO.2, FERRURY 2015.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a successive approximation analog-to-digital conversion calibration apparatus to solve the metastable state problem.
The invention discloses a successive approximation register analog-to-digital converter (SAR ADC) correction device, which can correct a digital output. The SAR ADC is used to generate a digital output. The digital circuit is used for judging whether the digital output accords with a metastable state output or not, and correcting the digital output according to a preset correction when the digital output accords with the metastable state output, wherein the metastable state output is associated with a metastable state binary comparison sequence, the metastable state binary comparison sequence comprises continuous K comparison results (such as 110000 or 001111), the K comparison results sequentially comprise a first comparison result, a second comparison result which is continuous with the first comparison result and continuous M comparison results which are continuous with the second comparison result, the first comparison result is the same as the second comparison result, the first comparison result and the second comparison result are different from each of the M comparison results, and each of the K and the M is an integer which is not less than 1.
The features, operation and function of the present invention will be described in detail with reference to the drawings.
Drawings
FIG. 1 shows an example of all possible output values of a digital-to-analog converter in a successive approximation register analog-to-digital converter on a time axis;
FIG. 2 shows a sample input value to the SAR ADC of FIG. 1 for comparison;
FIG. 3 shows a sample input value to the SAR ADC of FIG. 1 for comparison;
FIG. 4 shows an embodiment of the successive approximation analog-to-digital conversion correction apparatus of the present invention; and
FIG. 5 shows an embodiment of the SAR ADC of FIG. 4.
[ simple description of symbols in the drawings ]
400 successive approximation analog-to-digital conversion correcting device
410 successive approximation register analog-to-digital converter (SAR ADC)
412 first input circuit
414 second input circuit
416 comparator
418 control circuit
420 digital circuit
Positive side signal of Vip differential signal
Negative terminal signal of Vin differential signal
V1 first input signal
V2 second input signal
Detailed Description
FIG. 1 shows a digital-to-analog converter (SAR ADC) in a successive approximation register analog-to-digital converter (SAR ADC)All possible output values (V) of a digital-to-analog converter (DAC) on a time axis (t)DAC(LSB)) in units of Least Significant Bit (LSB) size of the DAC, the DAC being a 5-bit DAC, the first output value being an intermediate value of 24LSB is 16 LSB; the second time output value of the DAC is 16LSB + -23LSB; the third secondary output value of the DAC is + -22LSB; the fourth output value of the DAC is + -21LSB; the fifth output value of the DAC is + -20LSB。
Fig. 2 is a schematic diagram showing a sample input value of 24.9LSB input to the SAR ADC of fig. 1 for 5 comparisons, where the light solid line represents the unused output value in the above comparison. As can be seen from fig. 2, in the first comparison, the first input value 16LSB of the DAC is much smaller than the sampling input value 24.9LSB, so the second output value (16LSB +8LSB is 24LSB) outputted by the DAC according to the first comparison result normally approaches the sampling input value; next, since the difference between the second output value 24LSB of the DAC and the sampled input value 24.9LSB is very small, if the comparator of the SAR ADC cannot correctly compare the size of the second output value, the third output value outputted by the DAC according to the second comparison result may be 24LSB +4LSB equal to 28LSB (as shown by the dashed line in fig. 2) or 24LSB-4LSB equal to 20LSB (as shown by the dotted line in fig. 2); if the results of the subsequent comparison operations are correct, the results of the 5 comparisons are, in order, 00111 (as indicated by the solid black line and the dashed line in FIG. 2) or 01000 (as indicated by the solid black line and the dotted line in FIG. 2), where 0 indicates that the input value of the DAC is smaller than the sampled input value, 1 indicates that the input value of the DAC is larger than the sampled input value, and the meanings indicated by 0 and 1 are interchanged according to the requirement. Whether the comparison result of the SAR ADC is 00111 or 01000, we can deduce that the difference between the third output value (28LSB or 20LSB) of the DAC and the sampled input value (24.9LSB) is greater than the extent to which the subsequent output value of the DAC can approach the sampled input value, which results in the last comparison result being 1 or 0, so we can determine that the second output value of the DAC is likely to be close to the sampled input value, and thus determine that the second comparison result of the DAC is likely to be wrong (or that the second comparison operation of the DAC is likely to be metastable), i.e., the output of the SAR ADC is likely to be a metastable output (metastable).
Fig. 3 also shows a schematic diagram of a sampled input value (24.9LSB) input to the SAR ADC of fig. 1 for comparison, where the light solid line represents the unused output value in the comparison. In comparison with fig. 2, fig. 3 shows that the third comparison is incorrect, which may be caused by the abnormal operation of the second comparison, and in detail, the SAR ADC outputs the incorrect comparison result in the third comparison because the second output value of the DAC is relatively close to the sampling input value. The comparison result of fig. 3 may be 00011 (as shown by the solid black line and the dashed line in fig. 3) or 01100 (as shown by the solid black line and the dotted line in fig. 3), and the difference between any of the comparison results of fig. 3 and the correct comparison result 00111 is greater than that of any of the comparison results of fig. 2 and the correct comparison result, so that the comparison result of fig. 3 needs to be corrected. As can be seen from fig. 3, whether the comparison result of the SAR ADC is 00011 or 01100, the second comparison result is the same as the third comparison result, but different from each comparison result after the third comparison result, the pattern feature of the comparison result can be used to determine whether the comparison result of the SAR ADC needs to be corrected.
Based on the above-mentioned research, the present invention discloses a calibration apparatus for successive approximation analog-to-digital conversion to adaptively calibrate the digital output of a SAR ADC. An embodiment of the calibration apparatus of the present invention is shown in fig. 4, and the calibration apparatus 400 of fig. 4 comprises a SAR ADC410 and a digital circuit 420. The SAR ADC410 is configured to generate at least one digital output, which may be a sequence (e.g., a binary sequence) and/or a value (e.g., a decimal value). In this embodiment, the SAR ADC410 includes: a first input circuit 412 for generating a first input signal V1 according to a positive side signal Vip of a differential signal; a second input circuit 414 for generating a second input signal V2 according to a negative terminal signal Vin of the differential signal; a comparator 416 forComparing the first input signal V1 with the second input signal V2 to generate a comparison result; and a control circuit 418 for generating a portion of the digital output according to the comparison result, the control circuit 418 further generating control signals according to the comparison result to control the charge redistribution operation of the first input circuit 412 and the second input circuit 414, respectively, so as to update the first input signal V1 and the second input signal V2 for the comparator 416 to perform the next comparison, the operation of the SAR ADC410 is well known in the art, and the details are omitted here. Digital circuit 420 is configured to determine whether the digital output matches a metastable output and correct the digital output according to a predetermined correction when the digital output matches the metastable output, wherein the metastable output is associated with a metastable binary comparison sequence (e.g., (1) any one of the comparison results of fig. 3, each of K and M is an integer not less than 1. In one embodiment, a last comparison result of the M comparison results is used to determine a value of a Least Significant Bit (LSB) of SAR ADC 410; in one embodiment, M is not less than 2; in one embodiment, if SAR ADC410 is an N-bit ADC,
not less than 25%.
As mentioned above, in an embodiment, the digital output is a binary sequence, and when the digital output is the output of the comparison result of the SAR ADC410, the digital circuit 420 determines whether the pattern of the binary sequence (pattern) is the same as the pattern of the metastable binary comparison sequence, so as to determine whether the digital output conforms to the metastable state output, and at this time, the predetermined modification may be a predetermined binary sequence (or predetermined X sequence values, where X is a positive integer not greater than K), and the digital circuit 420 replaces/modifies the binary sequence of the digital output with the predetermined modification (or replaces/modifies X sequence values of the binary sequence of the digital output, for example, the last K sequence values when X is K), so as to achieve the correction. In another embodiment, the digital output is a binary sequence, and when the digital output is the output of the analog-to-digital conversion result of the SAR ADC410, the digital circuit 420 determines whether the pattern of the binary sequence is the same as the pattern of a digital output sequence corresponding to the metastable binary comparison sequence, so as to determine whether the digital output matches the metastable output, where the predetermined modification may be a predetermined binary sequence (or predetermined X sequence values, where X is a positive integer not greater than K), and the digital circuit 420 replaces/modifies the binary sequence of the digital output with the predetermined modification (or replaces/modifies X sequence values of the binary sequence of the digital output, for example, the last K sequence values when X ═ K) to achieve the correction. In another embodiment, the digital output is a decimal value, the digital circuit 420 determines whether the decimal value is the same as a metastable decimal value corresponding to the metastable binary comparison sequence, or determines whether the binary sequence pattern corresponding to the decimal value of the digital output is the same as the metastable binary comparison sequence pattern (or the digital output sequence pattern corresponding to the metastable binary comparison sequence), so as to determine whether the digital output matches the metastable output, where the predetermined modification may be a predetermined decimal value, and the digital circuit 420 replaces the decimal value of the digital output with the predetermined modification to achieve the correction.
It is noted that a specific correction (i.e., the predetermined correction) corresponding to a specific metastable binary comparison sequence can be known in advance by theory and/or implementation, so that a specific digital output of the SAR ADC410 can be corrected by the specific correction. For example, the erroneous comparison result 00011 of fig. 3 is a metastable binary comparison sequence corresponding to a binary digital output 11101 (i.e., the analog-to-digital conversion result of SAR ADC410, corresponding to decimal value 29), whereas the correct comparison result 00111 (shown in fig. 2) corresponds to another binary digital output 11001 (i.e., the analog-to-digital conversion result of SAR ADC410, corresponding to decimal value 25), so that when the digital output generated by SAR ADC410 is the comparison result, if digital circuit 420 finds that the digital output of SAR ADC410 conforms to pattern 00011, digital circuit 420 may replace the digital output of SAR ADC410 with a predetermined correction 00111. For another example, when the digital output generated by SAR ADC410 is the output of the analog-to-digital conversion result, if digital circuit 420 finds that the digital output of SAR ADC410 conforms to pattern 11101 (or decimal value 29), digital circuit 420 may replace the digital output of SAR ADC410 (i.e., binary sequence 11101 or decimal value 29) with a predetermined modification 11001 (or decimal value 25). The details are omitted herein because the determination of the sequence/value comparison and the modification/substitution of the sequence/value can be achieved by the prior art.
In one case, the digital circuit 420 determines that a digital output of the SAR ADC410 matches a metastable output, but the digital output is relatively close to the actual sampled input value (e.g., the analog-to-digital conversion result corresponding to the comparison result 01000 of fig. 2 is 10111 (i.e., the decimal value 23), which is relatively close to the actual sampled input value 24.9), in order to avoid mistaking the correct digital output as the metastable output or performing the unnecessary correction, an embodiment of the present invention may further add a redundant capacitor in a capacitor array of the SAR ADC410, so as to perform a redundant charge redistribution operation by the redundant capacitor after finishing the normal multiple comparison operations and obtaining the comparison result (e.g., the comparison result 01000 of fig. 2), and then perform a redundant comparison operation to generate a redundant comparison result, since the redundant charge redistribution operation would cause the original analog-to-digital conversion result, approaching the actual sampled input value by a predetermined margin (e.g., when the original conversion result 10111 (i.e., decimal value 23) is less than the actual sampled input value, the redundant charge redistribution operation equivalently adds 00110 (i.e., decimal value 6) to the original conversion result 10111 (i.e., decimal value 23), when the original conversion result is greater than the actual sampled input value, the redundant charge redistribution operation equivalently subtracts 00110 (i.e., decimal value 6) from the original conversion result), if the redundant comparison result is the same as the last comparison result of the normal comparison operation of SAR ADC410, this indicates that the difference between the original conversion result and the actual sampled input value exceeds the predetermined margin, and therefore, correction is required; if the redundant comparison result is different from the last comparison result of the normal comparison operation of SAR ADC410, this indicates that the original conversion result is within the predetermined range of the actual sampled input value, and therefore, no correction is needed. In one embodiment, the capacitor array of SAR ADC410 includes a Least Significant Bit (LSB) capacitor and the redundant capacitor having a capacitance greater than the capacitance of the LSB capacitor, e.g., six times the capacitance of the LSB capacitor.
As mentioned earlier, with the addition of this redundancy capacitance, one embodiment of SAR ADC410 is shown in fig. 5. The SAR ADC410 of fig. 5 includes: a first capacitor array 510 for sampling a positive side signal Vip of a differential signal and outputting a first input signal V1, the first capacitor array 510 comprising capacitors C1, C2, C3, C4, …, and a redundant capacitor CRThe redundant capacitor CRThe charge redistribution operation and the redundancy comparison operation for realizing the redundancy are carried out; a first switch circuit 520 for controlling a coupling relationship between the first capacitor array 510 and a reference voltage Vref (or a high voltage) and a ground voltage GND (or a low voltage) according to a first control signal, thereby achieving charge redistribution and controlling the magnitude of the first input signal V1; a second capacitor array 530 for sampling a negative terminal signal Vin of the differential signal and outputting a second input signal V2, the second capacitor array 530 comprising capacitors C1, C2, C3, C4, …, and a redundant capacitor CRThe redundant capacitor CRThe charge redistribution operation and the redundancy comparison operation for realizing the redundancy are carried out; a second switch circuit 540 for controlling a coupling relationship between the second capacitor array 530 and the reference voltage Vref (or the high voltage) and the ground voltage GND (or the low voltage) according to a second control signal, thereby implementingCharge redistribution and control of the magnitude of the second input signal V2; a comparator 550 for comparing the first input signal V1 with the second input signal V2 to output a comparison result; and a control circuit 560 for generating the first control signal and the second control signal according to the comparison result and outputting at least a portion of the digital output. Please note that the operation logic of the SAR ADC410 of fig. 5 is similar to that of the general SAR ADC, and the SAR ADC410 of fig. 5 only performs the redundant charge redistribution operation and the redundant comparison operation, which are the same as those of the general SAR ADC, and therefore, the operation details of the SAR ADC410 are omitted here; one of ordinary skill in the art can further understand the SAR ADC410 of fig. 5 by the following references: hongda Xu1,Yongda Cai1,Ling Du2,Yuan Zhou3,Benwei Xu3,Datao Gong4,Jingbo Ye4,Yun Chiu3,“A 78.5dB-SNDR Radiation and Metastability-Tolerant Two-Step Split SAR ADC Operating up to 75MS/s with24.9mW Power Consumption in 65nm CMOS”,ISSCC 2017/SESSION 28/HYBRID ADCs/28.6.(1University of Texas at Dallas,Richardson,TX；2University of Electronic Science and Technology of China,Chengdu,China；3Broadcom,Irvine,CA；4Southern Methodist University Dallas,TX)。
The capacitors of a capacitor array of a conventional SAR ADC typically include 2C, 4C, 8C, 16C …, where C is the capacitance of a unit capacitor, and the size of the unit capacitor is determined by the implementation, and the ratio of the capacitance of any two capacitors in the capacitors is a power of 2 or a power of 2. The SAR ADC410 of the present invention may employ the above-mentioned capacitor array to perform normal comparison operations (e.g., the capacitors C1, C2, C3, and C4 … of fig. 5, which are sequentially 2C, 4C, 8C, and 16C …), however, to improve the accuracy of the digital output of the SAR ADC410, in one embodiment, the capacitor array of the SAR ADC410 may comprise redundant capacitors for normal comparison operations (i.e., comparison operations other than the above-mentioned redundant comparison operations), for example, the capacitors C1, C2, C3, and C4 … of fig. 5, which are sequentially 3C, 4C, 7C, and 13C ….
As mentioned in the disclosure, the digital circuit 420 determines whether the digital output matches the meta-state output according to K consecutive comparison results of the binary comparison sequence for the meta-state, wherein the K comparison results sequentially include the first comparison result, the second comparison result, and the M consecutive comparison results. In one embodiment, the K consecutive comparison results relate to redistribution of charges of K capacitors in a capacitor array of SAR ADC410, the K capacitors having different capacitance values, and the K capacitors (e.g., 13C, 7C, 4C, 3C; or 32C, 24C, 16C, 8C, 4C, 2C) include a first capacitor, a second capacitor and M capacitors, wherein the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor, a capacitance value ratio of the first capacitor to the second capacitor is not equal to a power of 2, and the capacitance value of the second capacitor is less than a sum of the capacitance values of the M capacitors, which can help ensure correctness of the determination of digital circuit 420 when digital circuit 420 determines that the digital output corresponds to the metastable output.
It should be noted that although the input signals of the SAR ADC410 of fig. 4 and 5 are illustrated as differential signals, the present invention is not limited thereto, and those skilled in the art can understand that the present invention can be applied to the processing of single-ended signals according to the present disclosure and the related art. It should be noted that, when the implementation is possible, a person skilled in the art can selectively implement some or all of the technical features of any of the above embodiments, or selectively implement a combination of some or all of the technical features of the above embodiments, thereby increasing the flexibility in implementing the invention.
In summary, the present invention can effectively solve the metastable state problem of the SAR ADC with low complexity and low power consumption.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can apply variations to the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.
Description of the symbols
VDAC(LSB) output size of digital-to-analog converter (in units of size of least significant bit)
time t
400 successive approximation analog-to-digital conversion correcting device
410 successive approximation register analog-to-digital converter (SAR ADC)
412 first input circuit
414 second input circuit
416 comparator
418 control circuit
420 digital circuit
Positive side signal of Vip differential signal
Negative terminal signal of Vin differential signal
V1 first input signal
V2 second input signal
510 first capacitor array
520 first switch circuit
530 second capacitor array
540 second switching circuit
550 comparator
560 control circuit
C1, C2, C3 and C4 capacitors
CRRedundant capacitor
Vref reference voltage
GND ground voltage.
Claims (10)
1. A successive approximation analog-to-digital conversion correction device capable of correcting a digital output, the successive approximation analog-to-digital conversion correction device comprising:
a successive approximation register analog-to-digital converter for generating the digital output; and
a digital circuit for determining whether the digital output meets a metastable state output and correcting the digital output according to a preset correction when the digital output meets the metastable state output, wherein the preset correction is a specific correction corresponding to the metastable state output known in advance by theory and/or implementation,
the metastability output is associated with a metastability binary comparison sequence, the metastability binary comparison sequence includes K consecutive comparison results, the K comparison results sequentially include a first comparison result, a second comparison result following the first comparison result, and M consecutive comparison results following the second comparison result, the first comparison result is the same as the second comparison result, the M comparison results are the same, the first comparison result and the second comparison result are different from each of the M comparison results, and each of K and M is an integer not less than 1.
2. The successive approximation analog-to-digital conversion correction device of claim 1, wherein M is not less than 2.
3. The apparatus of claim 1, wherein the successive approximation register adc performs a plurality of comparisons to generate the digital output, the successive approximation register adc further performs a redundancy comparison to generate a redundancy comparison result after performing the plurality of comparisons, and the digital circuit further determines whether the digital output matches the meta-stable output after the redundancy comparison result is the same as a final comparison result of the plurality of comparisons.
4. The apparatus of claim 3, wherein the successive approximation register analog-to-digital converter comprises a capacitor array having a least significant bit capacitor and a redundancy capacitor, the capacitance of the redundancy capacitor is greater than the capacitance of the least significant bit capacitor, the successive approximation register analog-to-digital converter utilizes the redundancy capacitor to perform a redundant charge redistribution operation, and then performs the redundant comparison operation to generate the redundant comparison result.
5. The apparatus of claim 3, wherein the successive approximation register analog-to-digital converter comprises a capacitor array comprising K capacitors with different capacitance values, the K capacitors comprising a first capacitor, a second capacitor and M capacitors, a capacitance ratio of the first capacitor to the second capacitor being not equal to a power of 2, the capacitance value of the first capacitor being greater than the capacitance value of the second capacitor.
6. The successive approximation analog-to-digital conversion correction device of claim 5, wherein the sum of the capacitance values of the M capacitors is smaller than the capacitance value of the second capacitor.
7. The apparatus of claim 1, wherein the successive approximation register analog-to-digital converter comprises a capacitor array comprising K capacitors with different capacitance values, the K capacitors comprising a first capacitor, a second capacitor and M capacitors, a capacitance ratio of the first capacitor to the second capacitor being not equal to a power of 2, the capacitance value of the first capacitor being greater than the capacitance value of the second capacitor.
8. The successive approximation analog-to-digital conversion correction device of claim 7, wherein the sum of the capacitance values of the M capacitors is smaller than the capacitance value of the second capacitor.
9. The apparatus of claim 1, wherein the digital output is a binary bit sequence, and the digital circuit determines whether the digital output matches the metastable output by one of: judging whether the pattern of the binary bit sequence is the same as the pattern of the metastable binary comparison sequence; and judging whether the pattern of the binary bit sequence is the same as the pattern of a digital output sequence corresponding to the metastable binary comparison sequence.
10. The successive approximation analog-to-digital conversion correction device of claim 1, wherein the digital output is a decimal value, and the digital circuit determines whether the decimal value is the same as a metastable decimal value corresponding to the metastable binary comparison sequence, thereby determining whether the digital output matches the metastable output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710717605.6A CN109428595B (en) | 2017-08-21 | 2017-08-21 | Continuous approximation analog-to-digital conversion correcting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710717605.6A CN109428595B (en) | 2017-08-21 | 2017-08-21 | Continuous approximation analog-to-digital conversion correcting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109428595A CN109428595A (en) | 2019-03-05 |
| CN109428595B true CN109428595B (en) | 2022-06-24 |
Family
ID=65498839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710717605.6A Active CN109428595B (en) | 2017-08-21 | 2017-08-21 | Continuous approximation analog-to-digital conversion correcting device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109428595B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110071723A (en) * | 2019-04-29 | 2019-07-30 | 电子科技大学 | A kind of pseudo- common mode switch method for gradual approaching A/D converter |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486806B1 (en) * | 1999-09-09 | 2002-11-26 | Cirrus Logic, Inc. | Systems and methods for adaptive auto-calibration of Radix<2 A/D SAR converters with internally generated stimuli |
| KR101309837B1 (en) * | 2010-03-16 | 2013-09-23 | 한국전자통신연구원 | Successive approximation register analog-digital converter and method for operating the same |
| TWI514777B (en) * | 2012-08-03 | 2015-12-21 | Realtek Semiconductor Corp | Predictive successive-approximation-register converting device and method therefor |
| US8922415B2 (en) * | 2012-08-10 | 2014-12-30 | Maxlinear, Inc. | Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) |
| US8872691B1 (en) * | 2013-05-03 | 2014-10-28 | Keysight Technologies, Inc. | Metastability detection and correction in analog to digital converter |
| US8957802B1 (en) * | 2013-09-13 | 2015-02-17 | Cadence Design Systems, Inc. | Metastability error detection and correction system and method for successive approximation analog-to-digital converters |
| ITMI20132037A1 (en) * | 2013-12-06 | 2015-06-07 | St Microelectronics Int Nv | METHOD FOR THE CORRECTION OF DIGITAL ERRORS FOR BINARY DIGITAL ANALOGUE CONVERTER WITH SUCCESSIVE APPROXIMATIONS. |
| CN104242934B (en) * | 2014-08-29 | 2017-12-29 | 成都锐成芯微科技有限责任公司 | The disparate step SAR ADC metastable state and eliminate circuits of band redundant digit and method |
| CN106817131B (en) * | 2015-11-30 | 2020-05-08 | 复旦大学 | High-speed assembly line-successive approximation type ADC based on dynamic ringing operational amplifier |
| CN106817128B (en) * | 2015-12-01 | 2020-07-10 | 瑞昱半导体股份有限公司 | Method for self-adaptive regulating coding mode and its digital correcting circuit |
| US9484945B1 (en) * | 2016-05-05 | 2016-11-01 | Hong Kong Applied Science and Technology Research Institute Company, Limited | Asynchronous successive-approximation-register analog-to-digital converter (SAR ADC) in synchronized system |
-
2017
- 2017-08-21 CN CN201710717605.6A patent/CN109428595B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109428595A (en) | 2019-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI653836B (en) | Correcting device of successive approximation analog-to-digital conversion | |
| US9071265B1 (en) | Successive approximation analog-to-digital converter with linearity error correction | |
| US8378863B2 (en) | Analog-to-digital converter and correction method thereof | |
| EP3090488B1 (en) | Combining a coarse adc and a sar adc | |
| US8223044B2 (en) | INL correction circuitry and method for SAR ADC | |
| TWI454064B (en) | Successive approximation analog-to-digital converter having auxiliary prediction circuit and method thereof | |
| US8599059B1 (en) | Successive approximation register analog-digital converter and method for operating the same | |
| CN104639164B (en) | Binary capacitor array and its redundancy calibration method applied to single-ended SAR ADC | |
| TWI591969B (en) | Calibration circuit and calibration method for DAC | |
| CN105322966B (en) | Improve the capacitors exchange and averaging method of the gradually-appoximant analog-digital converter linearity | |
| CN111565042B (en) | Correction method suitable for two-step ADC | |
| TWI736103B (en) | Analog to digital converter device and capacitor weight calibration method | |
| TWI698091B (en) | Successive approximation register analog-to-digital converter and operation method thereof | |
| CN104467846B (en) | A kind of adaptive electric charge redistribution analog-digital converter, conversion method and calibration method | |
| US10084465B2 (en) | Analog-to-digital converters with a plurality of comparators | |
| CN112838866B (en) | Calibration logic control circuit and method, and successive approximation type analog-to-digital converter | |
| WO2019084085A1 (en) | Method and apparatus for enabling wide input common-mode range in sar adcs with no additional active circuitry | |
| CN109428595B (en) | Continuous approximation analog-to-digital conversion correcting device | |
| US10574248B2 (en) | Successive approximation register analog-to-digital converter and associated control method | |
| CN104467847B (en) | The adaptive electric charge of redundancy redistributes the calibration method of analog-digital converter | |
| EP2388922B1 (en) | Method and circuit for encoding and transmitting numerical values from an analog-to-digital conversion process | |
| US12136931B2 (en) | Semiconductor device, analog-to-digital converter and analog-to-digital converting method | |
| TW202114357A (en) | Analog to digital converter device and noise shaping digital slope analog to digital converter circuitry | |
| TWI777464B (en) | Signal converting apparatus and signal converting method | |
| CN106817128B (en) | Method for self-adaptive regulating coding mode and its digital correcting circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |