CN113130649A

CN113130649A - LDMOS device and preparation method thereof

Info

Publication number: CN113130649A
Application number: CN201911418179.1A
Authority: CN
Inventors: 李佳豪; 金华俊
Original assignee: CSMC Technologies Fab2 Co Ltd
Current assignee: CSMC Technologies Fab2 Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2021-07-16
Also published as: WO2021135265A1

Abstract

The invention relates to an LDMOS device, which comprises: a substrate; a drift region, located in the substrate; a plurality of trenches arranged at intervals, located in the drift region; a plurality of metal field plates, respectively located in each trench ; The isolation dielectric layer is at least located between the metal field plate and the inner wall of the trench. The spaced trenches enable the metal field plate to penetrate deeply into the drift region effectively, thereby forming a multi-dimensional depletion effect. At the same time, the drift region between the spaced trenches retains the carriers on the surface of the drift region. In the channel, the carriers of the LDMOS device basically flow along the surface of the drift region. Compared with the carriers bypassing the trench along the sidewall and the bottom wall of the trench, the movement path of the carriers is shorter. , which can effectively reduce the on-resistance of the LDMOS device.

Description

LDMOS device and preparation method thereof

Technical Field

The invention relates to the field of semiconductors, in particular to an LDMOS device and a preparation method thereof.

Background

With the rapid development of power integrated circuits, research and development of power semiconductor devices are becoming more and more important, for LDMOS (laterally diffused metal oxide semiconductor) devices, in order to improve the depletion capability of the drift region of an LDMOS device, in the existing LDMOS device, a trench is generally dug in the drift region and a metal aperture field plate is formed in the trench, and the metal field plate and a source electrode are interconnected to realize the depletion effect on the drift region of the LDMOS device, thereby forming a multi-dimensional depletion effect. However, since the distance of carriers flowing from the source to the drain is increased due to the introduction of the trench structure in the above scheme, the on-resistance (Ron) is also increased, and the magnitude of the decrease in the on-resistance of the LDMOS is limited.

Disclosure of Invention

Therefore, it is necessary to provide an LDMOS device and a method for manufacturing the same, aiming at the problem that the reduction of the on-resistance of the LDMOS is limited.

An LDMOS device comprising:

a substrate;

a drift region located within the substrate;

the grooves are arranged at intervals and are positioned in the drift region;

the metal field plates are respectively positioned in the grooves;

and the isolation dielectric layer is at least positioned between the metal field plate and the inner wall of the groove.

According to the technical scheme, the metal field plate can effectively penetrate into the drift region through the grooves arranged at intervals, so that a multi-dimensional depletion effect is formed, meanwhile, as the drift region between the grooves arranged at intervals reserves a carrier channel on the surface of the drift region, carriers of the LDMOS device basically flow along the surface of the drift region, compared with the situation that the carriers bypass the grooves along the side walls and the bottom walls of the grooves, the movement path of the carriers is shorter, and the on-resistance of the LDMOS device can be effectively reduced.

In one embodiment, the metal field plate is made of tungsten silicon compound.

In one embodiment, the metal field plate includes a pillar structure.

In one embodiment, the trench is a shallow trench.

In one embodiment, the method further comprises the following steps:

a gate located on the drift region;

the gate oxide layer is positioned between the grid and the drift region;

the body region is positioned in the drift region, and the grid electrode is spanned above the drift region and the body region;

the source electrode is positioned in the body region and positioned on one side of the grid electrode;

the drain electrode is positioned in the drift region and positioned on one side of the grid electrode, which is far away from the source electrode;

the trench and the metal field plate are located between the gate and the drain with a spacing from both the gate and the drain.

In one embodiment, a plurality of the trenches are arranged at intervals along the extending direction of the gate.

In one embodiment, a plurality of the trenches are arranged in a column along the extending direction of the gate.

In one embodiment, the semiconductor device further comprises an interconnect structure electrically connecting the source electrode with the metal field plate.

The invention also provides a preparation method of the LDMOS device, which is characterized by comprising the following steps of:

providing a substrate;

forming a plurality of grooves which are arranged at intervals in the substrate, wherein isolation medium layers are filled in the grooves; forming a drift region in the substrate, wherein the grooves are distributed in the drift region;

and respectively forming a metal field plate in each groove, wherein the isolation dielectric layer is at least positioned between the metal field plate and the inner wall of the groove.

In one embodiment, the forming a drift region in the substrate, after the trenches are distributed in the drift region, forming a metal field plate in each trench, and before the isolating dielectric layer is at least located between the metal field plate and the inner wall of the trench, further includes:

forming a body region in the drift region;

forming a gate oxide layer on the substrate, wherein the gate oxide layer covers the drift region and the body region;

forming a grid electrode on the surface of the gate oxide layer, wherein the grid electrode is arranged above the drift region and the body region in a spanning mode;

forming a source electrode in the body region and forming a drain electrode in the drift region; the source electrode is positioned on one side of the grid electrode, which is far away from the metal field plate, and the drain electrode is positioned on one side of the groove, which is far away from the grid electrode.

In one embodiment, a source is formed in the body region and a drain is formed in the drift region; the source electrode is positioned on one side of the grid electrode far away from the metal field plate, and the drain electrode is positioned behind one side of the groove far away from the grid electrode, and the method further comprises the following steps: forming an interconnect structure electrically connecting the metal field plate with the source electrode.

Drawings

FIG. 1 is a flow chart illustrating a method for fabricating an LDMOS device according to an embodiment of the present invention;

FIG. 2 is a flow chart showing a method for fabricating an LDMOS device according to another embodiment of the present invention;

FIG. 3 is a flow chart illustrating a method for fabricating an LDMOS device according to another embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view of a substrate after provision of a substrate in accordance with an embodiment of the present invention;

FIG. 5 is a cross-sectional view of a trench after being formed according to an embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view of a layer of isolation dielectric material after deposition in accordance with one embodiment of the present invention;

FIG. 7 is a cross-sectional view of the substrate with the dielectric material layer removed according to one embodiment of the present invention;

fig. 8 is a schematic cross-sectional view of a drift region and a body region after forming an embodiment of the invention;

FIG. 9 is a schematic cross-sectional view of a gate oxide layer after being formed according to an embodiment of the present invention;

FIG. 10 is a cross-sectional view of a gate formed according to one embodiment of the present invention;

FIG. 11 is a cross-sectional view of a source and drain after formation according to one embodiment of the present invention;

FIG. 12 is a cross-sectional view of a sacrificial layer after formation of a sacrificial layer in accordance with an embodiment of the present invention;

FIG. 13 is a cross-sectional view of a patterned mask layer after formation in accordance with one embodiment of the present invention;

FIG. 14 is a schematic cross-sectional view of a through-hole formed in accordance with an embodiment of the present invention;

fig. 15 is a schematic cross-sectional view of a metal field plate after formation according to an embodiment of the present invention;

FIG. 16 is a cross-sectional structural view of the patterned mask layer and sacrificial layer after removal in accordance with one embodiment of the present invention; FIG. 16 is a schematic diagram illustrating the structure of an LDMOS device according to an embodiment of the present invention;

FIG. 17 is a schematic cross-sectional view along AA' of FIG. 16;

fig. 18 is a schematic cross-sectional structure in the direction BB' in fig. 16.

Reference numerals: 10. a substrate; 11. a drift region; 12. a trench; 13. a metal field plate; 14. a body region; 15. a gate oxide layer; 16. isolating the dielectric layer; 17. a sacrificial layer; 18. a pattern mask layer; 19. a through hole; 20. a gate electrode; 21. a source electrode; 22. and a drain electrode.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

As shown in fig. 1, the present invention provides a method for manufacturing an LDMOS device, which specifically includes the following steps:

step S10: a substrate 10 is provided.

Step S20: a plurality of trenches 12 are formed in the drift region 11 at intervals, and the trenches 12 are filled with an isolation dielectric layer 16.

Step S30: a drift region 11 is formed in the substrate 10, and the trenches 12 are distributed in the drift region 11.

Step S40: a metal field plate 13 is formed in each trench 12, and an isolation dielectric layer 16 is at least located between the metal field plate 13 and the inner wall of the trench 12.

In an alternative embodiment, for step S10, as shown in fig. 4, the substrate 10 may be, in particular, a silicon substrate, but is not limited to this.

For step S20, the method specifically includes the following steps:

step S201: a patterned mask layer (not shown) is formed on the surface of the substrate 10.

Specifically, a photoresist is spin-coated on the surface of the substrate 10 to form a mask layer, the mask layer is patterned by a photolithography process to form a patterned mask layer, a plurality of opening patterns are formed in the patterned mask layer, the opening patterns define the shape and position of the subsequently formed trench 12, and the opening patterns expose the substrate 10.

Step S202: the substrate 10 is etched based on the patterned mask layer to form a plurality of spaced trenches 12, as shown in fig. 5.

Specifically, the substrate 10 is etched based on the pattern mask layer, a dry etching process or a wet etching process may be adopted to form a plurality of trenches 12 arranged at intervals, and since the trenches 12 are arranged at intervals and may be arranged at equal intervals, a part of the substrate 10 which is not etched remains between the trenches 12.

Specifically, the trenches 12 may include, but are not limited to, rectangular trenches 12; the trench 12 extends from the surface of the substrate 10 to the substrate 10, and the depth of the trench 12 may be set according to actual needs, preferably, in this embodiment, the trench 12 is a shallow trench, and the depth of the trench is smaller, so that the manufacturing difficulty of the trench 12 is low, and a circuit path when carriers bypass the trench 12 is smaller.

Step S203: an isolation dielectric material layer is formed on the surface of the substrate 10, and the isolation dielectric material layer fills the trench 12, as shown in fig. 6.

Specifically, an isolation dielectric material layer is formed on the surface of the substrate 10 by a chemical vapor deposition process, the isolation dielectric material layer may be dense silicon dioxide or a high-dielectric-constant material, and the isolation dielectric material layer covers the surface of the substrate 10.

Step S204: the layer of isolation dielectric material on the surface of the substrate 10 is removed and the layer of isolation dielectric material in the trench 12 remains, as shown in fig. 7.

Specifically, the isolation dielectric material layer on the surface of the substrate 10 is removed by a chemical mechanical polishing process. In this embodiment, the structure of the trench 12 filled with the isolation dielectric material layer is an sti (shallow trench isolation) structure.

For step S30, specifically, as shown in fig. 8, ions of a second doping type are implanted on the substrate 10 through an ion implantation process to form the drift region 11, and the second doping type may be N-type doping.

As shown in fig. 2, in an alternative embodiment, after step S30 and before step S40, the following steps are further included:

step S31: a body region 14 is formed in the drift region 11 as shown in fig. 8.

Specifically, ions of a first doping type, which may include P-type doping, are implanted in the drift region 11 by means of ion implantation to form the body region 14.

Step S32: a gate oxide layer 15 is formed on the surface of the substrate 10, and the gate oxide layer 15 covers the drift region 11 and the body region 14, as shown in fig. 9.

Specifically, a gate oxide layer 15 is formed on the surface of the drift region 11 through a deposition process or a thermal oxidation process, the gate oxide layer 15 may be made of dense silicon dioxide or a high dielectric constant material, and the gate oxide layer 15 can effectively isolate the subsequently formed gate 20 from the drift region 11 and the gate 20 from the body region 14.

Step S33: a gate 20 is formed on the surface of the gate oxide layer 15, and the gate 20 is spanned over the drift region 11 and the body region 14, as shown in fig. 10.

Specifically, a doped polysilicon layer or a metal layer is deposited on the surface of the gate oxide layer 15 through a deposition process to form a gate electrode 20; in an alternative embodiment, the plurality of trenches 12 are arranged at intervals along the extending direction of the gate 20, in an alternative embodiment, the plurality of trenches 12 may be arranged in a column along the extending direction of the gate 20, and in other alternative embodiments, the plurality of trenches 12 may be arranged in a column along the width direction of the conductive channel.

Step S34: forming a source 21 in the body region 14 and a drain 22 in the drift region 11; the source electrode 21 is located on the side of the gate 20 remote from the metal field plate 13 and the drain electrode 22 is located on the side of the trench 12 remote from the gate 20, as shown in figure 11.

Specifically, the source electrode 21 is formed on the body region 14 through an ion implantation process, the drain electrode 22 is formed on the drift region 11 through an ion implantation process, both the source electrode 21 and the drain electrode 22 are of a second doping type, the second doping type may be N-type doping, and when the plurality of trenches 12 and the plurality of metal field plates 13 are arranged at intervals along the extending direction of the gate 20, the path that a carrier travels when flowing from the source electrode 21 to the drain electrode 22 through the drift region 11 between the trenches 12 is the shortest.

For step S40, the method specifically includes the following steps:

step S401: a sacrificial layer 17 is formed on the upper surface of the gate oxide layer 15 as shown in fig. 12.

Specifically, the sacrificial layer 17 may include, but is not limited to, a carbon layer, and specifically, the sacrificial layer 17 may be formed on the upper surface of the gate oxide layer 15 by a spin-on carbon process.

Step S402: a patterned mask layer 13 is formed on the surface of the sacrificial layer 17, as shown in fig. 10.

Specifically, a photoresist is spin-coated on the upper surface of the sacrificial layer 17 to form a mask layer, the mask layer is patterned by photolithography to form a patterned mask layer 18, an opening (not shown) is formed in the patterned mask layer 18, and the opening defines the shape and position of the metal field plate 13 to be formed subsequently.

Step S403: sacrificial layer 17 is etched based on patterned masking layer 18 to form via 19, as shown in fig. 14.

Specifically, the sacrificial layer 17 is etched based on the pattern mask layer 18 until the isolation dielectric material layer is exposed, the isolation dielectric layer 16 is formed in the trench 12 by etching the isolation dielectric material layer based on the pattern mask layer 18, the isolation dielectric layer 16 can effectively isolate the metal field plate 13 and the drift region 11 which are formed subsequently, namely, the through hole 19 penetrates through the sacrificial layer 17 along the thickness direction, and the formed through hole 19 exposes the isolation dielectric layer 16 at the bottom of the trench 12.

Step S404: a metal field plate 13 is formed in the via 19 and the patterned masking layer 18 and sacrificial layer 17 are removed, as shown in fig. 15 and 16.

Specifically, the through hole 19 is filled with a metal or a metal compound by a physical vapor deposition method to form the metal field plate 13, preferably, the metal field plate 13 is made of a tungsten silicon compound, the pattern mask layer 18 can be removed by an ashing process, and the sacrificial layer 17 can be removed by a wet etching process. The formed metal field plate 13 is of a cylindrical structure, specifically, the metal field plate 13 may be a rectangular cylindrical structure, or may also be a cylindrical structure, and in an alternative embodiment, the isolation dielectric layer 16 is filled in the trench 12 and attached to the outer wall of the metal field plate 12.

As shown in fig. 3, in an alternative embodiment, step S40 is followed by:

step S50: an interconnect structure (not shown) is formed that electrically connects the metal field plate 13 with the source electrode 21.

Specifically, an interconnection structure is formed between the metal field plate 13 and the source electrode 21, so that the metal field plate 13 is electrically connected with the source electrode 21; the interconnect structure may include, but is not limited to, a wire structure.

The present invention also provides an LDMOS device, as shown in fig. 16 and 5, including: a substrate 10; a drift region 11 located within the substrate 10; a plurality of grooves 12 arranged at intervals and located in the drift region 11; and a plurality of metal field plates 13 respectively positioned in the trenches 12.

In an alternative embodiment, the base 10 may be a P-type silicon substrate, which is a compound semiconductor material of group iv-iv composed of carbon and silicon, and the drift region 11 is formed by implanting ions of the second doping type into the base 10, that is, the drift region 11 is a region of the second doping type, which may include N-type. A plurality of grooves 12 are formed on the upper surface of the drift region 11, and the grooves 12 may include, but are not limited to, rectangular grooves; the trench 12 extends from the surface of the drift region 11 to the substrate 10, and the depth of the trench 12 can be set according to actual needs, preferably, in this embodiment, the depth of the trench 12 is smaller than the depth of the drift region 11; the metal field plate 13 may be a columnar structure, specifically, the metal field plate 13 may be a rectangular body, a cylinder, or a polygonal cylinder; the material of the metal field plate 13 is metal or metal compound, and specifically, the metal field plate 13 may be tungsten silicon compound.

In an alternative embodiment, a gate oxide layer 15 is formed on the drift region 11, the gate oxide layer 15 may be formed through a deposition process or a thermal oxidation process, and the gate oxide layer 15 may be dense silicon dioxide or a high dielectric constant material. The gate oxide layer 15 is formed with a gate electrode 20, the gate oxide layer 15 isolates the gate electrode 20 from the drift region 11, and the gate electrode 20 may be doped polysilicon or metal.

A body region 14 is formed on the drift region 11 by ion implantation, the body region 14 extends from one side of the gate 20 to below the gate 20, and the body region 14 may be of the first doping type. A source 21 is formed on the body region 14 by ion implantation, the source 21 being located on the side of the gate 20, and a drain 22 being located on the side of the gate 20 away from the source 21. The drain 22 and the source 21 may both be of a second doping type, the first doping type may be a P-type doping, and the second doping type may be an N-type doping. The trench 12 and the metal field plate 13 are both located between the gate 20 and the drain 22 with a gap between the gate 20 and the drain 22. As shown in fig. 14 to 16, in an alternative embodiment, the plurality of trenches 12 and the plurality of metal field plates 13 are arranged at intervals along the extending direction of the gate 20, and specifically, the plurality of trenches 12 and the plurality of metal field plates 13 may be arranged in a column along the extending direction of the gate 20; at this time, the paths of the carriers flowing from the source 21 to the drain 22 include two paths, one current path is required to bypass the trench to reach the drain 22 as shown in fig. 17, and the other current path is required to flow from the source 21 to the drain 22 directly along the drift region surface as shown in fig. 18, and the combined application of the two current paths effectively reduces the distance of the carriers flowing from the source 21 to the drain 22 in the whole device, thereby reducing the on-resistance.

An isolation dielectric layer 16 is formed on the side wall and the bottom wall of the trench 12, the isolation dielectric layer 16 is integrally connected with the gate oxide layer 15, and the isolation dielectric layer 16 is located between the metal field plate 13 and the drift region 11 to separate the metal field plate 13 from the drift region 11. In an alternative embodiment, the isolation dielectric layer 16 fills the trench 12 and abuts the outer wall of the metal field plate 12.

The trench 12 enables the metal aperture field plate to effectively extend into the drift region, thereby forming a multi-dimensional depletion effect. Meanwhile, the isolation dielectric layer 16 can effectively isolate the metal field plate 13 from the drift region 11 of the LDMOS. The method does not need to add a mask plate on the cost, and is optimal in terms of the compatibility of the prior art. Carriers of the LDMOS device basically flow to the drain 22 along the surface of the drift region 11, so that the conventional trench type metal field plate structure does not consider this critical influence factor in design, and the trench is designed to be deeper, so that an extremely depletion effect is pursued, and the reduction of the on-resistance of the LDMOS is limited. The patent deeply recognizes that the current path on the surface of the drift region 11 is the key for influencing the conduction of the LDMOS, so that the structure provided by the patent can not only retain the carrier channel on a part of the surface, but also make the path below the trench 12 not as far as the deep trench structure, and effectively reduce the on-resistance caused by the structure itself by combining the two.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. An LDMOS device, comprising:

a substrate;

a drift region located within the substrate;

the grooves are arranged at intervals and are positioned in the drift region;

the metal field plates are respectively positioned in the grooves;

2. The LDMOS device set forth in claim 1 wherein said metal field plate is of a tungsten silicon compound.

3. The LDMOS device of claim 1, wherein the metal field plate comprises a columnar structure.

4. The LDMOS device of claim 1, wherein the trench is a shallow trench.

5. The LDMOS device of any of claims 1-4, further comprising:

a gate located on the drift region;

the gate oxide layer is positioned between the grid and the drift region;

6. The LDMOS device of claim 5, wherein a plurality of the trenches are spaced apart along a direction in which the gate extends.

7. The LDMOS device of claim 6, wherein a plurality of the trenches are arranged in a column along a direction in which the gate extends.

8. The LDMOS device of claim 6, further comprising an interconnect structure electrically connecting the source electrode with the metal field plate.

9. A preparation method of an LDMOS device is characterized by comprising the following steps:

providing a substrate;

forming a plurality of grooves which are arranged at intervals in the substrate, wherein isolation medium layers are filled in the grooves;

forming a drift region in the substrate, wherein the grooves are distributed in the drift region;

10. The method of claim 9, wherein the forming a drift region in the substrate, the forming a metal field plate in each trench after the trenches are distributed in the drift region, and the insulating dielectric layer at least before the metal field plate and the inner wall of the trench further comprises:

forming a body region in the drift region;

11. The method of claim 10, wherein a plurality of the trenches are spaced along a direction in which the gate extends.

12. The method of claim 11, wherein a source is formed in the body region and a drain is formed in the drift region; the source electrode is positioned on one side of the grid electrode far away from the metal field plate, and the drain electrode is positioned behind one side of the groove far away from the grid electrode, and the method further comprises the following steps: forming an interconnect structure electrically connecting the metal field plate with the source electrode.