CN113127291B - Micro controller - Google Patents

Abstract

A microcontroller includes a slave device, a master device and a bus. The slave device accesses a storage device according to an access instruction. The master device executes a program code to provide the access instruction. The bus is coupled between the slave device and the master device to transmit the access instruction to the slave device. When a trigger event occurs, the master device monitors the access status of the storage device to generate a monitoring result to an external device. The microcontroller provided in the present application is capable of monitoring the access status of its own storage device.

Description

Microcontroller

Technical Field

The invention relates to a microcontroller, and in particular to a microcontroller for monitoring the access status of its own storage device.

Background technique

With the advancement of technology, the types and functions of electronic devices are increasing. Generally, there is a microcontroller inside an electronic device. The microcontroller operates according to its internal program code. When the program code has an error (bug), the microcontroller will not work properly.

Summary of the invention

The present invention provides a microcontroller, including a slave device, a master device and a bus. The slave device accesses a storage device according to an access instruction. The master device executes a program code to provide the access instruction. The bus is coupled between the slave device and the master device to transmit the access instruction to the slave device. When a trigger event occurs, the master device monitors the access status of the storage device to generate a monitoring result to an external device. The microcontroller provided by the present application can monitor the access status of its own storage device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an operating system of the present invention.

FIG. 2 is a schematic diagram of a microcontroller according to the present invention.

FIG. 3 is another schematic diagram of the microcontroller of the present invention.

FIG. 4 is a schematic diagram of the interior of a storage module of the present invention.

【Symbol Description】

100: operating system;

110: external device;

120: Connector;

130, 200, 300: microcontroller;

121, 122: transmission interface;

210, 310, 320: main device;

220, 230, 330, 340: slave device;

240, 250, 350, 60: busbar;

CM ₁ , CM ₂ : access instructions;

CM ₃ : control instructions;

221, 231, 232, 331, 341: storage device;

260, 270: memory;

370: storage module;

PRC: program code;

S _M , S _MA , S _MB : monitoring results;

411-418: Repository;

addr_A, addr_B: address parameter group;

DA_A, DA_B: data parameter group;

TMS_A, TMS_B: time parameter group;

RorW_A, RorW_B: access parameter groups.

Detailed ways

In order to make the purpose, features and advantages of the present invention more clearly understood, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each element in the embodiment is for illustrative purposes and is not intended to limit the present invention. In addition, some repetitions of the figure numbers in the embodiments are for the purpose of simplifying the description and do not mean the relevance between different embodiments.

FIG. 1 is a schematic diagram of an operating system of the present invention. As shown in the figure, the operating system 100 includes an external device 110, a connector 120, and a microcontroller 130. The external device 110 communicates with the microcontroller 130 through the connector 120. In the present embodiment, the external device 110 analyzes the parameter group provided by the microcontroller 130 for the user to determine whether the flow of the program code inside the microcontroller 130 is correct. The present invention does not limit the type of the external device 110. In one possible embodiment, the external device 110 is a computer device. In this example, the external device 110 may be installed with a monitoring application code. When the user turns on the monitoring application code, the external device 110 presents an analysis screen for the user's reference based on the parameter group provided by the microcontroller 130.

The connector 120 is coupled between the external device 110 and the microcontroller 130. In the present embodiment, the connector 120 has transmission interfaces 121 and 122. The transmission interface 121 is used to couple the external device 110. The transmission interface 122 is used to couple the microcontroller 130. The present invention does not limit the types of the transmission interfaces 121 and 122. In one possible embodiment, the transmission interface 121 is a USB interface. In other embodiments, the type of the transmission interface 121 may be the same as or different from the type of the transmission interface 122.

In one possible embodiment, the connector 120 is used as a key. Through the connector 120, the external device 110 can access the microcontroller 130. Similarly, through the connector 120, the microcontroller 130 provides the relevant parameter set to the external device 110. In other embodiments, the connector 120 may be integrated into the external device 110 or the microcontroller 130. In some embodiments, the connector 120 may be omitted. In this example, the external device 110 and the microcontroller 130 have encryption and decryption functions to improve security.

The microcontroller 130 communicates with the external device 110 through the connector 120. When a trigger event occurs, the microcontroller 130 monitors the access status of the internal storage device and provides a monitoring result to the external device 110. In one possible embodiment, the trigger event refers to a button (not shown) being pressed. The button may be set in the microcontroller 130. When the user presses the button, the microcontroller 130 performs a monitoring operation. In another possible embodiment, the trigger event refers to the external device 110 issuing a monitoring trigger. In this example, when the user opens a monitoring application code of the external device 110, the external device 110 issues the monitoring trigger to command the microcontroller 130 to perform a monitoring operation.

Since the user can know the access status of the storage device inside the microcontroller 130 according to the monitoring result of the microcontroller 130, when the access status of the storage device inside the microcontroller 130 does not meet the preset value, the user can quickly find out the abnormality and perform debugging. Furthermore, since the microcontroller 130 only monitors the access status of the storage device, only a binary file is needed to know the data flow, and the external device 110 does not need to have the source code to reconstruct the program code flow executed by the microcontroller 130, thereby simplifying the debugging process.

FIG2 is a schematic diagram of a microcontroller of the present invention. As shown in the figure, the microcontroller 200 includes a master device 210, slave devices 220, 230, and buses 240 and 250. The master device 210 executes a program code PRC to issue access instructions CM ₁ and CM _2. The present invention does not limit the architecture of the master device 210. Any device that can issue access instructions can be used as the master device 210. In a possible embodiment, the master device 210 is a central processing unit (CPU) or a peripheral direct memory access controller (PDMA controller).

The slave device 220 accesses a storage device 221 according to the access instruction _CM1 . The present invention does not limit the number of storage devices. In other embodiments, the slave device 220 has more storage devices. In addition, in this embodiment, the storage device 221 is integrated into the slave device 220, but it is not used to limit the present invention. In other embodiments, the storage device 221 may be independent of the slave device 220. In one possible embodiment, the storage device 221 includes at least one register.

The slave device 230 accesses at least one of the storage devices 231 and 232 according to the access command CM ₂ . In other embodiments, the slave device 230 has more or fewer storage devices. In addition, in this embodiment, the storage devices 231 and 232 are integrated into the slave device 230, but this is not intended to limit the present invention. In other embodiments, at least one of the storage devices 231 and 232 is independent of the slave device 230. In one possible embodiment, the storage devices 231 and 232 each include at least one register.

The present invention does not limit the types of slave devices 220 and 230. The type of slave device 220 may be the same as or different from the type of slave device 230. In one possible embodiment, slave device 220 is an Inter-Integrated Circuit (I2C) circuit, and slave device 220 is a Universal Asynchronous Receiver/Transmitter (UART).

The bus 240 is coupled between the slave device 220 and the master device 210 to transmit the access command CM ₁ . The bus 250 is coupled between the slave device 230 and the master device 210 to transmit the access command CM ₂ . The present invention does not limit the types of the buses 240 and 250 . The types of the buses 240 and 250 correspond to the transmission interfaces of the slave devices 220 and 230 , respectively. For example, it is assumed that the slave device 220 is an I2C circuit, and the slave device 220 is a UART. In this example, the bus 240 is an I2C bus, and the bus 250 is a UART bus.

The present invention does not limit the number of slave devices of the microcontroller 200. In other embodiments, the microcontroller 200 may have more or fewer slave devices. In this case, the number of buses will also vary with the number of slave devices. For example, when the microcontroller 200 has more slave devices, the microcontroller 200 needs to use more buses to transmit instructions to the slave devices.

In other embodiments, the microcontroller 200 further includes a memory 260. The memory 260 is used to store the program code PRC. When the host device 210 executes the program code PRC, the host device 210 generates access instructions _CM1 and _CM2 to access the storage devices 221, 231, and 232. When a first trigger event occurs, the host device 210 monitors the access status of the storage devices 221, 231, and 232 to generate a monitoring result _SM . In one possible embodiment, the host device 210 directly outputs the monitoring result _SM to the external device 110. In another possible embodiment, the microcontroller 200 further includes a memory 270. The memory 270 is used to store the monitoring result _SM . In this example, the host device 210 first stores the monitoring result _SM in the memory 270, and at a specific time, reads the monitoring result _SM of the memory 270, and outputs the monitoring result _SM to the external device 110. The present invention does not limit the type of the memory 270. The memory 270 may be a volatile memory or a non-volatile memory. In one embodiment, the memory 270 is a static random access memory (SRAM).

In other embodiments, when a second trigger event occurs, the host device 210 stops monitoring the access status of the storage devices 221, 231, and 232. In this example, the host device 210 may read the monitoring result S _M stored in the memory 270 and provide the monitoring result S _M to the external device 110. The external device 110 analyzes the monitoring result S _M to generate an analysis screen. In this example, the user determines whether the flow of the program code PRC is correct based on the analysis screen of the external device 110.

The present invention does not limit the types of the first and second trigger events. In one possible embodiment, the main device 210 determines whether a first button (not shown) and a second button (not shown) are pressed. When the first button is pressed, it indicates that the first trigger event occurs. Therefore, the main device 210 performs a monitoring operation. When the second button is pressed, it indicates that the second trigger event occurs. Therefore, the main device 210 stops the monitoring operation.

In another possible embodiment, when the user opens a monitoring application code (not shown) of the external device 110 and clicks a monitoring option, the external device 110 sends a first trigger signal to the host device 210. The host device 210 starts to monitor the access status of the storage devices 221, 231, and 232 according to the first trigger signal. When the user clicks a stop option, the external device 110 sends a second trigger signal to the host device 210. The host device 210 stops monitoring the access status of the storage devices 221, 231, and 232 according to the second trigger signal. In this example, when the user clicks a transfer option, the external device 110 sends a third trigger signal to the host device 210. The host device 210 reports the monitoring result S _M according to the third trigger signal. In other embodiments, when the host device 210 executes the program code and reaches a breakpoint, it indicates that the second trigger event occurs. Therefore, the host device 210 stops monitoring.

FIG. 3 is another schematic diagram of the microcontroller of the present invention. FIG. 3 is similar to FIG. 2, except that the access commands _CM1 and _CM2 of FIG. 3 are provided by different master devices (such as 310 and 320). In this embodiment, the master device 310 transmits the access command _CM1 to the slave device 330 via the bus 350. The slave device 330 accesses the storage device 331 according to the access command _CM1 . In addition, the master device 320 transmits the access command _CM2 to the slave device 340 via the bus 360. The slave device 340 accesses the storage device 341 according to the access command _CM2 .

In one possible embodiment, the master device 310 is a central processing unit, and the master device 320 is a PDMA controller. When a first trigger event occurs, the master device 310 monitors the access operation of the slave device 330 to generate a monitoring result S _MA . When a second trigger event occurs, the master device 310 stops monitoring the access operation of the slave device 330. When a third trigger event occurs, the master device 320 monitors the access operation of the slave device 340 to generate a monitoring result S _MB . When a fourth trigger event occurs, the master device 320 stops monitoring the access operation of the slave device 340.

In one possible embodiment, the master devices 310 and 320 may store the monitoring results S _MA and S _MB in the storage module 370, respectively. In other embodiments, at least one of the master devices 310 and 320 directly outputs the monitoring results (S _MA and/or S _MB ) to an external device. In this embodiment, the storage module 370 has at least one memory (not shown) for storing program code and the monitoring results S _MA and S _MB . Since the characteristics of the slave devices 330, 340, and the bus 350, 360 are similar to those of the slave devices 220, 230, and the bus 240, 250 of FIG. 2 , they are not described in detail.

In some embodiments, the master device 310 executes a program code stored in the storage module 370 to generate a control instruction CM ₃ . The master device 320 generates an access instruction CM ₂ according to the control instruction CM ₃ to access the slave device 340 . In other embodiments, the master device 320 directly executes the program code stored in the storage module 370 to generate the access instruction CM ₂ . In one possible embodiment, the storage module 370 has a non-volatile memory to store the program code. In this example, the storage module 370 further has a volatile memory to store the monitoring results S _MA and S _MB . In other embodiments, the monitoring results S _MA and S _MB are stored in the non-volatile memory.

FIG4 is an internal schematic diagram of the storage module 370 of the present invention. As shown in the figure, the storage module 370 includes storage banks 411-418, but this is not intended to limit the present invention. In other embodiments, the storage module 370 has more or fewer storage banks. In this embodiment, the storage banks 411-414 are used to store the monitoring results S _MA , and the storage banks 415-418 are used to store the monitoring results S _MB .

The memory bank 411 is used to store the address parameter set addr_A in the monitoring result S _MA . For example, when the host device 310 accesses data at addresses 0x4007003x and 0x4007000c of the storage device 331 , the host device 310 records the addresses 0x4007003x and 0x4007000c in the memory bank 411 .

The storage memory 412 is used to store the data parameter group DA_A in the monitoring result S _MA . In one embodiment, the data parameter group DA_A is used to represent the data values written by the host device 310 to the addresses 0x4007003x and 0x4007000c, or the data values obtained by the host device 310 from the addresses 0x4007003x and 0x4007000c.

The memory bank 413 is used to store the time parameter set TMS_A in the monitoring result S _MA . For example, the host device 310 may access the memory device 331 at the fifth cycle and the sixth cycle of an operating frequency. In this example, the host device 310 records the cycles cycle5 and cycle6 in the memory bank 413 .

The storage memory 414 is used to store the access parameter set RorW_A in the monitoring result S _MA . For example, the host device 310 may write two data into the storage device 331 respectively. Therefore, the storage memory 414 records two write operations Write.

The memory banks 415-418 respectively record the address parameter group addr_B, data parameter group DA_B, time parameter group TMS_B and access parameter group RorW_B in the monitoring result S _MB . Since the characteristics of the address parameter group addr_B, data parameter group DA_B, time parameter group TMS_B and access parameter group RorW_B are the same as those of the address parameter group addr_A, data parameter group DA_A, time parameter group TMS_A and access parameter group RorW_A, they are not described in detail. In other embodiments, the address parameter group addr_B, data parameter group DA_B, time parameter group TMS_B and access parameter group RorW_B may be stored in the memory banks 411-414 respectively.

Since the main device only monitors the access status of the storage device (such as a register), the monitoring results S _MA and S _MB are just simple binary format files. The external device (such as a computer device) analyzes the monitoring results S _MA and S _MB to generate an easy-to-read format (such as a waveform) for the user's reference, so that the user can quickly know whether the flow of the program code is correct.

Unless otherwise defined, all words (including technical and scientific words) herein are generally understood by those skilled in the art to which the present invention belongs. In addition, unless expressly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in the relevant technical field, and should not be interpreted as an ideal state or overly formal tone.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims (9)

1. A microcontroller, comprising: A first slave device accesses a first storage device according to a first access instruction; a host device executing a program code to provide the first access instruction; and a first bus coupled between the first slave device and the master device, for transmitting the first access instruction to the first slave device; When a first trigger event occurs, the host device monitors the access status of the first storage device to generate a monitoring result. When a second trigger event occurs, the host device stops monitoring the access status of the first storage device and provides the monitoring result to an external device. The monitoring result includes a time point when the host device accesses the first storage device or a number of times when the host device writes data to the first storage device. 2. The microcontroller according to claim 1, further comprising: a second slave device, accessing a second storage device according to a second access instruction; and A second bus is coupled between the second slave device and the master device, and is used to transmit the second access instruction to the second slave device, wherein the master device executes the program code to provide the second access instruction. 3 . The microcontroller according to claim 2 , wherein the first slave device is a universal asynchronous transceiver transmitter, and the second bus is an inter-integrated circuit bus. 4 . The microcontroller according to claim 1 , wherein the host device is a central processing unit or a peripheral memory direct access device. 5. The microcontroller according to claim 1, further comprising: A memory is used to store the monitoring result. 6 . The microcontroller according to claim 1 , wherein the host device directly outputs the monitoring result to the external device. 7. The microcontroller according to claim 1, further comprising: A button, when the button is pressed, it indicates that the first trigger event occurs. 8 . The microcontroller according to claim 1 , wherein the program code has a breakpoint, and when the host device executes to the breakpoint, it indicates that the second trigger event occurs. 9 . The microcontroller according to claim 1 , wherein the first trigger event and the second trigger event are caused by the external device.