CN113097174A - High-power many basic lead internal insulation TO series's packaging structure - Google Patents
High-power many basic lead internal insulation TO series's packaging structure Download PDFInfo
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- CN113097174A CN113097174A CN202110416197.7A CN202110416197A CN113097174A CN 113097174 A CN113097174 A CN 113097174A CN 202110416197 A CN202110416197 A CN 202110416197A CN 113097174 A CN113097174 A CN 113097174A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 14
- 238000009421 internal insulation Methods 0.000 title abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052802 copper Inorganic materials 0.000 claims abstract description 16
- 239000010949 copper Substances 0.000 claims abstract description 16
- 238000009413 insulation Methods 0.000 claims abstract 3
- 239000000919 ceramic Substances 0.000 claims description 10
- 238000011084 recovery Methods 0.000 claims description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 2
- 230000008569 process Effects 0.000 abstract description 2
- 229910002601 GaN Inorganic materials 0.000 description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model provides a high-power many base lead internal insulation TO series's packaging structure, including a frame base member, the upper end of frame base member is provided with the fin, the centre is many base lead internal insulation module bottom plate copper frame, the lower extreme is a plurality of pins, it has the potsherd TO be packaged with on the many base lead internal insulation module bottom plate copper frame, set up first base island and second base island on the potsherd at least, the equipment has first high-power chip on the first base island, the equipment has the high-power chip of second on the second base island, a plurality of pins set up on the potsherd, be connected with the bonding lead between first high-power chip and the high-power chip of second and the pin. The invention has the greatest advantages that the product can achieve internal insulation and can be provided with two or more high-power chips, control chips or protection combinations, and the like, so that the product can achieve diversification, various functions can be realized, insulation can be achieved between the radiating fins and the chips of the product, and a plurality of operation processes and material cost can be reduced in the application of the product.
Description
Technical Field
The invention belongs TO the field of semiconductor TO series packaging, and particularly relates TO a packaging structure of a multi-base-island internal insulation module.
Background
Chip packaging is a technique for packaging integrated circuits with insulating plastic or ceramic materials, and is an important part of the overall integrated circuit manufacturing process. The chip package plays the role of placing, fixing, sealing, protecting the chip and enhancing the heat dissipation performance, and can isolate the external pollution and the damage of external force to the chip. In the field of semiconductor packaging, with the development of technology, the packaging requirements of semiconductor product application are higher and higher. For example, more chips need to be integrated in one package body, so as to achieve the purposes of high integration level, reduction of package volume, shortening of chip interconnection distance, improvement of chip processing speed and the like.
Disclosure of Invention
The invention aims to provide a packaging structure of a multi-base-island internal insulation module, which can realize different functional applications through the assembly of different chips of multiple base islands.
In order to achieve the purpose, the invention adopts the following technical scheme:
the utility model provides a packaging structure of high-power many leading internal insulation TO series, includes a frame base member, the upper end of frame base member is provided with the fin, and the centre is many leading internal insulation module bottom plate copper frame, and the lower extreme is a plurality of pins, be packaged with the potsherd on the many leading internal insulation module bottom plate copper frame, set up first base island and second base island on the potsherd at least, the equipment has first high-power chip on the first base island, the equipment has second high-power chip on the second base island, and a plurality of the pin sets up on the potsherd, first high-power chip with second high-power chip with be connected with the bonding lead between the pin.
The invention has the following beneficial effects:
1. two base guides are designed in the bottom plate copper frame, and the base guides can be added subsequently, so that products with different performances and different application fields can be realized when different base guides are designed, and diversification of the products is realized.
2. The pin can be applied through different circuits in the design, and different application functions can be realized by adjusting the positions of the bonding wires.
3. The high-power chips with different functions are assembled on different base conductors to realize various functions of the product, and the chips with different sizes can be assembled on the base conductors of the product, and can also be used as chips such as MOS (metal oxide semiconductor) tubes, silicon controlled rectifiers, fast recovery diodes, silicon carbide, gallium nitride, ICs (integrated circuits) and the like, so that the product can be assembled in different ways to realize different functional applications.
4. The chip and the pin can be welded by an aluminum wire or a copper sheet, if a low-current product can be welded by the aluminum wire, and if a high-current product can be welded by the copper sheet, the product can be greatly improved under high-current impact.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of a high-power multi-base-conductor internal insulation TO series package structure according TO the present invention.
Fig. 2 is a schematic structural diagram of another embodiment of a high-power multi-conductor internal insulation TO series package structure according TO the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, and furthermore, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1:
referring to fig. 1, the present invention provides an embodiment:
the utility model provides a packaging structure of high-power many base conduction internal insulation TO series, includes a frame base member, the upper end of frame base member is provided with fin 1, and the centre is many base conduction internal insulation module bottom plate copper frame 4, and the lower extreme is a plurality of pins 5, it has potsherd 9 TO encapsulate on many base conduction internal insulation module bottom plate copper frame 4, set up first base island 2 and second base island 8 on the potsherd base plate 9, the equipment has first high-power chip 3 on the first base island 2, the equipment has second high-power chip 7 on the second base island 8, and is a plurality of pin 5 sets up on the potsherd 9, first high-power chip 3 with second high-power chip 7 with be connected with bonding lead 6 between the pin 5.
Preferably, the first high-power chip 3 is a MOS transistor, a thyristor, a fast recovery diode, silicon carbide, gallium nitride, or an IC chip.
Preferably, the second high-power chip 7 is a MOS transistor, a thyristor, a fast recovery diode, silicon carbide, gallium nitride, or an IC chip.
Preferably, the ceramic sheet 9 is an aluminum oxide substrate or an aluminum nitride substrate.
Preferably, the bonding wire 6 is an aluminum wire or a copper sheet.
The product is molded by high-temperature sintering, so that the chip and the radiating fin of the product can be completely insulated, the product can be provided with a high-power chip, a product with higher power can be provided for various power supplies, the cost can be reduced and the efficiency can be improved in application, two radiating fins and two products are required on a circuit in the cost, the technology of the embodiment of the invention can completely achieve the insulating effect only by one product and one radiating fin to complete the previous functions, and meanwhile, an insulating film is not required to be arranged on the back of the product.
The TO series of the high-power multi-base-conductor internal insulation has the greatest advantages that the internal insulation of a product can be achieved, and two or more high-power chip combinations can be arranged in the product, so that the product can achieve diversification, various functions can be realized, meanwhile, the heat radiating fins and the chips of the product are insulated, and a lot of operation processes and material cost are reduced in the application of the product. Convenient popularization, reduced space and wide application range.
Example 2:
referring to fig. 2, another embodiment of the present invention is provided:
a high-power multi-base-conduction internal insulation TO series packaging structure comprises a frame base body, wherein a radiating fin 1 is arranged at the upper end of the frame base body, a multi-base-conduction internal insulation module base plate copper frame 4 is arranged in the middle of the frame base body, a plurality of pins 5 are arranged at the lower end of the frame base body, a ceramic plate 9 is packaged on the multi-base-conduction internal insulation module base plate copper frame 4, a first base island 2, a second base island 8 and a third base island 10 are less arranged on the ceramic plate base plate 9, a first high-power chip 3 is assembled on the first base island 2, a second high-power chip 7 is assembled on the second base island 8, a third high-power chip 11 is assembled on the third base island 10, a plurality of pins 5 are arranged on the ceramic plate 9, and a bonding lead 6 is connected between the first high-power chip 3 and the second high-power chip 7 and the pins 5.
Preferably, the first high-power chip 3 is a MOS transistor, a thyristor, a fast recovery diode, silicon carbide, gallium nitride, or an IC chip.
Preferably, the second high-power chip 7 is a MOS transistor, a thyristor, a fast recovery diode, silicon carbide, gallium nitride, or an IC chip.
Preferably, the second high-power chip 11 is a MOS transistor, a thyristor, a fast recovery diode, silicon carbide, gallium nitride, or an IC chip.
Preferably, the ceramic sheet 9 is an aluminum oxide substrate or an aluminum nitride substrate.
Preferably, the bonding wire 6 is an aluminum wire or a copper sheet.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110416197.7A CN113097174A (en) | 2021-04-19 | 2021-04-19 | High-power many basic lead internal insulation TO series's packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110416197.7A CN113097174A (en) | 2021-04-19 | 2021-04-19 | High-power many basic lead internal insulation TO series's packaging structure |
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| Publication Number | Publication Date |
|---|---|
| CN113097174A true CN113097174A (en) | 2021-07-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110416197.7A Pending CN113097174A (en) | 2021-04-19 | 2021-04-19 | High-power many basic lead internal insulation TO series's packaging structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114649217A (en) * | 2022-03-17 | 2022-06-21 | 西安西奈电子科技股份有限公司 | To-247 low-thermal-resistance high-speed insulation packaging method |
| CN117476633A (en) * | 2023-10-24 | 2024-01-30 | 重庆平伟实业股份有限公司 | Power chip, power chip manufacturing method and power factor correction circuit |
| CN119864333A (en) * | 2025-01-03 | 2025-04-22 | 品捷电子(苏州)有限公司 | Packaging structure of insulating series in car rule level TO-247PLUS |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06132468A (en) * | 1992-10-20 | 1994-05-13 | Hitachi Ltd | Semiconductor device |
| CN207398138U (en) * | 2017-11-22 | 2018-05-22 | 杭州友旺科技有限公司 | Semiconductor package |
| CN211605144U (en) * | 2020-04-09 | 2020-09-29 | 品捷电子(苏州)有限公司 | Packaging structure of gallium nitride chip in TO-220 |
| CN216435890U (en) * | 2021-04-19 | 2022-05-03 | 品捷电子(苏州)有限公司 | High-power many basic lead internal insulation TO series's packaging structure |
-
2021
- 2021-04-19 CN CN202110416197.7A patent/CN113097174A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06132468A (en) * | 1992-10-20 | 1994-05-13 | Hitachi Ltd | Semiconductor device |
| CN207398138U (en) * | 2017-11-22 | 2018-05-22 | 杭州友旺科技有限公司 | Semiconductor package |
| CN211605144U (en) * | 2020-04-09 | 2020-09-29 | 品捷电子(苏州)有限公司 | Packaging structure of gallium nitride chip in TO-220 |
| CN216435890U (en) * | 2021-04-19 | 2022-05-03 | 品捷电子(苏州)有限公司 | High-power many basic lead internal insulation TO series's packaging structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114649217A (en) * | 2022-03-17 | 2022-06-21 | 西安西奈电子科技股份有限公司 | To-247 low-thermal-resistance high-speed insulation packaging method |
| CN117476633A (en) * | 2023-10-24 | 2024-01-30 | 重庆平伟实业股份有限公司 | Power chip, power chip manufacturing method and power factor correction circuit |
| CN119864333A (en) * | 2025-01-03 | 2025-04-22 | 品捷电子(苏州)有限公司 | Packaging structure of insulating series in car rule level TO-247PLUS |
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