CN113096585A

CN113096585A - Pixel driving device and driving method thereof

Info

Publication number: CN113096585A
Application number: CN202110400095.6A
Authority: CN
Inventors: 赖柏君; 吴韦霆; 唐鸣远; 张玮轩; 陈勇志
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2020-11-20
Filing date: 2021-04-14
Publication date: 2021-07-09
Anticipated expiration: 2041-04-14
Also published as: TW202221687A; TWI765423B; CN113096585B

Abstract

A pixel driving device and a driving method thereof. The pixel driving device includes a current source and a pulse width modulation circuit. A current source is used to generate current. The pulse width modulation circuit is used for resetting in the first stage according to the reset signal or the first scanning signal of the previous stage. The pulse width modulation circuit is used for generating a pulse width modulation signal according to the first scan signal and the selection signal in the second stage, and driving the current source according to the pulse width modulation signal, so that the current source provides current to the light-emitting element. The selection signal generates a pulse signal in the second stage according to one of the plurality of gray scales. The time point at which the pulse signal is generated in the second stage determines the duty cycle of the PWM signal.

Description

Pixel driving device and driving method thereof

Technical Field

The present disclosure relates to a display device and method. In detail, the present disclosure relates to a pixel driving device and a pixel driving method.

Background

In the structure of the conventional display, an Integrated Circuit (IC) is packaged between a glass substrate and a printed circuit board of the lcd by a Chip On Film (COF) technology, so that data can be provided to a display panel by the IC using the COF technology. However, the data driving ic adopting COF technology occupies a certain volume in the entire display, and increases the production cost of the display. Therefore, the data driving integrated circuit adopting the COF technology has many defects, and other suitable data providing methods have yet to be developed by those skilled in the art.

Disclosure of Invention

One aspect of the present disclosure relates to a pixel driving device. The pixel driving device comprises a current source and a pulse width modulation circuit. The current source is used for generating current. The pulse width modulation circuit is used for resetting according to a reset signal or a previous stage first scanning signal in a first stage. The pulse width modulation circuit is used for generating a pulse width modulation signal according to the first scanning signal and the selection signal in the second stage and driving the current source according to the pulse width modulation signal, so that the current source provides current to the light-emitting element. The selection signal generates a pulse signal in the second phase according to one of the plurality of gray levels. The time point of the pulse signal generated in the second stage determines the duty cycle of the PWM signal.

Another aspect of the present disclosure relates to a pixel driving method. The pixel driving method comprises the following steps: resetting the PWM circuit according to a reset signal or a preceding-stage first scan signal at a first stage; and generating a pulse width modulation signal according to the first scanning signal and the selection signal in the second stage, and driving the current source according to the pulse width modulation signal so that the current source provides current to the light-emitting element. The selection signal generates a pulse signal in the second phase according to one of the plurality of gray levels. The time point of the pulse signal generated in the second stage determines the duty cycle of the PWM signal.

Drawings

The disclosure may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic diagram illustrating a partial structure of a pixel driving device according to some embodiments of the present disclosure;

FIG. 2 is a flow chart illustrating steps of a pixel driving method according to some embodiments of the present disclosure;

FIG. 3 is a signal timing diagram illustrating a pixel driving method according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram illustrating the state of elements of a pixel driving device according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram illustrating the state of elements of a pixel driving device according to some embodiments of the present disclosure;

FIG. 6 is a partial block diagram illustrating a pixel driving device according to some embodiments of the present disclosure;

FIG. 7 is a signal timing diagram illustrating a pixel driving method according to some embodiments of the present disclosure;

FIG. 8 is a schematic diagram illustrating the state of elements of a pixel driving device according to some embodiments of the present disclosure;

FIG. 9 is a schematic diagram illustrating the state of the elements of a pixel driving device according to some embodiments of the present disclosure;

FIG. 10 is a schematic diagram illustrating the state of the elements of a pixel driving device according to some embodiments of the present disclosure;

FIG. 11 is a schematic diagram illustrating the state of the elements of a pixel driving device according to some embodiments of the present disclosure;

FIG. 12 is a schematic diagram illustrating the state of the elements of a pixel driving device according to some embodiments of the present disclosure; and

fig. 13 is a schematic diagram illustrating the state of elements of a pixel driving device according to some embodiments of the present disclosure.

Description of reference numerals:

100: pixel driving device

110: pulse width modulation circuit

120: current source

VDD: power supply voltage (high potential)

VSS: power supply voltage (Low potential)

VREF 1: a first reference voltage

VREF 2: second reference voltage

ST: signal

S1[ N ]: first scanning signal

Sel: selection signal

DT 1: driving transistor

T1: a first transistor

T2: second transistor

T3: a third transistor

C1: first capacitor

N1: first node

L: light emitting element

T4: a fourth transistor

200: method of producing a composite material

210-220: step (ii) of

R < N >: reset signal

S1[ N-1], S1[ N ]: first scanning signal

Sel1 to Sel 5: selection signal

I1: first stage

I2: second stage

Duty 1-Duty 4: duty cycle of pulse width signal

P1-P4: time point of generating pulse signal

600: pixel driving device

610: pulse width modulation circuit

620: current source

VDD: power supply voltage (high potential)

VSS: power supply voltage (Low potential)

VREF 1: a first reference voltage

VREF 2: second reference voltage

ST: signal

S1[ N ]: first scanning signal

S2[ N ], S2[ N +1 ]: second scanning signal

Sel: selection signal

DT 1: driving transistor

T1: a first transistor

T2: second transistor

T3: a third transistor

C1: first capacitor

N1: first node

L: light emitting element

C2: second capacitor

N2 second node

T4: a fourth transistor

T5: fifth transistor

T6: sixth transistor

T7: seventh transistor

T8: eighth transistor

T9: ninth transistor

R < N >: reset signal

S1[ N-1], S1[ N ]: first scanning signal

S2[ N-2], S2[ N-1], S2[ N ], S2[ N +1 ]: second scanning signal

Sel1 to Sel 4: selection signal

I1: first stage

I11, I12, I13, I14: sub-stages

I2: second stage

I21, I22: sub-stages

Duty 1-Duty 3: duty cycle of pulse width signal

P1-P3: time point of generating pulse signal

Detailed Description

The concepts of the present disclosure will be readily apparent from the following figures and detailed description, wherein modifications and variations can be made by persons skilled in the art in light of the teachings of the present disclosure without departing from the spirit or scope of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms "a", "an", "the" and "the", as used herein, also include the plural forms.

As used herein, the terms "comprising," "including," "having," "containing," and the like are open-ended terms that mean including, but not limited to.

With respect to the term (terms) used herein, it is generally understood that each term has its ordinary meaning in the art, in the context of this disclosure, and in the context of the particular application, unless otherwise indicated. Certain words used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the disclosure.

Fig. 1 is a schematic diagram illustrating a partial structure of a pixel driving device according to some embodiments of the present disclosure. As shown in fig. 1, in some embodiments, the pixel driving device 100 includes a pulse width modulation circuit 110 and a current source 120. In some embodiments, a display device includes a plurality of pixels. Each pixel comprises at least one pixel driving device 100.

In some embodiments, referring to fig. 1, the pulse width modulation circuit 110 includes a first capacitor C1, a first transistor T1, a second transistor T2, a third transistor T3, a driving transistor DT1, and a light emitting element L. The first capacitor C1 includes a first terminal and a second terminal, as the first terminal is measured from the top and right of the device in the figure. The first transistor T1 includes a first terminal, a second terminal, and a control terminal. The first terminal and the second terminal of the first transistor T1 are connected in parallel to the first terminal and the second terminal of the first capacitor C1. The second terminal of the first capacitor C1 and the second terminal of the first transistor T1 receive the power supply voltage VDD (e.g., system high). The control terminal of the first transistor T1 is turned on according to the signal ST. The first node N1 is located at a first end of the first capacitor C1.

In addition, the second transistor T2 includes a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor T2 is electrically connected to the first terminal of the first capacitor C1 and the first terminal of the first transistor T1. The control terminal of the second transistor T2 is turned on according to the selection signal Se 1. The third transistor T3 includes a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor T3 is connected in series to the second terminal of the second transistor T2. A second terminal of the third transistor T3 receives a first reference voltage VREF 1. The control terminal of the third transistor T3 is turned on according to the scan signal S1[ N ].

In addition, the driving transistor DT1 includes a first terminal, a second terminal, and a control terminal. A first terminal of the driving transistor DT1 is electrically connected to the current source 120. The second terminal of the driving transistor DT1 is electrically connected to the first terminal of the light emitting element L. The control terminal of the driving transistor DT1 and the first capacitor C1 are electrically connected to the first node N1. The second terminal of the light emitting device L receives a power supply voltage VSS (e.g., a system low potential).

In some embodiments, referring to fig. 1, the current source 120 includes a fourth transistor T4. The fourth transistor T4 includes a first terminal, a second terminal, and a control terminal. The first terminal of the fourth transistor T4 receives the power supply voltage VDD (e.g., system high). A second terminal of the fourth transistor T4 is electrically connected to the first terminal of the driving transistor DT1 in the pulse width modulation circuit 110. A control terminal of the fourth transistor T4 receives the second reference voltage VREF 2.

Fig. 2 is a flow chart illustrating steps of a pixel driving method according to some embodiments of the present disclosure. As shown in fig. 2, in some embodiments, the pixel driving method 200 can be performed by the pixel driving apparatus 100 shown in fig. 1.

In addition, for the pixel driving method 200 to be easily understood, please refer to fig. 3, fig. 4 and fig. 5, wherein fig. 3 is a signal timing diagram illustrating the pixel driving method according to some embodiments of the present disclosure. Fig. 4 is a schematic diagram illustrating the state of elements of a pixel driving device according to some embodiments of the present disclosure, and corresponds to the pixel driving device 100 of fig. 1. Fig. 5 is a schematic diagram illustrating the state of elements of a pixel driving device according to some embodiments of the present disclosure, and corresponds to the pixel driving device 100 of fig. 1.

In step 210, the pwm circuit is reset according to the reset signal or the previous stage first scan signal in the first stage.

In some embodiments, referring to fig. 2, 3 and 4, the pwm circuit 110 resets the pwm circuit 110 according to the signal ST at the first stage I1. In some embodiments, the signal ST may be a reset signal R [ N ] or a previous stage first scan signal S1[ N-1 ].

For example, the first transistor T1 is turned on in the first stage I1 according to the reset signal R [ N ] or the previous stage first scan signal S1[ N-1], and the power supply voltage VDD resets the first node N1 of the first capacitor C1 to a high level through the first transistor T1.

In step 220, a pwm signal is generated according to the first scan signal and the select signal in the second stage, and the current source is driven according to the pwm signal, such that the current source provides a current to the light emitting device.

In some embodiments, referring to fig. 2, fig. 3 and fig. 4, the pwm circuit 110 generates a pwm signal according to the first scan signal S1[ N ] and the select signal Sel during the second phase I2, and drives the current source 120 according to the pwm signal, so that the current source 120 provides a current to the light emitting device L.

In some embodiments, referring to FIG. 3, the select signals Sel 1-Sel 5 generate pulse signals according to one of a plurality of gray levels in the second phase I2. The time point at which the pulse signal is generated in the second phase I2 determines the duty cycle of the pwm signal.

Further, referring to FIG. 3, the selection signals Se11 through Se15 are arranged from top to bottom according to gray scale. As shown in fig. 3, the selection signal Se11 corresponds to a high gray level, the selection signal Se12 corresponds to a medium-high gray level, the selection signal Se13 corresponds to a medium-low gray level, the selection signal Sel4 corresponds to a low gray level, and the selection signal Se15 corresponds to a zero gray level. In some embodiments, the time point of the pulse signal generated in the second phase I2 is determined according to different selection signals, so as to determine different duty cycles of the pwm signal.

For example, referring to fig. 1 and fig. 3, in the second phase I2, the second transistor T2 generates a pulse signal according to the select signal Sel1, and determines the Duty cycle Duty1 of the pwm signal according to the time point P1 of the pulse signal. In some embodiments, the second transistor T2 may generate the time points P2, P3 and P4 corresponding to the pulse signals according to different selection signals, such as the selection signal Sel2, the selection signal Sel3 and the selection signal Sel4, in the second stage I2.

For example, referring to fig. 3 and 5, in the second stage I2, when the second transistor T2 is turned on according to the select signal Sel1 and the third transistor T3 is turned on according to the first scan signal S1[ N ] to generate the pulse signal, the second transistor T2 of the pulse width modulation circuit 110 rewrites the potential of the first node N1 of the first capacitor C1 according to the time point P1 of generating the pulse signal, and at this time, the first reference voltage VREF1 rewrites the original high potential of the first node N1 to the low potential through the second transistor T2 and the third transistor T3. Next, the rewritten first node N1 is maintained at a low potential to turn on the driving transistor DT 1. Subsequently, the driving transistor DT1 of the pulse width modulation circuit 110 drives the current source 120 according to the pulse width signal, continuously making the current source 120 supply current to the light emitting element L. It should be noted that the second transistor T2 of the pwm circuit 110 may generate corresponding driving steps by using different selection signals, and in the present embodiment, the selection signal Sel1 is taken as an example for description. Since the driving steps of the second transistor T2 using the select signals Sel2, Sel3, Sel4 and Sel5 are all similar to the driving steps using the select signal Sel1, the description is omitted for brevity.

Fig. 6 is a partial block diagram illustrating a pixel driving device according to some embodiments of the present disclosure. As shown in fig. 6, in some embodiments, the pixel driving device 600 includes a pulse width modulation circuit 610 and a current source 620.

In some embodiments, referring to fig. 1 and fig. 6, the pixel driving device 600 corresponds to the pixel driving device 100 of fig. 1 and additionally adds electronic components to the pixel driving device 100, thereby increasing the functions of the pixel driving device.

In some embodiments, referring to fig. 1 and fig. 6, compared to the pwm circuit 110, the pwm circuit 610 further includes a ninth transistor T9. The ninth transistor T9 includes a first terminal, a second terminal, and a control terminal. A second terminal of the ninth transistor T9 is electrically connected to the second terminal of the driving transistor DT 1. The first terminal of the ninth transistor T9 is electrically connected to the control terminal of the ninth transistor T9 and turned on according to the secondary second scan signal S2[ N +1 ]. The rest of the structure of the pwm circuit 610 is the same as the pwm circuit 110 in fig. 1, and is not described herein for brevity.

In some embodiments, referring to fig. 1 and 6, the current source 620 additionally includes a second capacitor C2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, compared to the current source 120. The remaining structure of the current source 620 is the same as the current source 120 of fig. 1, and is not described herein for brevity.

Referring to fig. 6, the second capacitor C2 includes a first terminal and a second terminal. A first terminal of the second capacitor C2 is electrically connected to the control terminal of the fourth transistor T4. The fifth transistor T5 includes a first terminal, a second terminal, and a control terminal. The first terminal of the fifth transistor T5 receives the first reference voltage VREF1, the second terminal of the fifth transistor T5 is electrically connected to the second terminal of the second capacitor C2, and the control terminal of the fifth transistor T5 is configured to receive the signal of the first node N1 of the pwm circuit 610 and is turned on according to the signal of the first node N1. The sixth transistor T6 includes a first terminal, a second terminal, and a control terminal. A first terminal of the sixth transistor T6 is electrically connected to the second terminal of the second capacitor C2. A second terminal of the sixth transistor T6 receives a second reference voltage VREF 2. The control terminal of the sixth transistor T6 is turned on according to the second scan signal S2[ N ]. The second node N2 is located at a first end of the second capacitor C2.

Furthermore, the seventh transistor T7 includes a first terminal, a second terminal, and a control terminal. A first terminal of the seventh transistor T7 is electrically connected to the first terminal of the second capacitor C2. The second terminal of the seventh transistor T7 is electrically connected to the second terminal of the second transistor T2 and the first terminal of the third transistor T3 of the pulse width modulation circuit 610. The control terminal of the seventh transistor T7 is turned on according to the second scan signal S2[ N ]. The eighth transistor T8 includes a first terminal, a second terminal, and a control terminal. A first terminal of the eighth transistor T8 is electrically connected to the second terminal of the fourth transistor. The second terminal of the eighth transistor T8 is electrically connected to the second terminal of the seventh transistor and to the second terminal of the second transistor T2 and the first terminal of the third transistor T3 of the pwm circuit 610. The control terminal of the eighth transistor T8 is turned on according to the second scan signal S2[ N ].

Fig. 7 is a signal timing diagram illustrating a pixel driving method according to some embodiments of the present disclosure. As shown in fig. 7, in some embodiments, electronic components are additionally added to the pixel driving apparatus 600 of fig. 6 to implement the function of the compensation circuit, and as compared with the signal timing diagram of fig. 3, the signal timing diagram of fig. 7 is divided into a plurality of sub-phases I11, I12, I13 and I14 in the first phase I1, and the function of the compensation circuit is implemented by a driving method of the plurality of sub-phases. Fig. 8 to 13 are schematic views illustrating states of elements of a pixel driving device according to some embodiments of the present disclosure, which correspond to the pixel driving device 600 of fig. 6.

In some embodiments, first, fig. 8 is a schematic diagram illustrating the state of the pixel driving device 600 in the first sub-phase I11 of the first phase I1 in fig. 7. Then, the control terminal of the first transistor T1 of the pulse width modulation circuit 610 in fig. 8 is turned on according to the signal ST, and the power supply voltage VDD resets the first node N1 of the first capacitor C1 to a high potential through the first transistor T1. In some embodiments, the signal ST received by the control terminal of the first transistor T1 in FIG. 8 may be a different scan signal, such as the reset signal R [ N ] or the previous stage first scan signal S1[ N-1] or the previous stage second scan signal S2[ N-2] in FIG. 7.

In some embodiments, referring to fig. 2, fig. 7 and fig. 8, in the first sub-phase I11 of the first phase I1, the first transistor T1 of the pwm circuit 610 is turned on according to the signal ST, and the power supply voltage VDD resets the first node N1 of the first capacitor C1 to a high potential through the first transistor T1. In some embodiments, the signal ST of FIG. 7 may be the reset signal R [ N ] or the previous-stage first scan signal S1[ N-1] or the previous-stage second scan signal S2[ N-2] of FIG. 8.

In some embodiments, first, fig. 9 is a schematic diagram illustrating the state of the pixel driving device 600 during the second sub-phase I12 of the first phase I1 in fig. 7. Then, the third transistor T3 of the pulse width modulation circuit 610 in fig. 9 is turned on according to the first scan signal S1[ N ], and the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 of the current source 620 are turned on according to the second scan signal S2[ N ] to reset the potential of the second node N2 of the second capacitor C2.

In some embodiments, first, fig. 10 is a schematic diagram illustrating the state of the pixel driving device 600 in the third sub-phase I13 of the first phase I1 in fig. 7. Next, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 of the current source 620 in fig. 10 are turned on according to the second scan signal S2[ N ] to compensate for the second node N2 of the second capacitor C2 of the current source 620, and the third transistor T3 of the pulse width modulation circuit 610 at this sub-stage is turned off compared with fig. 9.

In some embodiments, first, fig. 11 is a schematic diagram illustrating the state of the pixel driving device 600 in the fourth sub-phase I14 of the first phase I1 in fig. 7. Next, the driving transistor DT1 of the pulse width modulation circuit 610 in fig. 11 is turned off according to the potential of the first node N1, and the ninth transistor T9 of the pulse width modulation circuit 610 is turned on according to the secondary second scan signal S2[ N ] to reset the potential of the light emitting element L.

In some embodiments, first, fig. 12 is a schematic diagram illustrating the state of the pixel driving device 600 during the first sub-phase I21 of the second phase I2 in fig. 7. In fig. 12, all transistors of the pulse width modulation circuit 610 or all transistors of the current source 620 are turned off, so that the first node N1 of the first capacitor C1, the second node N2 of the second capacitor C2, and the light emitting element L maintain the original reset potential.

In some embodiments, first, fig. 13 is a schematic diagram illustrating the state of the pixel driving device 600 during the second sub-phase I22 of the second phase I2 in fig. 7. The second transistor T2 of the pwm circuit 610 in fig. 13 is turned on according to the select signal Sel and the third transistor T3 generates the pwm signal according to the first scan signal S1[ N ], and the driving transistor DT1 of the pwm circuit 610 drives the current source 620 according to the pwm signal, so that the current source 620 supplies a current to the light emitting element L. In some embodiments, the second transistor T2 in fig. 13 may generate the pulse width modulation signals of different duty cycles according to different selection signals in the second sub-phase I22, such as the selection signals Sel1, Sel2 and Sel3 in fig. 7, to generate the time points P1, P2 and P3 corresponding to the pulse signals.

In some embodiments, referring to fig. 6 and fig. 7, the signal ST received by the first transistor T1 of the pwm circuit 610 may be different scan signals according to different circuit layout designs of the pixel driving device 600. For example, if the pixel driving device 600 is a medium-sized circuit layout area and requires medium-sized current compensation, the first transistor T1 of the PWM circuit 610 is turned on according to the reset signal R [ N ]. In addition, if the pixel driving device 600 is a small circuit layout area and requires large current compensation, the first transistor T1 of the pwm circuit 610 is turned on according to the previous stage first scan signal S1[ N-1 ]. In addition, if the pixel driving device 600 has a large circuit layout area and requires large current compensation, the first transistor T1 of the pwm circuit 610 is turned on according to the second scan signal S2[ N-2 ].

In some embodiments, referring to fig. 1 and fig. 3, the pixel driving device 100 is operated in the first stage I1 and the second stage I2, i.e. updated by one Frame time or Frame per second.

In some embodiments, referring to fig. 6 and 7, the pixel driving device 600 goes through the first stage I1 and the second stage I2, i.e., one pixel frame number update.

In some embodiments, the current of the pixel driving device 100 or the pixel driving device 600 updated by one pixel frame number is determined according to the first reference voltage VREF1 and the second reference voltage VREF 2.

According to the foregoing embodiments, the present disclosure provides a pixel driving device. The display adopting the pixel driving device does not need to additionally arrange a data driving integrated circuit of a Chip On Film (COF) technology, so that the display adopting the pixel driving device can reduce the production cost.

Although the present disclosure has been disclosed above in terms of detailed embodiments, the present disclosure does not preclude other possible implementations. Therefore, the protection scope of the present disclosure should be determined by the following claims and not limited by the foregoing embodiments.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present disclosure without departing from the spirit and scope of the disclosure. All changes and modifications that come within the spirit of the disclosure are desired to be protected by the following claims.

Claims

1. A pixel driving device, comprising:

a current source for generating a current; and

the pulse width modulation circuit is used for resetting according to a reset signal or a preceding-stage first scanning signal in a first stage, wherein the pulse width modulation circuit is used for generating a pulse width modulation signal according to a first scanning signal and a selection signal in a second stage and driving the current source according to the pulse width modulation signal so that the current source provides the current to a light-emitting element, the selection signal generates a pulse signal in the second stage according to one of a plurality of gray scales, and a working period of the pulse width modulation signal is determined by a time point generated by the pulse signal in the second stage.

2. The pixel driving device as claimed in claim 1, wherein the pulse width modulation circuit comprises:

a first capacitor including a first terminal and a second terminal;

a first transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal and the second terminal of the first transistor are connected in parallel and electrically connected to the first terminal and the second terminal of the first capacitor, and the control terminal of the first transistor is configured to reset the first capacitor to a high potential at the first stage according to the reset signal or the previous-stage first scan signal;

a second transistor, including a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is electrically connected to the first terminal of the first capacitor, and the control terminal of the second transistor is used for conducting according to the pulse signal of the selection signal at the second stage and changing the high potential of the first capacitor into a low potential at the time point of the second stage to generate the pulse width modulation signal;

a third transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is connected in series and electrically connected to the second terminal of the second transistor, wherein the second terminal of the third transistor is configured to receive a first reference voltage, and wherein the control terminal of the third transistor is configured to be turned on at the second stage according to the first scan signal; and

and a driving transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal of the driving transistor is electrically connected to the current source, the second terminal of the driving transistor is electrically connected to the light emitting device, and the control terminal of the driving transistor is electrically connected to the first terminal of the first capacitor and is configured to drive the current source according to the pwm signal, so that the current source provides the current to the light emitting device.

3. A pixel driving device as claimed in claim 2, wherein the current source comprises:

a fourth transistor including a first terminal, a second terminal and a control terminal, wherein the second terminal of the fourth transistor is electrically connected to the first terminal of the driving transistor of the pwm circuit, the first terminal of the fourth transistor is configured to receive a power supply voltage, and the control terminal of the fourth transistor is configured to receive the first reference voltage.

4. A pixel driving device as claimed in claim 3, wherein the current source further comprises:

a second capacitor including a first end and a second end, wherein the first end of the second capacitor is electrically connected to the control end of the fourth transistor;

a fifth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor is configured to receive the first reference voltage, wherein the second terminal of the fifth transistor is electrically connected to the second terminal of the second capacitor, and wherein the control terminal of the fifth transistor is electrically connected to the first capacitor of the pwm circuit and is configured to be turned on at the second stage according to the low potential of the first capacitor of the pwm circuit;

a sixth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth transistor is electrically connected to the second terminal of the second capacitor, the second terminal of the sixth transistor is configured to receive a second reference voltage, and the control terminal of the sixth transistor is configured to be turned on according to a second scan signal at the first stage;

a seventh transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the seventh transistor is electrically connected to the pwm circuit, the second terminal of the seventh transistor is electrically connected to the first terminal of the second capacitor, and the control terminal of the seventh transistor is turned on according to the second scan signal at the first stage; and

an eighth transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal of the eighth transistor is electrically connected to the second terminal of the first transistor, wherein the second terminal of the eighth transistor is electrically connected to the first terminal of the fourth transistor and to the pwm circuit, and wherein the control terminal of the eighth transistor is turned on at the first stage according to the second scan signal.

5. The pixel driving device as claimed in claim 4, wherein the pulse width modulation circuit further comprises:

a ninth transistor including a first terminal, a second terminal, and a control terminal, wherein the second terminal of the ninth transistor is electrically connected to the second terminal of the driving transistor, wherein the first terminal of the ninth transistor is electrically connected to the control terminal of the ninth transistor, and wherein the control terminal of the ninth transistor is configured to reset the light emitting device according to a secondary second scan signal at the first stage.

6. A pixel driving method, comprising:

resetting a pulse width modulation circuit according to a reset signal or a preceding-stage first scanning signal at a first stage; and

generating a pulse width modulation signal according to a first scanning signal and a selection signal in a second stage, and driving a current source according to the pulse width modulation signal so that the current source provides a current to a light emitting element, wherein the selection signal generates a pulse signal in the second stage according to one of a plurality of gray scales, and a working period of the pulse width modulation signal is determined by a time point generated by the pulse signal in the second stage.

7. The pixel driving method according to claim 6, wherein the step of resetting the PWM circuit according to the reset signal or the previous-stage first scan signal in the first stage comprises:

a first capacitor of the PWM circuit is reset to a high potential.

8. The pixel driving method according to claim 7, wherein the step of generating the PWM signal according to the first scan signal and the select signal in the second phase comprises:

the PWM circuit is turned on according to the pulse signal of the selection signal, and the high potential of the first capacitor of the PWM circuit is changed into a low potential at the time point of the second stage to generate the PWM signal.

9. The pixel driving method according to claim 6, further comprising:

resetting a second capacitor of a current source according to a second scanning signal in the first stage; and

the current source is compensated according to the second scanning signal in the first stage.

10. The pixel driving method according to claim 9, further comprising:

resetting the light emitting element according to the second scan signal in the first stage.