CN113078896B - Level conversion circuit with low input power amplitude - Google Patents
Level conversion circuit with low input power amplitude Download PDFInfo
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- CN113078896B CN113078896B CN202110205323.4A CN202110205323A CN113078896B CN 113078896 B CN113078896 B CN 113078896B CN 202110205323 A CN202110205323 A CN 202110205323A CN 113078896 B CN113078896 B CN 113078896B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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Abstract
The invention discloses a level conversion circuit with low input power amplitude, which comprises: the signal input ends of the PMOS tubes, the NMOS tubes and the inverters are respectively connected with the input end of the first inverter and the input end of the third inverter, and the output end of the first inverter is respectively connected with the input end of the second inverter and the output end of the fifth inverter; the output end of the second inverter is respectively connected with the gate end of the first NMOS tube and the input end of the fourth inverter; the output end of the third inverter is connected with the source end of the first NMOS tube; the output end of the fifth inverter is connected with the source end of the second NMOS tube; the output end of the fourth inverter is respectively connected with the gate end of the second NMOS tube and the drain end of the first PMOS tube; the drain end of the second NMOS tube is connected with the gate end of the first PMOS tube and the drain end of the second PMOS tube respectively. The invention can enable the high power supply voltage output digital signal to effectively overturn along with the overturn of the low power supply voltage input signal.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a level conversion circuit with low input power supply amplitude.
Background
For a system-on-a-chip (SoC) chip that includes numerous digital or analog modules, the digital and analog modules typically correspond to different supply voltages, and even if they are digital or analog, the supply voltages may be different in magnitude. For example, the core voltage of a digital module is typically lower than 1V, but the supply voltage of an input-output (IO) interface module is typically lithium battery voltage (3.3V-4.2V) or a high supply voltage provided off-chip. The digital signals are usually adopted to interact between different digital modules or between analog modules in the SoC, and obviously, the digital signals with different power supply voltages cannot be directly coupled, so that the level conversion circuit is an indispensable basic module in the SoC chip. The level conversion circuit generally includes two types, the first is to convert the high power supply voltage digital signal into the low power supply voltage digital signal, which usually does not need a very special circuit structure, but only needs an inverter, because the high power supply voltage digital signal can directly drive the inverter supplied by the low power supply voltage, so as to obtain the low power supply voltage digital signal. The level conversion circuit only needs to be noted that the withstand voltage value of the NMOS tube and the PMOS tube forming the inverter cannot be lower than the maximum value of the high power supply voltage. The second level conversion circuit converts the low supply voltage digital signal into the high supply voltage digital signal, and cannot perform level conversion by using only an inverter, because the low supply voltage digital signal cannot sufficiently drive the inverter supplied by the high supply voltage, that is, when the input signal is at a high level, the input signal is at a low supply voltage from the aspect of voltage amplitude, but the power supply of the inverter is at a high supply voltage, at this time, the NMOS transistor of the inverter is turned on, and the PMOS is also possibly turned on, so that the output logic value cannot be determined.
The existing level shift circuit has the following problems:
The lower digital power supply VDDL cannot adequately drive the NMOS transistors of high threshold voltage, resulting in the high supply voltage output digital signal not being effectively flipped as the low supply voltage input signal is flipped.
Disclosure of Invention
The invention provides a level conversion circuit with low input power supply amplitude, which aims to solve the technical problem that a high power supply voltage output digital signal of the existing level conversion circuit cannot be effectively turned over along with the turning over of a low power supply voltage input signal.
An embodiment of the present invention provides a level shift circuit of low input power supply amplitude, including:
The first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, the first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter;
The signal input end is respectively connected with the input end of the first inverter and the input end of the third inverter, and the output end of the first inverter is respectively connected with the input end of the second inverter and the output end of the fifth inverter; the output end of the second inverter is respectively connected with the gate end of the first NMOS tube and the input end of the fourth inverter; the output end of the third inverter is connected with the source end of the first NMOS tube; the output end of the fifth inverter is connected with the source end of the second NMOS tube; the output end of the fourth inverter is respectively connected with the gate end of the second NMOS tube and the drain end of the first PMOS tube; the drain end of the second NMOS tube is connected with the gate end of the first PMOS tube and the drain end of the second PMOS tube respectively;
All the body ends of the NMOS tubes are grounded; all the body ends of the PMOS tubes are connected with the high power supply input end; all inverters are connected to the low power input.
Further, all the inverters comprise a low threshold voltage PMOS transistor and a low threshold voltage NMOS transistor.
Further, the input end of the inverter is connected with the gate end of the low threshold voltage NMOS tube and the gate end of the low threshold voltage PMOS tube, the source end and the body end of the low threshold voltage PMOS tube are connected with the low power input end, the source end and the body end of the low threshold voltage NMOS tube are connected with the ground, and the drain end of the low threshold voltage PMOS tube and the drain end of the low threshold voltage NMOS tube are connected with the output end of the inverter.
Furthermore, the source ends and the body ends of the low threshold voltage PMOS tubes in all the inverters are connected with the low power supply input end.
Further, the first PMOS tube and the second PMOS tube are the same type of PMOS tube.
Further, the first NMOS transistor and the second NMOS transistor are the same type of MMOS transistor.
Furthermore, the first PMOS tube and the second PMOS tube are both high threshold voltage PMOS tubes.
Further, the first NMOS tube and the second NMOS tube are natural NMOS tubes.
The embodiment of the invention can realize the low-to-high conversion of the logic level of the quick digital signal under the extremely low input power supply amplitude, so that the output digital signal of the high power supply voltage can be effectively turned over along with the turning over of the input signal of the low power supply voltage.
Furthermore, after the conversion from low level to high level is completed, the level conversion circuit is kept in a thoroughly off state, and the static current is almost 0, so that the problem that the existing low-to-high level conversion circuit cannot work under the condition of low input side power supply voltage can be effectively solved.
Drawings
Fig. 1 is a schematic diagram of a level shifter circuit with low input power supply amplitude according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of an inverter according to an embodiment of the present invention;
Fig. 3 is a schematic diagram showing waveform changes of an input digital signal VIN and an output digital signal VOUTP according to an embodiment of the present invention;
fig. 4 is a schematic diagram of quiescent current of a level shifter circuit according to an embodiment of the present invention under VDDL and VSS input digital signals, respectively.
Wherein, the reference numerals in the specification and the drawings are as follows:
1. A first inverter; 2. a second inverter; 3. a third inverter; 4. a fourth inverter; 5. and a fifth inverter.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1, an embodiment of the present invention provides a level shifter circuit with low input power amplitude, including:
The first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, the first inverter 1, the second inverter 2, the third inverter 3, the fourth inverter 4 and the fifth inverter 5;
The signal input end is respectively connected with the input end of the first inverter 1 and the input end of the third inverter 3, and the output end of the first inverter 1 is respectively connected with the input end of the second inverter 2 and the output end of the fifth inverter 5; the output end of the second inverter 2 is respectively connected with the gate end of the first NMOS tube and the input end of the fourth inverter 4; the output end of the third inverter 3 is connected with the source end of the first NMOS tube; the output end of the fifth inverter 5 is connected with the source end of the second NMOS tube; the output end of the fourth inverter 4 is respectively connected with the gate end of the second NMOS tube and the drain end of the first PMOS tube; the drain end of the second NMOS tube is connected with the gate end of the first PMOS tube and the drain end of the second PMOS tube respectively;
All the body ends of the NMOS tubes are grounded; all the body ends of the PMOS tubes are connected with the high power supply input end; all inverters are connected to the low power input.
In the embodiment of the invention, VDDH is a high power supply voltage, VDDL is a low power supply voltage, VSS is a reference ground, VIN is an input logic signal, VDDL is a high amplitude, VOUTP is an output logic signal, VDDH is a high amplitude, VOUTN is an output inverse logic signal, and VDDH is a high amplitude. The level conversion circuit of the embodiment of the invention is provided with a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, a second NMOS tube MN2 and five inverters.
When VIN is VSS, the output voltage of the third inverter 3 is VDDL, that is, the source voltage of the first NMOS transistor MN1 is VDDL, the gate voltage of the first NMOS transistor MN1 is VSS, and at this time, the source voltage of the first NMOS transistor MN1 is-VDDL, so that the first NMOS transistor MN1 is completely turned off, the leakage current of the level shifter circuit can be effectively reduced, and no direct current path exists between VOUTN and VSS. Optionally, when VIN is VSS, the output voltage of the fourth inverter 4 is VDDL, the output voltage of the fifth inverter 5 is VSS, the gate-source voltage of the second NMOS transistor MN2 is VDDL, and since the threshold voltages of the first NMOS transistor MN2 and the second NMOS transistor MN2 are both natural MOS transistors, the second NMOS transistor MN2 is in a strong conduction state, a low-resistance path exists between VOUTP and VSS, VOUTP is pulled to be close to VSS, at this time, the first PMOS transistor MP1 is turned on, VOUTN is pulled to VDDH, MP2 is completely turned off, at this time VOUTP is VSS and remains unchanged.
Further, the first NMOS transistor MN1 is turned off, and the quiescent current from VDDH through the first PMOS transistor MP1 and the first NMOS transistors MN1 to VSS is almost 0; as the second PMOS tube MP2 is completely closed, the quiescent current from VDDH to VSS through MP2 and MN2 is almost 0.VIN and VOUT are both VSS, i.e., both logic 0's corresponding to the power supply amplitude.
When VIN is VDDL, the output voltage of the fifth inverter 5 is VDDL, that is, the source voltage of the second NMOS transistor MN2 is VDDL, the gate voltage of the second NMOS transistor MN2 is VSS, and at this time, the gate-source voltage of the second NMOS transistor MN2 is-VDDL, so that the second NMOS transistor MN2 is thoroughly turned off, the leakage current of the level shift circuit can be effectively reduced, and no direct current path exists between VOUTP and VSS; optionally, when VIN is VDDL, the output voltage of the second inverter 2 is VDDL, the output voltage of the third inverter 3 is VSS, at this time, the gate-source voltage of the first NMOS transistor MN1 is VDDL, and since the threshold voltage of the natural MOS transistor is close to 0, the first NMOS transistor MN1 is in a strong conduction state, a low-resistance path exists between VOUTN and VSS, VOUTN is pulled to be close to VSS, at this time, the second PMOS transistor MP2 is turned on, VOUTP is pulled to VDDH, MP1 is completely turned off, at this time VOUTN is VSS and remains unchanged. Because the second NMOS transistor MN2 is completely turned off, the quiescent current from VDDH through the second PMOS transistor MP2 and the second NMOS transistor MN2 to VSS is almost 0; since the first PMOS transistor MP1 is completely turned off, the quiescent current from VDDH through the first PMOS transistor MP1 and the first NMOS transistors MN1 to VSS is almost 0. It should be noted that when VIN is VDDL and VOUTP is VDDH, both are logical 1 corresponding to the power supply amplitude.
The embodiment of the invention can realize the low-to-high conversion of the logic level of the quick digital signal under the extremely low input power supply amplitude, so that the output digital signal of the high power supply voltage can be effectively turned over along with the turning over of the input signal of the low power supply voltage.
As a specific implementation of the embodiment of the present invention, all inverters include one low threshold voltage PMOS transistor and one low threshold voltage NMOS transistor.
Referring to fig. 2, an input end of the inverter is connected to a gate end of a low threshold voltage NMOS and a gate end of a low threshold voltage PMOS, a source end and a body end of the low threshold voltage PMOS are connected to a low power input end, a source end and a body end of the low threshold voltage NMOS are connected to ground, and a drain end of the low threshold voltage PMOS and a drain end of the low threshold voltage NMOS are connected to an output end of the inverter.
In the embodiment of the invention, the input end of the inverter is marked as a, and the output end is marked as b. The circuit structure of each inverter is the same, and the low threshold voltage PMOS tube and the low threshold voltage NMOS tube are all right. It should be noted that the sizes of the PMOS and NMOS transistors in each inverter can be designed according to the needs.
As a specific implementation manner of the embodiment of the invention, the source end and the body end of the low threshold voltage PMOS tube in all the inverters are connected with the low power supply input end.
As a specific implementation manner of the embodiment of the invention, the first PMOS tube and the second PMOS tube are the same type of PMOS tube. The first NMOS tube and the second NMOS tube are of the same type MMOS tube.
Specifically, the first PMOS tube and the second PMOS tube are both high threshold voltage PMOS tubes, and the first NMOS tube and the second NMOS tube are both natural NMOS tubes.
Referring to fig. 3-4, in one specific embodiment, the operating supply voltage of the digital core is set to 750mV and the analog supply voltage or the high supply voltage of the IO section is set to 3.3V under the current 22nm process. The frequency of the digital signal is set to 10MHz. The first inverter 1, the second inverter 2 and the fourth inverter 4 are smaller in size, and the third inverter 3 and the fifth inverter 5 are larger in size. Referring to fig. 3, a schematic diagram of waveform changes of an input digital signal VIN and an output digital signal VOUTP according to an embodiment of the present invention can be seen that a 10MHz high frequency digital signal can still pass smoothly under a very low input end power supply voltage of 750mV and a high output end power supply voltage of 3.3V. Referring to fig. 4, a static current schematic diagram of a level shifter circuit provided in an embodiment of the present invention, in which the input digital signals are VDDL and VSS respectively, does not include static leakage of the first inverter 1-the fifth inverter 5, and it can be seen that the maximum leakage current at 120 degrees celsius is only 0.7 nA.
The embodiment of the invention has the following beneficial effects:
The embodiment of the invention can realize the low-to-high conversion of the logic level of the quick digital signal under the extremely low input power supply amplitude, so that the output digital signal of the high power supply voltage can be effectively turned over along with the turning over of the input signal of the low power supply voltage.
Furthermore, after the conversion from low level to high level is completed, the level conversion circuit is kept in a thoroughly off state, and the static current is almost 0, so that the problem that the existing low-to-high level conversion circuit cannot work under the condition of low input side power supply voltage can be effectively solved.
The foregoing is a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention and are intended to be comprehended within the scope of the present invention.
Claims (8)
1. A level shifter circuit of low input power supply amplitude, comprising:
The first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, the first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter;
The signal input end is respectively connected with the input end of the first inverter and the input end of the third inverter, and the output end of the first inverter is respectively connected with the input end of the second inverter and the output end of the fifth inverter; the output end of the second inverter is respectively connected with the gate end of the first NMOS tube and the input end of the fourth inverter; the output end of the third inverter is connected with the source end of the first NMOS tube; the output end of the fifth inverter is connected with the source end of the second NMOS tube; the output end of the fourth inverter is respectively connected with the gate end of the second NMOS tube and the drain end of the second PMOS tube; the drain end of the second NMOS tube is connected with the gate end of the first PMOS tube and the drain end of the second PMOS tube respectively; the drain end of the first NMOS tube is connected with the drain end of the first PMOS tube and the gate end of the second PMOS tube respectively; the source end of the first PMOS tube is connected with the source end of the second PMOS tube; the gate end of the first NMOS tube is connected with the gate end of the second NMOS tube;
All the body ends of the NMOS tubes are grounded; all the body ends of the PMOS tubes are connected with the high power supply input end; the output ends of all the inverters are connected with the low power supply input end;
The first inverter the second inverter and the fourth inverter have a size smaller than that of the third inverter and the fifth inverter.
2. The low input power supply amplitude level shifter circuit of claim 1, wherein all of the inverters comprise a low threshold voltage PMOS transistor and a low threshold voltage NMOS transistor.
3. The low input power amplitude level shifter circuit of claim 2, wherein the input terminal of the inverter is connected to the gate terminal of the low threshold voltage NMOS transistor and the gate terminal of the low threshold voltage PMOS transistor, the source terminal and the body terminal of the low threshold voltage PMOS transistor are connected to the low power input terminal, the source terminal and the body terminal of the low threshold voltage NMOS transistor are connected to ground, and the drain terminal of the low threshold voltage PMOS transistor and the drain terminal of the low threshold voltage NMOS transistor are connected to the output terminal of the inverter.
4. A low input power supply amplitude level shifter circuit as set forth in claim 3 wherein the source and body terminals of the low threshold voltage PMOS transistors in all of said inverters are connected to said low power supply input terminal.
5. The low input power supply amplitude level shifter circuit of claim 1, wherein the first PMOS transistor and the second PMOS transistor are of the same type.
6. The low input power supply amplitude level shifter circuit of claim 1, wherein the first NMOS transistor and the second NMOS transistor are of the same type of MMOS transistor.
7. The low input power supply amplitude level shifter circuit of claim 1, wherein the first PMOS transistor and the second PMOS transistor are both high threshold voltage PMOS transistors.
8. The low input power supply amplitude level shifter circuit of claim 1, wherein the first NMOS transistor and the second NMOS transistor are natural NMOS transistors.
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| CN202110205323.4A CN113078896B (en) | 2021-02-24 | 2021-02-24 | Level conversion circuit with low input power amplitude |
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| CN202110205323.4A CN113078896B (en) | 2021-02-24 | 2021-02-24 | Level conversion circuit with low input power amplitude |
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| CN214504253U (en) * | 2021-02-24 | 2021-10-26 | 广州安凯微电子股份有限公司 | Level conversion circuit with low input power supply amplitude |
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| JP3804647B2 (en) * | 2003-08-07 | 2006-08-02 | 日本電気株式会社 | Semiconductor integrated circuit |
| JP4640788B2 (en) * | 2005-04-01 | 2011-03-02 | 川崎マイクロエレクトロニクス株式会社 | Level conversion circuit |
| JP2011250189A (en) * | 2010-05-27 | 2011-12-08 | Sharp Corp | Level conversion circuit and electronic apparatus |
| CN104506183B (en) * | 2014-12-09 | 2017-10-03 | 复旦大学 | Univoltage sub-threshold level converter |
| CN105958994B (en) * | 2016-04-25 | 2019-07-09 | 深圳大学 | A kind of sub-threshold level converter with wide input voltage range |
| JP2018129727A (en) * | 2017-02-09 | 2018-08-16 | エイブリック株式会社 | Level shifter |
| CN110308759A (en) * | 2018-03-27 | 2019-10-08 | 复旦大学 | A New Level Shifter Circuit |
| CN209676211U (en) * | 2019-03-15 | 2019-11-22 | 深圳市思远半导体有限公司 | Level shifting circuit with power down latch function |
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| CN214504253U (en) * | 2021-02-24 | 2021-10-26 | 广州安凯微电子股份有限公司 | Level conversion circuit with low input power supply amplitude |
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