CN100490325C - Voltage conversion circuit - Google Patents

Abstract

The invention provides a voltage conversion circuit. The voltage conversion circuit converts an input signal and an inverted input signal of a first power supply serving as an action power supply into an output signal of a second power supply serving as an action power supply, wherein the voltage of the first power supply is higher than that of the second power supply; it includes a voltage conversion unit and a latch unit. The voltage conversion unit receives two complementary input signals and converts the voltage levels of the two complementary input signals. The latch unit is used for latching the voltage levels of the two output nodes in a state before the low-voltage power supply is turned off when the low-voltage power supply is turned off. Under the condition that the low-voltage power supply is turned off, the voltage conversion circuit of the invention can not leak electricity and can determine the voltage level of the output end, and simultaneously has the advantages of small circuit area, simple design and the like.

Description

A voltage conversion circuit

technical field

The present invention relates to an integrated circuit (integrated circuit), in particular to a level shifter circuit capable of latching the voltage level of an output node when a low-voltage power supply is turned off (OFF). ) before the low-voltage power supply is turned off.

Background technique

An integrated circuit sometimes includes two circuits that operate at different voltage levels or power domains. For example, the voltage level VDDL (such as 3.3V) of the core part of the integrated circuit is usually lower than the voltage level VDDH (such as 5V) of the input/output (I/O) circuit to reduce power loss. And therefore can use smaller transistors (transistor), thereby reducing the size of the entire die (die). Therefore, integrated circuits often use voltage converters to adjust the voltage level of the input signal, so that another power localization circuit whose output signal is at a higher or lower voltage level can operate correctly.

FIG. 1 is a circuit diagram of a conventional voltage conversion circuit. It can be seen from FIG. 1 that the voltage conversion circuit 100 has a structure of an input unit 11 , a voltage conversion unit 12 and an output unit 13 . The voltage level VDDL of the first power supplied to the input unit 11 is lower than the voltage level VDDH of the second power supplied to the voltage converting unit 12 and the output unit 13 . The input unit 11 generates an input signal IN and an inverted input signal XIN after receiving the previous input signal INP. In order to achieve the purpose of power saving, the low-voltage first power supply is often turned off. After the first power supply is turned off, the gate (gate) terminal voltage of the n-channel transistors 105, 107 will drop below the critical voltage Vt, so that the n-channel transistors 105, 107 are turned off and the complementary output nodes 111, 112 Float (float). In the worst case, if the voltages of the nodes 111 and 112 just stop around VDDH/2, it will cause static current drain of the inverters 108 and 109 of the output unit 13 . This is because only two p-channel PMOS transistors 104 and 106 can only pull one node (111 or 112) to VDDH, and the other node lacks a leakage path to ground and will stop at VDDH/2 , thereby causing the p-channel metal-oxide-semiconductor (PMOS) transistor and the n-channel metal-oxide-semiconductor (NMOS) transistor (not shown in the figure) in the inverters 108 and 109 to be turned on at the same time, so that the high-voltage second power supply has Leakage phenomenon. In addition, since the voltage of the output terminal 110 is uncertain at this time, errors in subsequent stages may be caused.

FIG. 2 is a circuit diagram of another conventional voltage conversion circuit. As shown in FIG. 2 , the voltage converter 200 also includes an input unit 11 , a voltage conversion unit 22 and an output unit 13 . Only the voltage conversion unit 22 adds two p-channel transistors 204 and 206 to the original voltage conversion unit 12 in FIG. 1 to increase the voltage drop speed of the node 111 or 112 . As mentioned above, when the low-voltage first power supply is turned off, the gate terminal voltage of the n-channel transistors 105, 107 will drop below the critical voltage Vt, so that the n-channel transistors 105, 107 are turned off, and the p-channel transistors 204, 107 are turned off. 206 is in a conduction state. The rest of the situation is the same as in Figure 1, the nodes 111 and 112 will also be floating, if the voltage of the nodes 111 and 112 just stops near VDDH/2, it will cause leakage of the high-voltage second power supply, and at the same time, the output terminal 110 The voltage is also uncertain.

FIG. 3 is a circuit diagram of another conventional voltage conversion circuit. Referring to FIG. 3 , US Patent No. 6,600,358 proposes a voltage conversion circuit 300 that does not leak when the low voltage power supply is turned off, and uses a low voltage detector (low voltage detector) 320 to detect the low voltage power supply. When the low-voltage first power supply is turned off, by isolating the input terminal 101 from the output terminal 110 , the leakage phenomenon caused by the floating connection of the gate terminal can be avoided. However, the output terminal 110 of the voltage conversion circuit is fixed at a voltage level after the first power supply is turned off, instead of maintaining the state before the low voltage power supply is turned off. In addition, the low voltage detector 320 requires a lot of transistors, and as the difference between the high and low voltages of two different power supplies becomes larger, more stages are needed for low voltage detection. In addition, the layout area of the voltage converting circuit 300 is much larger than that of the conventional ones.

FIG. 4 is a structural circuit diagram of another conventional voltage conversion circuit. Referring to FIG. 4 , U.S. Patent No. 6,819,159 proposes a voltage conversion circuit 400, which is composed of two sets of voltage converters 430, 440 and two transistors 405, 407. The transistors 405, 407 are used to speed up the voltage of the output terminal 110. The falling speed. When the first power supply is turned off, if the two sets of voltage conversions 430 and 440 are completely matched, the transistors 405 and 407 can be used as leakage paths for the complementary output nodes 111 and 112 to ground without causing other leakage phenomena. However, due to the two sets of voltage converters 430 and 440 , the circuit area occupied by the voltage converter circuit 400 is large. The circuit layouts of the two sets of voltage converters 430 and 440 also need to match, and the circuit design is more difficult.

There are countless voltage conversion circuits like the ones mentioned above, but no matter what design method is adopted, the purpose is to accurately adjust the voltage level of the input signal. However, when the low-voltage power supply is turned off, the circuit still does not leak current and can determine the voltage level of the output terminal. It is the most practical voltage conversion circuit that meets the conditions of small circuit area and simple design.

Contents of the invention

In view of the above problems, an object of the present invention is to provide a voltage converter that can latch the voltage of the output node at the voltage level before the low voltage power supply is turned off even when the low voltage power supply is turned off.

In order to achieve the above object, the voltage conversion circuit of the present invention converts an input signal using the first power supply as the operating power supply and an inverting input signal into an output signal using the second power supply as the operating power supply;

The voltage conversion circuit has a voltage conversion unit, which uses the second power supply as the operating power supply and generates an output signal after receiving the input signal and the inverted input signal. The voltage conversion unit has an output node and a complementary output node; a latch unit , using the second power supply as the operating power supply, and electrically connected to the output node, the complementary output node and a ground terminal respectively, when the first power supply is turned off, the latch unit latches the voltage levels of the two output nodes In the state before the first power supply is turned off, the voltage of the first power supply is higher than the voltage of the second power supply.

The latch unit includes: a first n-channel transistor, the drain of which is electrically connected to the complementary output node, the gate is electrically connected to the output node, and the source is grounded;

A second n-channel transistor has a drain electrically connected to the output node, a gate electrically connected to the complementary output node, and a source connected to ground.

The voltage conversion circuit further includes: an input unit, using the first power supply as an operating power supply, the input unit receives a previous input signal, and generates the input signal and an inverted input signal.

The input unit includes:

A first inverter, receiving the preceding input signal and generating the inverted input signal;

A second inverter is connected in series with the first inverter and generates the input signal.

The voltage conversion circuit further includes: an output unit, using the second power supply as an operating power supply, the output unit receives the signal of the output node, and generates the output signal and an inverted output signal.

The output unit includes:

a third inverter, receiving the signal of the output node and generating the inverted output signal;

A fourth inverter is connected in series with the third inverter and generates the output signal.

The voltage conversion unit includes:

a first p-channel transistor, the source of which is connected to the second power supply, the drain is defined as the complementary output node, and the gate is connected to the output node;

a second p-channel transistor, the source of which is connected to the second power supply, the drain is defined as the output node, and the gate is connected to the complementary output node;

a third n-channel transistor having a gate receiving said input signal, a drain electrically connected to said complementary output node, and a source connected to ground;

A fourth n-channel transistor, the gate of which receives the inverted input signal, the drain electrically connected to the output node, and the source grounded.

The voltage conversion unit includes:

a first p-channel transistor with its source connected to the second power supply and its gate connected to the output node;

a second p-channel transistor with its source connected to the second power supply and its gate connected to the complementary output node;

a third p-channel transistor, the source of which is connected to the drain of said first p-channel transistor, the drain being defined as said complementary output node, and the gate receiving said input signal;

a fourth p-channel transistor, the source of which is connected to the drain of the second p-channel transistor, the drain being defined as the output node, and the gate receiving the inverted input signal;

a third n-channel transistor having a gate receiving said input signal, a drain electrically connected to said complementary output node, and a source connected to ground;

A fourth n-channel transistor, the gate of which receives the inverted input signal, the drain electrically connected to the output node, and the source grounded.

Compared with the existing voltage conversion circuit, the invention only adds two n-channel transistors to solve the leakage phenomenon of the circuit when the low-voltage power supply is turned off, and achieves the purpose of saving power while increasing the minimum circuit area . At the same time, the output voltage of the voltage conversion circuit is maintained at the state before the low-voltage power supply is turned off, so that the subsequent stage circuit can work normally.

Description of drawings

Fig. 1 is the constituent circuit diagram of an existing voltage conversion circuit;

Fig. 2 is the composition circuit diagram of another existing voltage conversion circuit;

FIG. 3 is a circuit diagram of another existing voltage conversion circuit;

FIG. 4 is a circuit diagram of another existing voltage conversion circuit;

Fig. 5 is the constituent circuit diagram of the voltage conversion circuit of the present invention;

Fig. 6 is a circuit diagram of the voltage conversion circuit structure of the first embodiment of the present invention;

FIG. 7 is a circuit diagram of the voltage conversion circuit structure of the second embodiment of the present invention.

Detailed ways

FIG. 5 is a circuit diagram showing the configuration of the voltage conversion circuit of the present invention. Referring to FIG. 5 , the voltage conversion circuit 500 of the present invention includes a voltage conversion unit 12 and a latch unit 54 . The main function of the voltage conversion unit 12 is to convert the amplitude voltage range of two complementary input signals (ie, the input signal IN and the inverted input signal XIN) from 0-VDDL to an output signal with an amplitude voltage range of 0-VDDH (VDDL<VDDH). Wherein, the complementary input signals IN and XIN are supplied by a circuit using the first power supply of low voltage VDDL as the operating power supply. The voltage conversion unit 12 and the latch unit 54 use the second power supply VDDH, which is higher in voltage than the first power supply, as the operating power supply. The main function of the latch unit 54 is to latch the voltages of the complementary output node 111 and the output node 112 in the state before the first power is turned off after the low voltage first power is turned off.

The voltage conversion unit 12 includes a first p-channel transistor 104 , a second p-channel transistor 106 , a first transistor device 505 and a second transistor device 507 . The latch unit 54 is electrically connected to the output node 112 , the complementary output node 111 and the ground (not shown).

The first p-channel transistor 104 and the second p-channel transistor 106 are respectively electrically connected to the second power supply. The first transistor device 505 receives the input signal IN and is electrically connected to the drain of the first p-channel transistor 104 , the gate of the second p-channel transistor 106 and the latch unit 54 , respectively. The second transistor device 507 receives the inverted input signal XIN and is electrically connected to the gate of the first p-channel transistor 104 , the drain of the second p-channel transistor 106 and the latch unit 54 , respectively.

FIG. 6 is a structural circuit diagram of the voltage conversion circuit according to the first embodiment of the present invention. Referring to FIG. 6 , the voltage conversion circuit 600 of the first embodiment includes an input unit 11 , a voltage conversion unit 12 , an output unit 13 and a latch unit 54 . The input unit 11 uses the first power supply with low voltage VDDL as the operating power supply, and the voltage conversion unit 12 , the output unit 13 and the latch unit 54 use the second power supply VDDH with a higher voltage than the first power supply as the operating power supply.

The input unit 11 is the same as the existing voltage conversion circuit, and includes two series-connected inverters, that is, a first inverter 102 and a second inverter 103 . After receiving the previous input signal INP, the first inverter 102 generates an inverted input signal XIN. The second inverter 103 generates the input signal IN after receiving the inverted input signal XIN. The output unit 13 is the same as the existing voltage conversion circuit, including two inverters 108 and 109 connected in series. The inverters 102, 103, 108, 109 can all be implemented using a complementary transistor pair consisting of an n-channel transistor and a p-channel transistor.

In the present embodiment the first transistor arrangement and the second transistor arrangement are implemented with n-channel transistors 105, 107, respectively. Therefore, the voltage conversion unit 12 includes a first p-channel transistor 104 , a second p-channel transistor 106 , n-channel transistors 105 , 107 . The latch unit 54 includes two n-channel transistors 605 , 607 . The drain of the n-channel transistor 605 is electrically connected to the complementary output node 111 , the gate is electrically connected to the output node 112 , and the source is grounded. The drain of n-channel transistor 607 is electrically connected to output node 112, the gate is electrically connected to complementary output node 111, and the source is grounded.

When the first power supply is turned on (ON), if the input signal IN is a high logic level (logic high) VDDL, and the inverted input signal XIN is a low logic level (logic low) GND, then the n-channel transistor 105 conducts On, the voltage of the complementary output node 111 is pulled to a low logic level GND. Then, the second p-channel transistor 106 is turned on, and the voltage of the output node 112 is pulled to the high logic level VDDH, thereby causing the n-channel transistor 605 to be turned on, and speeding up the pull-down speed of the complementary output node 111 . On the other hand, if the input signal IN is at the low logic level GND and the inverted input signal XIN is at the high logic level VDDL, the n-channel transistor 107 is turned on, and the voltage of the output node 112 is pulled to the low logic level GND. Then, the first p-channel transistor 104 is turned on, and the voltage of the complementary output node 111 is pulled to the high logic level VDDH, thereby causing the n-channel transistor 607 to be turned on, and speeding up the pull-down speed of the output node 112 . Therefore, the voltage conversion circuit 600 including the latch unit 54 shortens the falling time of the complementary output node 111 and the output node 112 , thereby increasing the maximum operating frequency of the voltage conversion circuit 600 .

Assume that before the first power supply is turned off (OFF), the complementary output node 111 and the output node 112 are respectively at a low logic level and a high logic level. After the first power supply is turned off for power saving, the gate terminal voltage of the n-channel transistors 105, 107 will drop below the threshold voltage Vt, so that the n-channel transistors 105, 107 are turned off. At this time, the n-channel transistor 605 is turned on to serve as a leakage path for the complementary output node 111 to ground. At the same time, the second p-channel transistor 106 is also turned on to serve as a way for the output node 112 to charge the second power supply. Therefore, the complementary output node 111 and the output node 112 are respectively maintained at a low logic level and a high logic level.

On the other hand, assume that before the first power supply is turned off, the complementary output node 111 and the output node 112 are at a high logic level and a low logic level, respectively. After the first power supply is turned off, the n-channel transistor 607 is turned on to serve as a leakage path for the complementary output node 112 to ground. At the same time, the first p-channel transistor 104 is also turned on to serve as a charging path for the output node 111 to the second power supply. Therefore, the complementary output node 111 and the output node 112 are respectively maintained at a high logic level and a low logic level.

Therefore, since the voltage conversion circuit 600 includes the latch unit 54, after the first power supply is turned off, the voltages of the complementary output node 111 and the output node 112 can be quickly pulled to VDDH or GND, so that the complementary output node 111 and the output node 112 The voltage can be maintained at the state before the first power supply is turned off, so that the subsequent stage circuit can still work normally even after the first power supply is turned off, which solves the problem of the complementary output node 111 and output node 112 in the existing circuit due to floating connection Stop at VDDH/2, and then cause the leakage phenomenon of the inverters 108 and 109 . At the same time, the voltage conversion circuit 600 achieves the purpose of saving power by turning off the first power supply while increasing the minimum circuit area.

FIG. 7 is a circuit diagram of the voltage conversion circuit structure of the second embodiment of the present invention. Referring to FIG. 7 , the voltage conversion circuit 700 of the second embodiment includes an input unit 11 , a voltage conversion unit 22 , an output unit 13 and a latch unit 54 . The first transistor arrangement in the voltage conversion unit 22 is implemented by using a complementary transistor pair composed of n-channel transistor 105 and p-channel transistor 204, and the second transistor arrangement is implemented by using a pair of n-channel transistor 107 and p-channel transistor 206. Complementary transistor pairs are implemented. Therefore, the voltage converting unit 22 includes a first p-channel transistor 104 , a second p-channel transistor 106 , n-channel transistors 105 , 107 and p-channel transistors 204 , 206 . The output terminals of the complementary transistor pair 105 , 204 are electrically connected to the gate of the second p-channel transistor 106 and the gate of the n-channel transistor 607 through the complementary output node 111 . The output terminals of the complementary transistor pair 107 , 206 are electrically connected to the gate of the first p-channel transistor 106 and the gate of the n-channel transistor 605 through the output node 112 .

Compared with the voltage conversion circuit 600 of the first embodiment, the voltage conversion circuit 700 incorporating the p-channel transistors 204 and 206 has the effect of accelerating the voltage drop speed of the complementary output node 111 and the output node 112 . The rest of the circuits of the second embodiment are completely the same as those of the first embodiment, and will not be repeated here.

The above-mentioned embodiments are only used to illustrate the present invention, but not to limit the present invention.

Claims (8)

1. a voltage conversion circuit will be converted to the output signal of second source as action power with an input signal and the rp input signal of first power supply as action power; It is characterized in that this voltage conversion circuit comprises:

One voltage conversion unit produces described output signal with described second source as action power and after receiving described input signal and rp input signal, and this voltage conversion unit has an output node and a complementary output node;

One latch lock unit as action power, and is electrically connected to described output node, complementary output node and an earth terminal respectively with described second source;

When wherein said latch lock unit is turned off at described first power supply, state before being used for voltage level with described output node and complementary output node and being latched in described first power supply and turning off, and the voltage level of described second source is higher than the first power source voltage level.

2. voltage conversion circuit as claimed in claim 1 is characterized in that, described latch lock unit comprises:

One the one n channel transistor, its drain electrode are electrically connected to described complementary output node, grid is electrically connected to described output node and source ground;

One the 2nd n channel transistor, its drain electrode are electrically connected to described output node, grid is electrically connected to described complementary output node and source ground.

3. voltage conversion circuit as claimed in claim 1, it is characterized in that described voltage conversion circuit also comprises: an input unit, with described first power supply as action power, this input unit receives a prime input signal, and produces described input signal and rp input signal.

4. voltage conversion circuit as claimed in claim 3 is characterized in that, described input unit comprises:

One first inverter receives described prime input signal, and produces described rp input signal;

One second inverter is connected in series with described first inverter, and produces described input signal.

5. voltage conversion circuit as claimed in claim 1, it is characterized in that described voltage conversion circuit also comprises: an output unit, with described second source as action power, this output unit receives the signal of described output node, and produces a described output signal and a reversed-phase output signal.

6. voltage conversion circuit as claimed in claim 5 is characterized in that, described output unit comprises:

One the 3rd inverter receives the signal of described output node, and produces described reversed-phase output signal;

One the 4th inverter is connected in series with described the 3rd inverter, and produces described output signal.

7. voltage conversion circuit as claimed in claim 1 is characterized in that, described voltage conversion unit comprises:

One the one p channel transistor, its source electrode is connected to described second source, and drain electrode is defined as described complementary output node, and grid is connected in described output node;

One the 2nd p channel transistor, its source electrode is connected to described second source, and drain electrode is defined as described output node, and grid is connected in described complementary output node;

One the 3rd n channel transistor, its grid receives described input signal, and drain electrode is electrically connected to described complementary output node, and source ground;

One the 4th n channel transistor, its grid receives described rp input signal, and drain electrode is electrically connected to described output node, and source ground.

8. voltage conversion circuit as claimed in claim 1 is characterized in that, described voltage conversion unit comprises:

One the one p channel transistor, its source electrode is connected to described second source, and grid is connected in described output node;

One the 2nd p channel transistor, its source electrode is connected to described second source, and grid is connected in described complementary output node;

One the 3rd p channel transistor, its source electrode is connected to the drain electrode of a described p channel transistor, and drain electrode is defined as described complementary output node, and grid receives described input signal;

One the 4th p channel transistor, its source electrode is connected to the drain electrode of described the 2nd p channel transistor, and drain electrode is defined as described output node, and grid receives described rp input signal;

One the 3rd n channel transistor, its grid receives described input signal, and drain electrode is electrically connected to described complementary output node, and source ground;

One the 4th n channel transistor, its grid receives described rp input signal, and drain electrode is electrically connected to described output node, and source ground.

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