CN112311207A - Voltage conversion device, power chip and electronic equipment - Google Patents
Voltage conversion device, power chip and electronic equipment Download PDFInfo
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- CN112311207A CN112311207A CN202011287539.1A CN202011287539A CN112311207A CN 112311207 A CN112311207 A CN 112311207A CN 202011287539 A CN202011287539 A CN 202011287539A CN 112311207 A CN112311207 A CN 112311207A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0096—Means for increasing hold-up time, i.e. the duration of time that a converter's output will remain within regulated limits following a loss of input power
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
本公开涉及电压转换装置、电源芯片及电子设备，所述电压转换装置包括第一NMOS晶体管及电压保持单元，所述电压转换装置用于将属于第一电压范围的输入信号转换为属于第二电压范围的输出信号，所述电压保持单元的电源端用于输入第一电源电压，接地端接地，第二端用于产生所述输出信号，当产生所述输入信号的第二电源电压在维持一段时间消失时，所述电压保持单元用于维持第一端的所述输出信号的反向信号的电位，并维持第二端的输出信号的电位。本公开实施例提出的电压转换装置可以保持输出信号的稳定，且，利用一个电源进行工作，可以降低功耗。
The present disclosure relates to a voltage conversion device, a power chip and an electronic device, the voltage conversion device includes a first NMOS transistor and a voltage holding unit, and the voltage conversion device is used for converting an input signal belonging to a first voltage range into a second voltage The power supply terminal of the voltage holding unit is used to input the first power supply voltage, the ground terminal is grounded, and the second terminal is used to generate the output signal. When the second power supply voltage that generates the input signal is maintained for a period of time When time elapses, the voltage maintaining unit is used for maintaining the potential of the reverse signal of the output signal at the first end, and maintaining the potential of the output signal at the second end. The voltage conversion device proposed by the embodiments of the present disclosure can maintain the stability of the output signal, and can reduce power consumption by using one power supply to operate.
Description
Technical Field
The present disclosure relates to the field of power management technologies, and in particular, to a voltage conversion device, a power chip, and an electronic apparatus.
Background
Voltage conversion devices are commonly used in semiconductor circuits to convert signal levels in one voltage domain to different voltage levels in another domain. At present, the voltage conversion device in the related art generally performs level conversion by using dual power sources, and when one of the power sources stops operating due to some reason, the voltage conversion device in the related art cannot stably operate, an output signal is unstable, so that a problem that a through current flows through a subsequent stage circuit that operates according to the output signal occurs, and the voltage conversion device in the related art has a problem of high power consumption when realizing its function.
Disclosure of Invention
In view of the above, the present disclosure provides a voltage conversion apparatus including a first NMOS transistor and a voltage holding unit, the voltage conversion apparatus being configured to convert an input signal belonging to a first voltage range into an output signal belonging to a second voltage range, wherein,
the grid electrode of the first NMOS transistor is used for receiving an input signal, and the drain electrode of the first NMOS transistor is electrically connected to the first end of the voltage holding unit, wherein the voltage signal of the first end of the voltage holding unit is an inverse signal of the output signal;
the voltage holding unit has a power source terminal for inputting a first power voltage, a ground terminal for grounding, and a second terminal for generating the output signal, wherein when a second power voltage generating the input signal disappears after being maintained for a period of time, the voltage holding unit is used for maintaining the potential of an inverted signal of the output signal at the first terminal and maintaining the potential of the output signal at the second terminal.
In one possible embodiment, the voltage holding unit includes a first inverter and a second inverter, wherein the first inverter and the second inverter are cross-coupled.
In one possible implementation, the first inverter includes a second NMOS transistor and a first PMOS transistor, and the second inverter includes a third NMOS transistor and a second PMOS transistor, wherein:
the drain of the second NMOS transistor is electrically connected to the drain of the first PMOS transistor, the gate of the third NMOS transistor, the gate of the second PMOS transistor and the drain of the first NMOS transistor for generating an inverse signal of the output signal,
a gate of the second NMOS transistor is electrically connected to a gate of the first PMOS transistor, a drain of the third NMOS transistor, and a drain of the second PMOS transistor for generating the output signal,
the source electrode of the second NMOS transistor is electrically connected with the source electrode of the third NMOS transistor and is used for grounding,
the source electrode of the first PMOS transistor is electrically connected to the source electrode of the second PMOS transistor and used for receiving the first power supply voltage.
In one possible implementation, the source of the first NMOS transistor is electrically connected to the source of the second NMOS transistor and the source of the third NMOS transistor.
In one possible implementation, the voltage conversion device further includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, wherein,
a drain of the fourth NMOS transistor is electrically connected to the source of the first NMOS transistor, a gate of the fourth NMOS transistor is configured to receive the second power voltage, a source of the fourth NMOS transistor is grounded,
the drain of the fifth NMOS transistor is electrically connected to the second end of the voltage holding unit, the gate of the fifth NMOS transistor is used for receiving the inverse signal of the input signal,
the drain of the sixth NMOS transistor is electrically connected to the source of the fifth NMOS transistor, the gate of the sixth NMOS transistor is configured to receive the second power voltage, and the source of the sixth NMOS transistor is grounded.
In one possible embodiment, the voltage of the first supply voltage is higher than the voltage of the second supply voltage.
According to another aspect of the present disclosure, a power supply chip is provided, the chip including the voltage conversion device.
According to another aspect of the present disclosure, an electronic device is provided, which includes the power supply chip.
In one possible implementation, the electronic device includes a portable computer, an intelligent handheld electronic device.
The voltage conversion apparatus provided by the embodiment of the disclosure may maintain the potential of the inverted signal of the output signal at the first end and maintain the potential of the output signal at the second end when the second power voltage generating the input signal is maintained for a period of time to disappear, so that when one of the power supplies stops working, the output signal is kept stable, and the power consumption may be reduced by using one power supply to work.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a schematic diagram of a voltage conversion device according to an embodiment of the present disclosure.
Fig. 2 shows a schematic diagram of a voltage conversion device according to an embodiment of the present disclosure.
Fig. 3 shows a schematic diagram of a voltage conversion device according to an embodiment of the present disclosure.
Fig. 4 and 5 are schematic diagrams illustrating the operation effect of the voltage conversion device according to an embodiment of the disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a voltage conversion apparatus according to an embodiment of the disclosure.
As shown in fig. 1, the voltage conversion device includes a first NMOS transistor 110 and a voltage holding unit 120, and is used for converting an input signal a belonging to a first voltage range into an output signal Y belonging to a second voltage range, wherein,
the gate of the first NMOS transistor 110 is used to receive the input signal a, and the drain is electrically connected to the first end of the voltage holding unit 120, wherein the voltage signal Y at the first end of the voltage holding unit 120bIs an inverse of the output signal Y;
the power supply terminal of the voltage holding unit 120 is used for inputting a first power supply voltage VDDHA ground terminal is grounded, a second terminal is used for generating the output signal Y, wherein, when the second power voltage generating the input signal a is maintained for a period of time and disappears, the voltage holding unit 120 is used for maintaining the inverted signal Y of the output signal Y at the first terminalbAnd the potential of the output signal Y of the second terminal is maintained.
The voltage conversion apparatus provided by the embodiment of the disclosure may maintain the potential of the inverted signal of the output signal at the first end and maintain the potential of the output signal at the second end when the second power voltage generating the input signal is maintained for a period of time to disappear, so that when one of the power supplies stops working, the output signal is kept stable, and the power consumption may be reduced by using one power supply to work.
The voltage conversion device of the embodiment of the disclosure can be applied to a power supply chip, and the power supply chip can be applied to electronic equipment. The electronic device may include, for example, a mobile phone, a sound box, a smart wearable device, a digital camera, mp3, mp4, a router, an electronic book, a switch, a modem, a PSP, PS3, an NDS, an XBOX, a usb disk, a digital satellite receiver, and other digital products, and may also include a computer motherboard, a BIOS of a printer, a BIOS of a display card, a mouse, a display, an optical drive, a hard disk, a keyboard, a GPS terminal, a precision electronic instrument (such as a nuclear magnetic resonance instrument), and the like. In one example, the first voltage range may be a voltage range formed by the second power supply voltage and the ground voltage, and the second voltage range may be a range formed by the first power supply voltage and the ground voltage.
In one example, the voltage conversion device may be a Level Shifter (Level Shifter).
In one possible embodiment, the voltage of the first power supply voltage may be higher than the voltage of the second power supply voltage, and the voltage of the first power supply voltage is higher than the logic 1 potential of the input signal a.
In one example, when the second voltage source for generating the input signal a disappears after the input signal a assumes a logic 1 level for a period of time, the first NMOS transistor 110 will pull down the level of the inverted output signal Yb to raise the level of the output signal Y during the period of time, and when the level of the input signal a drops to the reference ground due to the disappearance of the second voltage source, the channel of the first NMOS transistor 110 will present a high impedance, so that the output signal Y and the inverted output signal Yb of the voltage holding unit 120 will still maintain at a high level (close to VDDH) and a low level (close to the reference ground), respectively. That is, the voltage conversion device allows the second voltage source for generating the input signal a to be maintained for a short time to ensure effective transmission and retention of the logic state, thereby reducing the power consumption of the whole circuit.
In one possible embodiment, the voltage holding unit 120 may be implemented by a hardware circuit.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a voltage conversion apparatus according to an embodiment of the disclosure.
In one possible embodiment, the voltage holding unit 120 may include a first inverter and a second inverter, wherein the first inverter and the second inverter are cross-coupled.
The embodiment of the present disclosure can realize a potential holding function of the voltage holding unit by cross-coupling the first inverter and the second inverter.
In one possible implementation, as shown in fig. 2, the first inverter includes a second NMOS transistor 121a and a first PMOS transistor 122a, and the second inverter includes a third NMOS transistor 121b and a second PMOS transistor 122b, wherein:
the drain of the second NMOS transistor 121a is electrically connected to the drain of the first PMOS transistor 122a, the gate of the third NMOS transistor 121b, the gate of the second PMOS transistor 122b, and the drain of the first NMOS transistor, for generating an inverse signal of the output signal,
the gate of the second NMOS transistor 121a is electrically connected to the gate of the first PMOS transistor 122a, the drain of the third NMOS transistor 121b, and the drain of the second PMOS transistor 122b, for generating the output signal,
the source of the second NMOS transistor 121a is electrically connected to the source of the third NMOS transistor 121b, for grounding,
the source of the first PMOS transistor 122a is electrically connected to the source of the second PMOS transistor 122b for receiving the first power voltage.
In one possible implementation, the source of the first NMOS transistor 110 is electrically connected to the sources of the second and third NMOS transistors 121a and 121 b.
In one example, under the control of the second power voltage, the voltage converting apparatus receives an input signal a, the voltage range of which is between the second power voltage and the ground voltage, the voltage converting apparatus may convert the input signal a, which belongs between the second power voltage and the low voltage, into an output signal Y, which belongs between the first power voltage and the low voltage, assuming that the input signal a is logic 1, the first NMOS transistor 110 is turned on, the drain of the first NMOS transistor 110 (i.e., the first end of the voltage holding unit) is at the low level, in which case the second PMOS transistor 122b is turned on, the third NMOS transistor 121b is turned off, the drain of the third NMOS transistor 121b (i.e., the second end of the voltage holding unit, the output end of the voltage converting apparatus) is at the high level logic 1, when the second power voltage is turned off so that the input signal a changes from the high level to the low level (in fact that the input signal a is still at the high level), since the first inverter composed of the second NMOS transistor 121a and the first PMOS transistor 122a, and the second inverter composed of the third NMOS transistor 121b and the second PMOS transistor 122b are cross-coupled, the second terminal of the voltage holding unit can still maintain the output signal Y at a high level, and the second terminal can still maintain the inverted signal YbIs low.
The above describes the case where the second power supply voltage directly supplies the input signal a, and the second power supply voltage may also supply the input signal a in other ways, which is described as an example below.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a voltage conversion apparatus according to an embodiment of the disclosure.
In one possible implementation, as shown in fig. 3, the voltage conversion device further includes a fourth NMOS transistor 110a, a fifth NMOS transistor 112, and a sixth NMOS transistor 112a, wherein,
a drain of the fourth NMOS transistor 110a is electrically connected to a source of the first NMOS transistor, and a gate of the fourth NMOS transistor 110a is configured to receive the second power voltage VDDLThe source of the fourth NMOS transistor 110a is grounded,
a drain of the fifth NMOS transistor 112 is electrically connected to the second end of the voltage holding unit 120, and a gate of the fifth NMOS transistor 112 is used for receiving the inverted signal Y of the input signalb，
A drain of the sixth NMOS transistor 112a is electrically connected to a source of the fifth NMOS transistor 112, and a gate of the sixth NMOS transistor 112a is configured to receive the second power voltage VDDLAnd the source of the sixth NMOS transistor 112a is grounded.
The voltage holding unit 120 can refer to the previous description and will not be described herein.
In one example, when the first power supply voltage VDDLAfter the input signal A is at a logic 1 level for a period of time, the fourth NMOS transistor 110a and the sixth NMOS transistor 112a are turned off to turn off the first NMOS transistor 110 and the fifth NMOS transistor 112, so that the output signal Y of the voltage holding unit 120 and the inverse signal Y of the output signal Y are enabledbYet remain at a high potential (near VDDH) and a low potential (near the ground reference), respectively. That is, the voltage conversion means allows the second power supply voltage VDDLEffective transmission and retention of a logic state can be ensured by maintaining for a short time, thereby reducing power consumption of the whole circuit and avoiding the need for a second power supply voltage VDDLAnd data loss is caused by abnormal power failure, and the circuit stability is maintained.
Referring to fig. 4 and 5, fig. 4 and 5 are schematic diagrams illustrating operation effects of a voltage conversion device according to an embodiment of the disclosure.
According to the voltage conversion device of the embodiment of the present disclosure, as shown in FIG. 4, when the second power voltage V is appliedDDLWhen the power failure is maintained for a period of time, although the level of the input signal A is also reduced from the high level to the low level, the output signal Y is still maintained at the high level due to the action of the voltage holding unit, and the normal and stable output of the circuit is maintained.
According to the voltage conversion apparatus of the embodiment of the present disclosure, as shown in fig. 5, when the input signal a is input to the voltage conversion apparatus, the logic state of the output signal Y of the output terminal of the voltage conversion apparatus may follow the logic state of the input signal aChange of state in phase at VDDHEqual to 5.5V and VDDLWhen the voltage of the input signal a is equal to 2.5V, the potential of the logic 1 of the input signal a is equal to 2.5V, and the potential of the logic 1 of the output signal Y is equal to 5.5V, when the input signal is logic 1 or logic 0, even if the second power supply voltage for controlling the potential of the input signal a is powered down, the voltage conversion device can still output the output signal Y (as shown in fig. 4) in the same phase as the input signal a.
By the voltage conversion device, the embodiment of the disclosure can effectively maintain the logic state of the output signal only by using the bias voltage of the high-voltage first power voltage after the low-voltage second power voltage disappears, so that the circuit can be maintained stable, and the low-voltage power supply is allowed to output the voltage without a normal state, thereby further saving power consumption.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (9)
1. A voltage conversion apparatus comprising a first NMOS transistor and a voltage holding unit, the voltage conversion apparatus for converting an input signal belonging to a first voltage range into an output signal belonging to a second voltage range, wherein,
the grid electrode of the first NMOS transistor is used for receiving an input signal, and the drain electrode of the first NMOS transistor is electrically connected to the first end of the voltage holding unit, wherein the voltage signal of the first end of the voltage holding unit is an inverse signal of the output signal;
the voltage holding unit has a power source terminal for inputting a first power voltage, a ground terminal for grounding, and a second terminal for generating the output signal, wherein when a second power voltage generating the input signal disappears after being maintained for a period of time, the voltage holding unit is used for maintaining the potential of an inverted signal of the output signal at the first terminal and maintaining the potential of the output signal at the second terminal.
2. The voltage conversion device of claim 1, wherein the voltage holding unit comprises a first inverter and a second inverter, wherein the first inverter and the second inverter are cross-coupled.
3. The voltage conversion apparatus of claim 2, wherein the first inverter comprises a second NMOS transistor and a first PMOS transistor, and the second inverter comprises a third NMOS transistor and a second PMOS transistor, wherein:
the drain of the second NMOS transistor is electrically connected to the drain of the first PMOS transistor, the gate of the third NMOS transistor, the gate of the second PMOS transistor and the drain of the first NMOS transistor for generating an inverse signal of the output signal,
a gate of the second NMOS transistor is electrically connected to a gate of the first PMOS transistor, a drain of the third NMOS transistor, and a drain of the second PMOS transistor for generating the output signal,
the source electrode of the second NMOS transistor is electrically connected with the source electrode of the third NMOS transistor and is used for grounding,
the source electrode of the first PMOS transistor is electrically connected to the source electrode of the second PMOS transistor and used for receiving the first power supply voltage.
4. The voltage conversion device of claim 3, wherein the source of the first NMOS transistor is electrically connected to the source of the second NMOS transistor and the source of the third NMOS transistor.
5. The voltage conversion device of claim 1, further comprising a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, wherein,
a drain of the fourth NMOS transistor is electrically connected to the source of the first NMOS transistor, a gate of the fourth NMOS transistor is configured to receive the second power voltage, a source of the fourth NMOS transistor is grounded,
the drain of the fifth NMOS transistor is electrically connected to the second end of the voltage holding unit, the gate of the fifth NMOS transistor is used for receiving the inverse signal of the input signal,
the drain of the sixth NMOS transistor is electrically connected to the source of the fifth NMOS transistor, the gate of the sixth NMOS transistor is configured to receive the second power voltage, and the source of the sixth NMOS transistor is grounded.
6. The voltage conversion device according to claim 1, wherein a voltage of the first power supply voltage is higher than a voltage of the second power supply voltage.
7. A power supply chip characterized in that the chip comprises the voltage conversion device according to any one of claims 1 to 6.
8. An electronic device characterized in that the electronic device comprises the power supply chip according to claim 7.
9. The electronic device of claim 8, wherein the electronic device comprises a portable computer, an intelligent handheld electronic device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011287539.1A CN112311207A (en) | 2020-11-17 | 2020-11-17 | Voltage conversion device, power chip and electronic equipment |
| JP2023515693A JP7639125B2 (en) | 2020-11-17 | 2021-09-08 | Voltage conversion device, power chip and electronic device |
| PCT/CN2021/117266 WO2022105377A1 (en) | 2020-11-17 | 2021-09-08 | Voltage conversion apparatus, power chip, and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011287539.1A CN112311207A (en) | 2020-11-17 | 2020-11-17 | Voltage conversion device, power chip and electronic equipment |
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| CN112311207A true CN112311207A (en) | 2021-02-02 |
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| CN202011287539.1A Pending CN112311207A (en) | 2020-11-17 | 2020-11-17 | Voltage conversion device, power chip and electronic equipment |
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| WO2022105377A1 (en) * | 2020-11-17 | 2022-05-27 | 北京集创北方科技股份有限公司 | Voltage conversion apparatus, power chip, and electronic device |
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| KR101931408B1 (en) * | 2012-08-01 | 2018-12-20 | 르네사스 일렉트로닉스 가부시키가이샤 | Level shift circuit, semiconductor device |
| JP2018129727A (en) | 2017-02-09 | 2018-08-16 | エイブリック株式会社 | Level shifter |
| CN111294042B (en) * | 2020-02-14 | 2023-07-18 | 上海华虹宏力半导体制造有限公司 | Level shift circuit |
| CN112311207A (en) * | 2020-11-17 | 2021-02-02 | 北京集创北方科技股份有限公司 | Voltage conversion device, power chip and electronic equipment |
-
2020
- 2020-11-17 CN CN202011287539.1A patent/CN112311207A/en active Pending
-
2021
- 2021-09-08 JP JP2023515693A patent/JP7639125B2/en active Active
- 2021-09-08 WO PCT/CN2021/117266 patent/WO2022105377A1/en active Application Filing
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| CN1905371A (en) * | 2005-07-26 | 2007-01-31 | 凌阳科技股份有限公司 | A voltage conversion circuit |
| CN1988344A (en) * | 2006-12-06 | 2007-06-27 | 威盛电子股份有限公司 | Voltage converter and method thereof |
| US20090212842A1 (en) * | 2008-02-26 | 2009-08-27 | Illegems Paul F | Level Shifter with Memory Interfacing Two Supply Domains |
| CN107483046A (en) * | 2017-08-01 | 2017-12-15 | 深圳芯启航科技有限公司 | Level translator |
| CN213426011U (en) * | 2020-11-17 | 2021-06-11 | 北京集创北方科技股份有限公司 | Voltage conversion device, power supply chip and electronic equipment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022105377A1 (en) * | 2020-11-17 | 2022-05-27 | 北京集创北方科技股份有限公司 | Voltage conversion apparatus, power chip, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022105377A1 (en) | 2022-05-27 |
| JP7639125B2 (en) | 2025-03-04 |
| JP2023540787A (en) | 2023-09-26 |
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