CN113055149A - Time synchronization and frequency synchronization method under radio frequency transceiver cascade system - Google Patents
Time synchronization and frequency synchronization method under radio frequency transceiver cascade system Download PDFInfo
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Abstract
The invention relates to a time synchronization and frequency synchronization method under a radio frequency transceiver cascade system, which can effectively solve the function problems of time synchronization and frequency synchronization which can be realized under the cascade system by using a plurality of devices to realize the self-adaptive selection of an optimal input clock under the condition of multiple clock sources of the radio frequency transceiver; frequency synchronization, namely the synchronization of the frequency and the phase of each node under a cascade system; and (3) frequency adaptation, namely determining the optimal frequency and time of the system by adopting a frequency adaptation and time optimal algorithm so as to generate each clock signal used by the system. The equipment of the invention has scientific and reasonable assembly, simple method, easy operation, good effect and consistent time and frequency, and obtains the accurate system clock.
Description
Technical Field
The invention relates to a network technology, in particular to a time synchronization and frequency synchronization method under a radio frequency transceiver cascade system.
Background
The clock synchronization technology is a very critical technology and is widely applied to the fields of communication, military, traffic, industrial automation and the like at present. The technology is adopted in the distributed data system, so that the time consistency and the accuracy of data acquisition of each node in the system can be greatly improved, and the stability and the reliability of the whole system are improved. At present, there are multiple schemes for the research of related fields at home and abroad, mainly as follows:
based on the synchronous clock technology of the time service center, the time service center transmits standard time and frequency signals to each acquisition point so as to realize the unification of the sampling time and the frequency of the whole system. The typical technology is GPS clock synchronization technology, which carries out multiple communications with ground GPS receiving equipment through a GPS satellite, calculates the distance between the GPS receiving equipment and the corresponding satellite, transmits signals sent by the satellite to information such as time delay parameters generated by the GPS equipment, and corrects messages transmitted by the GPS through the parameters.
The clock synchronization technology based on the NTP network time protocol adopts the working principle that a mode of adding time marks on an application layer is adopted. The protocol is flexible in application and simple in implementation.
The frequency synchronization signals in a general cascade system or a distributed networking system are the second pulse signals of a GPS and the signals of a local system clock crystal oscillator. The scheme utilizes the long-term stability characteristics of the GPS second pulse and the short-term stability characteristics of the local system clock to provide a reliable stable clock for the system. The crystal oscillator in the scheme generally selects an oven controlled crystal oscillator (OCXO) and is limited by the frequency adjustment range of the oven controlled crystal oscillator, if the frequency adjustment range of the oven controlled crystal oscillator exceeds the frequency adjustment range of the design requirement, the frequency calibration cannot be correctly carried out, and the frequency synchronization processing cannot be carried out, so that the system fails. Therefore, how to effectively solve the time synchronization and the frequency synchronization in the radio frequency transceiver cascade system is a technical problem to be solved seriously.
Disclosure of Invention
In view of the above situation, to overcome the drawbacks of the prior art, the present invention provides a method for time synchronization and frequency synchronization in a cascade system of radio frequency transceivers, which can effectively solve the functional problems of time synchronization and frequency synchronization that can be achieved in a cascade system, in which a plurality of devices can form a cascade system, and the radio frequency transceivers can adaptively select an optimal input clock under the condition of multiple clock sources.
The technical scheme includes that the time synchronization and frequency synchronization method under a radio frequency transceiver cascade system includes that equipment is installed firstly, the equipment is composed of a host PC and a system unit, the host PC is composed of a first GPS1 (global positioning system, the same below), a first optical port module G1 and an Ethernet Y, a signal input end 1 of the first GPS1 is connected with an antenna, a signal output end 2 of the first GPS1 is connected with a satellite signal input end 1 of the first optical port module G1, an Ethernet signal input interface 2 of the first optical port module G1 is connected with the Ethernet Y, an Ethernet physical layer analysis time output port 3 of the first optical port module G1 is connected with an input end 1 of a second optical port module G2 of the system unit; the system unit is composed of a primary unit and a secondary unit, wherein the primary unit is composed of a second GPS2, a second optical port module G2, a first synchronous clock generator (singlechip) IC1 and a first programmable logic array IC2, a satellite interface 1 of the second GPS2 is connected with an antenna, a GPS time output port 2 is connected with a time input port 2 of the first programmable logic array IC2, a 1PPS output port 2 of the second GPS2 is connected with a 1PPS input port 2 of the first synchronous clock generator IC1, a serial port 1 of the first programmable logic array IC2 is connected with a serial port cascade to transmit time information, an external synchronous time input interface 1 of the first synchronous clock generator IC1 is connected with external synchronous input time, a signal input end 3 of the first synchronous clock generator IC1 is connected with a signal input port 4 of the first programmable logic array IC2, a 1PPS 4 of the first synchronous clock generator IC1 is connected with a PPS input port 1 of the second synchronous clock generator IC3, the signal output end 2 of the second optical port module G2 is connected with the signal input end 3 of the first programmable logic array IC2, and the signal output end 5 of the first programmable logic array IC2 is connected with the signal input end 1 of the second programmable logic array IC 4; the secondary unit consists of a third GPS3 and a third light port module G3, the second synchronous clock generator IC3 and the second programmable logic array IC4, the satellite signal input end 1 of the third GPS3 connects with the antenna, the satellite signal output end 2 connects with the signal input end 2 of the second programmable logic array IC4, the signal input end 1 of the third optical port module G3 connects with the time analyzed by the Ethernet physical layer, the signal output end 2 connects with the signal input end 3 of the second programmable logic array IC4, the signal output end 2 of the second synchronous clock generator IC3 connects with the signal input end 4 of the second programmable logic array IC4, the pin 3 of the second synchronous clock generator IC3 connects with the signal input port of the embedded microcontroller of the next primary unit, the pin 5 of the second programmable logic array IC4 connects with the signal input end of the programmable logic array of the next primary unit, the secondary units can be connected together by the same plurality of series;
after the equipment (system) is installed, the following steps are carried out:
(1) and time synchronization: as shown in fig. 1, in the primary system, the time with the best quality is selected and transmitted to the secondary system through the serial port of the first programmable logic array IC2 (FPGA), and the secondary system determines that the time information is transmitted from the serial port of the first programmable logic array IC2 and disables other time information, and then performs a time delay compensation algorithm to calculate the time delay in the transmission link and further compensate the delay, thereby realizing the time synchronization of the primary system and the secondary system;
the time for selecting the optimal quality is obtained by the following steps (shown in figure 6):
firstly, judging whether time input is available at an optical port (serial port), if so, judging that the time input is the time input of the previous stage under the cascade system, ending the algorithm, and carrying out time synchronization treatment under the cascade system;
secondly, when no time is input at the serial port, the serial port is a non-cascade system, the algorithm collects the reading of second within a period of time, judges whether the second jump exists or not, and if the second jump does not exist, the serial time is continuous time, and the next step of calculation is carried out;
when the time collected in the second step is continuous, the algorithm part calculates the maximum time interval error and compares the maximum time interval errors of all clocks; selecting the clock source with the minimum error as the time with the best quality;
the method for compensating the delay is as follows (see fig. 2):
firstly, a secondary system sends a time synchronization request data packet REQ to a primary system, and adds a time stamp T1 on a frame header of a data frame of the data packet REQ;
the primary system receives a synchronous request data packet REQ, and the time point of receiving the data packet is marked as T2;
the primary system sends a corresponding data packet RES, and adds a time stamp T3 on the header of a data frame responding to the data packet RES;
fourthly, the secondary system receives the response data packet, and the received time point is recorded as T4;
calculating delay time t of linkoffset，toffsetIs calculated as toffset= (T2-T1 + T3-T4)/2, and T is calculatedoffsetThereafter, the time received by the secondary system plus the offset time toffsetThe time received by the secondary system can be corrected, so that the time synchronization of the primary system and the secondary system is realized;
(2) and frequency synchronization:
the second pulse is used as a frequency synchronization signal of a system by utilizing the characteristic of good stability of the second pulse, each clock used in the system is generated by a first synchronous clock generator IC1 (having the functions of a clock generator and a digital phase-locked loop) on the optimal clock selected in the step (1) under a primary system, and a second pulse signal of 1PPS is generated by locking at the same time, the signal is transmitted to an external synchronization input of a secondary system by the primary system and is used as a reference signal of a first synchronous clock generator IC1, and a high-precision system clock synchronous with the reference signal is generated by the digital phase-locked loop, so that the synchronization of the frequency and the phase of each node under a cascade system is ensured;
(3) frequency self-adaptation:
as shown in fig. 1 and fig. 3, the cascade system of the present invention is formed by combining a plurality of rf transceivers, and for a non-cascade system, i.e. a single rf transceiver, for a multi-clock domain source and a multi-time source, there are 3 kinds of frequency signals, respectively, a 1PPS signal generated by GPS is a first signal, a synchronous ethernet clock/fiber recovery clock is a second signal, under the cascade system, an external synchronization signal formed by connecting an external synchronization signal of a secondary system with a 1PPS signal generated by an AD9548 in a primary system is a third signal, and a frequency adaptive and time optimal algorithm is used to determine the optimal frequency and time of the system;
the frequency adaptation comprises two parts (shown in figure 3), wherein the first part is a clock generation and locking unit, each clock required by the system is generated by a circuit taking a synchronous clock generator ICA as a main chip, and a 1PPS signal is simultaneously locked and generated and is used as a frequency synchronization signal under a cascade system; the synchronous Ethernet clock/optical fiber recovery clock comes from an optical port part in the system, and different clocks are selected according to different protocols; the second part is an algorithm unit which is composed of a singlechip ICB and a synchronous clock generator ICA, software codes are stored in an RAM in the chip, an external 8MHz crystal oscillator is used for providing time signals for the singlechip, an onboard power supply is used for supplying power, the synchronous clock generator ICA and the singlechip ICB are connected and communicated through a 12C bus, the algorithm unit and the synchronous clock generator ICA have the same input, namely, a first signal, a second signal and a third signal are respectively input into the synchronous clock generator ICA and the singlechip ICB through a first coupling capacitor A and a second coupling capacitor B, the algorithm unit and the synchronous clock generator ICA have the functions of monitoring clocks of all interfaces, sequencing according to the priority levels of the clocks at different interfaces, then configuring corresponding registers passing through the synchronous clock generator ICA to enable the synchronous clock generator ICA to select the clock with the highest priority level as the reference input, further generating the clock used in the system, the flow of the arithmetic unit is shown in fig. 4: the priority order of each interface is external synchronous clock, GPS/1PPS, synchronous Ethernet clock/optical fiber recovery clock from high to low; the single chip microcomputer only sequences input clock signals, and configures corresponding registers of the synchronous clock generator ICA through the 12C bus according to a sequencing result to control the synchronous clock generator ICA to open corresponding clock reference input channels, so that the synchronous clock generator ICA can obtain high-quality external input clocks, and further generate each clock signal used by the system.
The device is scientific and reasonable in assembly, simple in method, easy to operate and good in effect, and is effectively used for realizing the self-adaptive selection of the optimal input clock of the radio frequency transceiver under the condition of multiple clock sources, meanwhile, a plurality of devices can form a cascade system, the functions of time synchronization and frequency synchronization can be realized under the cascade system, the data acquired by the system is more accurate, the self-adaptive selection of a clock domain and the optimization of multiple time sources can be realized under an independent system, the synchronization of time and frequency can be realized under a multi-machine system, the time and the frequency are kept consistent, and the clock acquired by the whole system is more accurate.
Drawings
FIG. 1 is a block diagram of a process apparatus of the present invention.
FIG. 2 is a flowchart illustrating the calculation of the delay time according to the present invention.
Fig. 3 is a schematic block diagram of the frequency adaptation of the present invention.
FIG. 4 is a flow chart of the algorithm unit of the present invention.
FIG. 5 is a block diagram of the system time input module of the present invention.
FIG. 6 is a flow chart of the time-optimalization algorithm of the present invention.
Detailed Description
The following detailed description of the embodiments of the invention is provided in connection with the accompanying drawings and the detailed description.
As shown in fig. 1 to 6, in the implementation of the present invention, a method for time synchronization and frequency synchronization in a radio frequency transceiver cascade system is provided by the following steps:
(1) and time synchronization: as shown in fig. 1, in the primary system, the time with the best quality is selected and transmitted to the secondary system through a serial port of a first programmable logic array IC2 (FPGA) with model number EP3C5, the secondary system determines that time information is transmitted from the serial port of the first programmable logic array IC2, and then disables other time information, and then calculates the time delay in the transmission link by using an algorithm for compensating the time delay, and further compensates the delay, thereby realizing the time synchronization of the primary system and the secondary system;
the time for selecting the optimal quality is obtained by the following steps (shown in figure 6):
firstly, judging whether the optical port of a second optical port module G2 (the type QSFP-40G-SR4 is only the optical port module used in the invention, wherein the optical port module mentioned in the invention has universal applicability, and meets the requirement that the optical port modules of QSFP packaging types are all suitable for the invention) has time input, if so, the optical port module is the time input of the previous stage under the cascade system, the algorithm is ended, and the time synchronization under the cascade system is processed;
secondly, when no time is input at the optical port of the second optical port module G2, the system is a non-cascaded system, the algorithm collects the reading of second within a period of time, judges whether the second jump exists or not, and if the second jump does not exist, the time is continuous time, and the next step of calculation is carried out;
when the time is continuous, the algorithm part calculates the maximum time interval error and compares the maximum time interval errors of the clocks; selecting the clock source with the minimum error as the time with the best quality;
the method for compensating the delay is as follows (see fig. 2):
firstly, a secondary system sends a time synchronization request data packet REQ to a primary system, and adds a time stamp T1 on a frame header of a data frame of the data packet REQ;
the primary system receives a synchronous request data packet REQ, and the time point of receiving the data packet is marked as T2;
the primary system sends a corresponding data packet RES, and adds a time stamp T3 on the header of a data frame responding to the data packet RES;
fourthly, the secondary system receives the response data packet, and the received time point is recorded as T4;
calculating the delay time of the linkTime toffset，toffsetIs calculated as toffset= (T2-T1 + T3-T4)/2, and T is calculatedoffsetThereafter, the time received by the secondary system plus the offset time toffsetThe time received by the secondary system can be corrected, so that the time synchronization of the primary system and the secondary system is realized;
(2) and frequency synchronization:
the second pulse is used as a frequency synchronization signal of a system by utilizing the characteristic of good stability of the second pulse, each clock used in the system is generated by the optimal clock selected in the step (1) through a first synchronous clock generator IC1 (with the model of AD9548 and the function of a clock generator and a digital phase-locked loop) under a primary system, and simultaneously, the second pulse signal of 1PPS is generated in a locking way, the signal is transmitted to the external synchronization input of a secondary system by the primary system and is used as a reference signal of the first synchronous clock generator IC1, and then a high-precision system clock synchronous with the reference signal is generated through the digital phase-locked loop, so that the synchronization of the frequency and the phase of each node under a cascade system is ensured;
(3) frequency self-adaptation:
as shown in fig. 1 and fig. 3, the cascade system of the present invention is formed by combining a plurality of rf transceivers, and for a non-cascade system, i.e. a single rf transceiver, for a multi-clock domain source and a multi-time source, there are 3 kinds of frequency signals, respectively, a 1PPS signal generated by GPS is a first signal, a synchronous ethernet clock/fiber recovery clock is a second signal, under the cascade system, an external synchronization signal formed by connecting an external synchronization signal of a secondary system with a 1PPS signal generated by an AD9548 in a primary system is a third signal, and a frequency adaptive and time optimal algorithm is used to determine the optimal frequency and time of the system;
the frequency self-adaptation comprises two parts (shown in figure 3), wherein the first part is a clock generation and locking unit, each clock required by the system is generated by a circuit taking an AD9548 synchronous clock generator ICA as a main chip, and a 1PPS signal is simultaneously locked and generated and is used as a frequency synchronization signal under a cascade system; the synchronous Ethernet clock/optical fiber recovery clock comes from an optical port part in the system, and different clocks are selected according to different protocols; the second part is an arithmetic unit which is composed of an STM32F101C6T6ATR singlechip ICB (embedded microcontroller) and an AD9548 synchronous clock generator ICA, software codes are stored in an RAM in the chip, an external 8MHz crystal oscillator is used for providing time signals for the singlechip, an onboard power supply is used for supplying power, the synchronous clock generator ICA and the singlechip ICB are connected and communicated through a 12C bus, the arithmetic unit and the synchronous clock generator ICA have the same input, namely, a first signal, a second signal and a third signal are respectively input into the AD9548 synchronous clock generator ICA and the singlechip ICB through a first coupling capacitor CA and a second coupling capacitor CB, the ICB is used for monitoring clocks of each interface, sorting is carried out according to priority levels of the clocks at different interfaces, then corresponding registers passing through the synchronous clock generator ICA are configured, so that the AD9548 synchronous clock generator ICA selects the clock with the highest priority level, as a reference input, and further generate the clock used in the system, the flow of the algorithm unit is shown in fig. 4: the priority order of each interface is external synchronous clock, GPS/1PPS, synchronous Ethernet clock/optical fiber recovery clock from high to low; the single chip microcomputer only sequences input clock signals, and configures corresponding registers of the synchronous clock generator ICA through the 12C bus according to a sequencing result to control the synchronous clock generator ICA to open corresponding clock reference input channels, so that the synchronous clock generator ICA can obtain high-quality external input clocks, and further generate each clock signal used by the system.
The synchronous clock generator ICA can be a single synchronous clock generator IC1, or can be a secondary second synchronous clock generator IC3 and a plurality of cascaded synchronous clock generators, and the types of the synchronous clock generators are AD9548 in the present invention, but the present invention is not limited to AD9548, and other synchronous clock generators of the same type are within the protection scope of the present patent.
The AD9548 clock generator/synchronizer is used for remote optical network and wireless network nodes, wired infrastructure and data communication equipment, and can omit special oscillators, phase-locked loops and other clock recovery circuit systems which are required to generate clock signals synchronous with the widely used 1pps GPS standard. Utilizing GPS signals through AD9548 may simplify and shorten the design process while providing a lower power consumption timing reference.
The AD9548 incorporates an embedded microcontroller (ICB) which can up-convert 1pps GPS signals while reducing input time jitter or phase noise associated with external references to 300 femtoseconds; the clock distribution part provides four output drivers, each driver can be programmed into a single differential LVPECL/LVDS output or a pair of single-ended CMOS outputs, and the four outputs are provided with special 30-bit programmable post-frequency dividers and can generate various different output frequencies; when the system reference clock is as low as 4MHz, the output as high as 450MHz can still be realized through the integrated reference clock multiplier; a programmable digital control loop filter is built in to support as low as 1-mHz (1x10-3), and manual and automatic hold circuits that continuously generate an effective output clock with low jitter.
AD9548 can operate in the industrial temperature range of-40 deg.C to +85 deg.C, network synchronization, reference clock jitter clean, GPS1 pulses per second synchronization, SONET/SDH clocks up to OC-192, including Forward Error Correction (FEC), Stratum 2 hold (hold), jitter clean, and phase transient control, Stratum 3/3E reference clock wireless base station, controller, wired infrastructure data communications.
The single-chip microcomputer ICB can be a single embedded microcontroller of a synchronous clock generator IC1, and can also comprise a secondary second synchronous clock generator IC3 or a plurality of cascaded embedded microcontrollers, wherein the models of the embedded microcontrollers are STM32F101C6T6 ATR.
The secondary of the method system can be formed by connecting a plurality of secondary in series with the same structure, only the primary secondary is given in the figure, the equipment of the algorithm unit is formed by a small single chip microcomputer STM32F101C6T6ATR and a matched external circuit (shown in figure 3), the content of the algorithm is realized in the single chip microcomputer, AD9548 is a chip which not only has the function of a digital phase-locked loop, but also can generate a clock signal, and PPS means pulse per second, 1PPS =1Hz =1 times/second; the 1PPS signal generated by the GPS is a first signal, the synchronous Ethernet clock/optical fiber recovery clock is a second signal, and the external synchronous signal (in a cascade system, the external synchronous signal of a secondary system is connected with the 1PPS signal generated by the AD9548 in the primary system) is a third signal; the first coupling capacitor CA consists of a first capacitor C1, a second capacitor C2 and a third capacitor C3, one end of the first capacitor C1 is connected with a GPS/1PPS signal end, the other end of the first capacitor C1 is connected with a signal input end 1 of an AD9548 synchronous clock generator ICA, one end of the second capacitor C2 is connected with a synchronous clock signal, the other end of the second capacitor C1 is connected with a synchronous clock signal input end 2 of the AD9548 synchronous clock generator ICA, one end of the third capacitor C3 is connected with a recovered clock signal, and the other end of the third capacitor C3 is connected with a recovered clock signal input end 3 of the AD9548 synchronous clock generator ICA; the second coupling capacitor CB is composed of a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6, one end of the sixth capacitor C6 is connected with a GPS/1PPS signal end, the other end of the sixth capacitor C6 is connected with a signal input end 3 of a single chip microcomputer STM32F101C6T6ATR, one end of the fifth capacitor C5 is connected with a synchronous clock signal, the other end of the fifth capacitor C5 is connected with a synchronous clock signal input end 2 of the single chip microcomputer STM32F101C6T6ATR, one end of the fourth capacitor C4 is connected with a recovered clock signal, and the other end of the fourth capacitor C4 is connected with a recovered clock signal input end 1 of;
an optical port module of the PC and an optical port module of the system perform data transmission through an optical port, and simultaneously, the time of Ethernet or GPS in a PC main station can be transmitted as one of time inputs of the system, the GPS module receives satellite signals to generate corresponding time information and also serves as one of time sources of the system, in a secondary system, the secondary system receives the time sent by a primary (system) FPGA serial port and also serves as one of the time sources of the secondary system, namely, time selection is performed aiming at the three time sources; the synchronous ethernet clock/fiber recovery clock selects different clocks according to different protocols in the transmission process. In the primary system in the cascade system, the 1PPS signal generated by the GPS and the external synchronous clock are selected as the two alternatives when in application, in the secondary system, the source of the external synchronous clock is the 1PPS signal generated by the AD9548 of the primary system, and the 1PPS signal generated by the AD9548 is taken as the frequency synchronous signal of the whole cascade system.
It can be seen from the above that the present invention provides a method of time synchronization and frequency synchronization, which makes the data transmission and sampling of the system more accurate and stable, selects the best time in the primary system, transfers the time to the secondary system through the serial port of the FPGA, deduces the time information transfer at the serial port of the FPGA from the time of the secondary system, and disables other time information, and then performs the algorithm of time delay compensation, calculates the time delay in the transfer link, and further compensates the delay, thereby realizing the time synchronization of the primary system and the secondary system.
The frequency synchronization avoids using a constant temperature clock as a source of a system clock, and selects and utilizes the characteristic of good stability of the pulse per second as a frequency synchronization signal of the system. The cascade mode is shown in figure 1. The optimal clock is selected under the primary system, each clock used in the system is generated after passing through a clock generator AD9548, and meanwhile, the AD9548 also locks a pulse per second signal generating 1 PPS. The signal is transmitted to the external synchronous input of the secondary system by the primary system and is used as a reference signal of an AD9548 digital phase-locked loop, and a high-precision system clock synchronous with the reference signal is generated by the digital phase-locked loop, so that the synchronization of the frequency and the phase of each node under the cascade system is ensured. The cascade system of the method of the invention is combined by a plurality of radio frequency transceivers. For a non-cascaded system, namely an individual radio frequency transceiver, a frequency self-adaptive and time optimal selection algorithm is proposed for a multi-clock domain source and a multi-time source of the system to determine the optimal frequency and time of the system, and the self-adaptive selection of the multi-clock domain and the selection of the multi-time source can be realized under the individual system. The time and frequency synchronization can be realized under a multi-machine system, so that the time and frequency of the whole system are kept consistent, the time synchronization and the frequency synchronization of the radio frequency device under a cascade system are effectively realized, the data acquired by the system are more accurate, and the stability and the reliability of the system are improved. Under the condition of non-cascade, the self-adaptive selection of multiple clock domains input by equipment and the time optimization are realized, so that the clock obtained by the whole system is more stable and accurate, the long-term stability is 0.2ppb, the method is a great innovation in the network communication technology, and has great economic and social benefits.
Claims (6)
1. A time synchronization and frequency synchronization method under a radio frequency transceiver cascade system is characterized in that equipment is installed firstly, the equipment is composed of a host PC and a system unit, the host PC is composed of a first GPS1, a first optical port module G1 and an Ethernet Y, a signal input end 1 of the first GPS1 is connected with an antenna, a signal output end 2 of the first GPS1 is connected with a satellite signal input end 1 of the first optical port module G1, an Ethernet signal input interface 2 of the first optical port module G1 is connected with the Ethernet Y, an Ethernet physical layer analysis time output port 3 of the first optical port module G1 is connected with an input end 1 of a second optical port module G2 of the system unit; the system unit is composed of a primary unit and a secondary unit, wherein the primary unit is composed of a second GPS2, a second optical port module G2, a first synchronous clock generator IC1 and a first programmable logic array IC2, a satellite interface 1 of the second GPS2 is connected with an antenna, a GPS time output port 2 is connected with a time input port 2 of the first programmable logic array IC2, a 1PPS output port 2 of the second GPS2 is connected with a 1PPS input port 2 of the first synchronous clock generator IC1, a serial port 1 of the first programmable logic array IC2 is connected with serial port cascade transmission time information, an external synchronous time input interface 1 of the first synchronous clock generator IC1 is connected with external synchronous input time, a signal input end 3 of the first synchronous clock generator IC1 is connected with a signal input port 4 of the first programmable logic array IC2, a 1PPS output port 4 of the first synchronous clock generator IC1 is connected with a 1PPS input port 1 of the second synchronous clock generator IC3, the signal output end 2 of the second optical port module G2 is connected with the signal input end 3 of the first programmable logic array IC2, and the signal output end 5 of the first programmable logic array IC2 is connected with the signal input end 1 of the second programmable logic array IC 4; the secondary unit consists of a third GPS3 and a third light port module G3, the second synchronous clock generator IC3 and the second programmable logic array IC4, the satellite signal input end 1 of the third GPS3 connects with the antenna, the satellite signal output end 2 connects with the signal input end 2 of the second programmable logic array IC4, the signal input end 1 of the third optical port module G3 connects with the time analyzed by the Ethernet physical layer, the signal output end 2 connects with the signal input end 3 of the second programmable logic array IC4, the signal output end 2 of the second synchronous clock generator IC3 connects with the signal input end 4 of the second programmable logic array IC4, the pin 3 of the second synchronous clock generator IC3 connects with the signal input port of the embedded microcontroller of the next primary unit, the pin 5 of the second programmable logic array IC4 connects with the signal input end of the programmable logic array of the next primary unit, the secondary units can be connected together by the same plurality of series;
after the equipment is installed, the method comprises the following steps:
(1) and time synchronization: in the primary system, the time with the optimal quality is selected and transmitted to the secondary system through the serial port of the first programmable logic array IC2, the secondary system judges that the time information transmission at the serial port of the first programmable logic array IC2 disables other time information, and then the time delay compensation algorithm is carried out to calculate the time delay in a transmission link and further compensate the delay, so that the time synchronization of the primary system and the secondary system is realized;
the method for selecting the optimal time comprises the following steps:
firstly, judging whether time input is available at an optical port, if so, inputting the time of the previous stage under the cascade system, ending the algorithm, and carrying out time synchronization treatment under the cascade system;
secondly, when no time is input at the serial port, the serial port is a non-cascade system, the algorithm collects the reading of second within a period of time, judges whether the second jump exists or not, and if the second jump does not exist, the serial time is continuous time, and the next step of calculation is carried out;
when the time collected in the second step is continuous, the algorithm part calculates the maximum time interval error and compares the maximum time interval errors of all clocks; selecting the clock source with the minimum error as the time with the best quality;
the method for compensating the delay comprises the following steps:
firstly, a secondary system sends a time synchronization request data packet REQ to a primary system, and adds a time stamp T1 on a frame header of a data frame of the data packet REQ;
the primary system receives a synchronous request data packet REQ, and the time point of receiving the data packet is marked as T2;
the primary system sends a corresponding data packet RES, and adds a time stamp T3 on the header of a data frame responding to the data packet RES;
fourthly, the secondary system receives the response data packet, and the received time point is recorded as T4;
calculating delay time t of linkoffset，toffsetIs calculated as toffset= (T2-T1 + T3-T4)/2, and T is calculatedoffsetThereafter, the time received by the secondary system plus the offset time toffsetThe time received by the secondary system can be corrected, so that the time synchronization of the primary system and the secondary system is realized;
(2) and frequency synchronization:
the second pulse is used as a frequency synchronization signal of a system by utilizing the characteristic of good stability of the second pulse, the optimal clock selected in the step (1) is generated into clocks used in the system through a first synchronous clock generator IC1 under a primary system, simultaneously, the second pulse signal of 1PPS is generated in a locking mode, the signals are transmitted to an external synchronization input of a secondary system by the primary system and are used as reference signals of a first synchronous clock generator IC1, and then high-precision system clocks synchronous with the reference signals are generated through a digital phase-locked loop, so that the synchronization of the frequency and the phase of each node under a cascade system is ensured;
(3) frequency self-adaptation:
the cascade system is formed by combining a plurality of radio frequency transceivers, aiming at a non-cascade system, namely an independent radio frequency transceiver, aiming at a multi-clock domain and a multi-time source, 3 frequency signals are respectively a 1PPS first signal generated by a GPS, a synchronous Ethernet clock/optical fiber recovery clock second signal, under the cascade system, an external synchronous signal of a secondary system is connected with a 1PPS signal generated by an AD9548 in a primary system to form an external synchronous third signal, and the optimal frequency and time of the system are determined by adopting a frequency self-adaption and time optimal algorithm;
the frequency self-adaptation comprises two parts, wherein the first part is a clock generation and locking unit, each clock required by the system is generated by using a circuit taking a synchronous clock generator ICA as a main chip, and a 1PPS signal is simultaneously locked and generated and is used as a frequency synchronization signal under a cascade system; the synchronous Ethernet clock/optical fiber recovery clock comes from an optical port part in the system, and different clocks are selected according to different protocols; the second part is an algorithm unit which is composed of a singlechip ICB and a synchronous clock generator ICA, software codes are stored in an RAM in the chip, an external 8MHz crystal oscillator is used for providing time signals for the singlechip, an onboard power supply is used for supplying power, the synchronous clock generator ICA and the singlechip ICB are connected and communicated through a 12C bus, the algorithm unit and the synchronous clock generator ICA have the same input, a first signal, a second signal and a third signal are respectively input into the synchronous clock generator ICA and the singlechip ICB through a first coupling capacitor A and a second coupling capacitor B, clocks of all interfaces are monitored and sequenced according to priority levels of the clocks at different interfaces, then corresponding registers passing through the synchronous clock generator ICA are configured, so that the synchronous clock generator ICA selects the clock with the highest priority level as the input of a reference to further generate the clocks used in the system, the priority order of each interface is external synchronous clock, GPS/1PPS, synchronous Ethernet clock/optical fiber recovery clock from high to low; the single chip microcomputer only sequences input clock signals, and configures corresponding registers of the synchronous clock generator ICA through the 12C bus according to a sequencing result to control the synchronous clock generator ICA to open corresponding clock reference input channels, so that the synchronous clock generator ICA can obtain high-quality external input clocks, and further generate each clock signal used by the system.
2. The method of claim 1, wherein the first programmable logic array IC2 is of the type EP3C 5.
3. The method for time synchronization and frequency synchronization in a cascaded radio frequency transceiver system as claimed in claim 1, wherein the synchronous clock generator ICA is a first synchronous clock generator IC1 or a second synchronous clock generator IC2, a first synchronous clock generator IC1 at a primary side and a second synchronous clock generator IC2 at a secondary side.
4. The method for time synchronization and frequency synchronization under a radio frequency transceiver cascade system according to claim 1, wherein the single chip microcomputer ICB is an embedded microcontroller having a model number of STM32F101C6T6 ATR.
5. The method for time synchronization and frequency synchronization under a radio frequency transceiver cascade system as claimed in claim 1, wherein the first optical port module G1, the second optical port module G2 and the third optical port module G3 are QSFP-40G-SR 4.
6. The method for time synchronization and frequency synchronization under a radio frequency transceiver cascade system according to claim 1, wherein the secondary is composed of a plurality of secondary in series with the same structure, each secondary is composed of a synchronous clock generator ICA and an algorithm unit, the equipment of the algorithm unit is composed of a single chip microcomputer STM32F101C6T6ATR and a matched external circuit, the content of the algorithm is realized in the single chip microcomputer, AD9548 is a chip which not only has a digital phase-locked loop function, but also can generate a clock signal, a 1PPS signal generated by GPS is a first signal, a synchronous ethernet clock/fiber recovery clock is a second signal, and an external synchronization signal of the secondary system and a 1PPS signal generated by the AD9548 in the primary system are external synchronization third signals under the cascade system; the first coupling capacitor A consists of a first capacitor C1, a second capacitor C2 and a third capacitor C3, one end of the first capacitor C1 is connected with a GPS/1PPS signal end, the other end of the first capacitor C1 is connected with a signal input end 1 of an AD9548 synchronous clock generator ICA, one end of the second capacitor C2 is connected with a synchronous clock signal, the other end of the second capacitor C1 is connected with a synchronous clock signal input end 2 of the AD9548 synchronous clock generator ICA, one end of the third capacitor C3 is connected with a recovered clock signal, and the other end of the third capacitor C3 is connected with a recovered clock signal input end 3 of the AD9548 synchronous clock generator ICA; the second coupling capacitor B consists of a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6, one end of the sixth capacitor C6 is connected with a GPS/1PPS signal end, the other end of the sixth capacitor C6 is connected with a signal input end 3 of a single chip microcomputer STM32F101C6T6ATR, one end of the fifth capacitor C5 is connected with a synchronous clock signal, the other end of the fifth capacitor C5 is connected with a synchronous clock signal input end 2 of the single chip microcomputer STM32F101C6T6ATR, one end of the fourth capacitor C4 is connected with a recovered clock signal, and the other end of the fourth capacitor C4 is connected with a recovered clock signal input end 1 of the;
the optical port module of the PC and the optical port module of the system carry out data transmission through an optical port, simultaneously the time of Ethernet or GPS in the PC main station is transmitted as one of time inputs, the GPS module receives satellite signals to generate corresponding time information as another time source of the system, in the secondary system, the secondary system receives the time sent by the primary FPGA serial port as one of the time sources of the secondary system, and the time is preferably selected according to the three time sources; the synchronous Ethernet clock/optical fiber recovery clock selects different clocks according to different protocols in the transmission process, in a primary system in the cascade system, a 1PPS signal generated by a GPS and an external synchronous clock are selected as alternatives when in application, in a secondary system, the source of the external synchronous clock is the 1PPS signal generated by an AD9548 of the primary system, and the 1PPS signal generated by the AD9548 is taken as a frequency synchronous signal of the whole cascade system.
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