CN109495203A - A kind of recovery system of PTP from clock - Google Patents
A kind of recovery system of PTP from clock Download PDFInfo
- Publication number
- CN109495203A CN109495203A CN201811620790.8A CN201811620790A CN109495203A CN 109495203 A CN109495203 A CN 109495203A CN 201811620790 A CN201811620790 A CN 201811620790A CN 109495203 A CN109495203 A CN 109495203A
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- master clock
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The present invention provides a kind of PTP from the recovery system of clock, it is characterized in that, it include: PTP module, timestamp is beaten to PTP data packet in PHY layer (physical layer), the PTP of output high-precision, high stability when system configuration is at master clock source, the response PTP synchronization request of hardware level and hardware self-timing send PTP synchronization packet；It when system configuration Cheng Congzhong, can receive, send PTP synchronization event message and general message, optimal PTP master clock source is selected according to best master clock source selection algorithm, calculate PTP synchronization circuit delay and the local clock jitter with PTP master clock source；Input signal processing and system clock frequency adjust module, are used to adjust the frequency of clock signal of system, are locked to system clock frequency in external perimysium reference reference signal or PTP input；And local clock module, it is used to provide local reference clock for system, the basis as system accuracy.
Description
Technical field
The present invention relates to PTP synchronization technologies more particularly to PTP timestamp to obtain, sends PTP synchronization packet and response automatically
PTP synchronization request and clock frequency modulation, Phase Lock Technique, recovery system of specifically a kind of PTP from clock.
Background technique
The end-to-end transparent clock equipment of PTP as common bridge, router or interchanger, forwarding clock equipment with
From all messages of interaction between clockwork.Typically, the residence time bridge of end-to-end transparent clock equipment is for interactive
PTP event message can calculate residence time of the message Jing Guo the equipment, and by the residence time in the PTP event message
One specific fields is added up, read after receiving PTP event message from clockwork the residence time wherein carried and its
It is synchronous that his timestamp carries out clock.And calculating resident used timestamp (namely residence time) is by transparent clock equipment base
It is generated in local clock.
But the local clock of actually end-to-end transparent clock equipment is inaccurate, and not necessarily begins with clock equipment
It keeps synchronizing eventually, so will also have error based on the residence time that local clock calculates, to influence from clockwork
Clock synchronization accuracy.
For this purpose, the end-to-end transparent clock equipment of PTP is usually that basis had done the correction of uplink residence time in existing method
Clock equipment and local clock equipment to the sending cycle of Sync message in PTP event message, calculate master clock and local
The ratio (i.e. the frequency shift (FS) factor, Ff) of clock rate, then corrects local clock according to the ratio.But this method is deposited
In the excessive problem of the local clock rate and master clock rate error of acquisition, such as the shadow by various factors such as network environments
It rings, each Sync message that the end-to-end transparent clock equipment of PTP periodically sends master clock, can not be inherently strictly according to spy
What fixed cycle was forwarded, can only substantially estimate a sending cycle to Sync message, so as to cause the essence of residence time
Exactness is difficult to ensure.
Summary of the invention
In order to solve the above technical problems, overcome deficiency in the prior art, a kind of restorer of PTP from clock is provided
System.
Technical solution used by the present invention solves the above problems is: a kind of PTP exists from the recovery system of clock, feature
In, comprising: PTP module is beaten timestamp to PTP data packet in PHY layer (physical layer), is exported when system configuration is at master clock source
In high precision, the PTP of high stability, the response PTP synchronization request of hardware level and hardware self-timing send PTP synchronization packet；System
It when being configured to from clock, can receive, send PTP synchronization event message and general message, selected according to best master clock source selection algorithm
Optimal PTP master clock source is selected, PTP synchronization circuit delay and the local clock jitter with PTP master clock source are calculated；At input signal
Reason and system clock frequency adjust module, are used to adjust the frequency of clock signal of system, are locked to system clock frequency outer
In ministerial standard reference signal or PTP input；And local clock module, it is used to provide local reference clock for system, as
The basis of system accuracy.
Further, the invention also includes external perimysium reference reference source input modules, when system configuration is at master clock source,
System will lock onto external perimysium reference reference signal, thus for system as PTP master clock source when accurate, stable ginseng is provided
Examine source；And local standard clock signal generating module, it is used to generate the local synchronization signal of standard.
Further, the PTP can configure system operating mode from the recovery system of clock, make system as PTP master clock
Source or PTP can beat timestamp to PTP data packet in PHY layer (physical layer) from clock；It, can when the system is as PTP master clock source
It is requested with the response PTP of hardware level from the PTP synchronization of clock and hardware self-timing sends PTP synchronization packet, so that it is defeated to expand PTP
Capacity out when as PTP from clock, can receive, send PTP synchronization event message and general message, can be according to best master clock
Selection algorithm selects optimal PTP master clock source, calculates PTP synchronization circuit delay and the local clock jitter with PTP master clock source；
Adjustment system clock frequency is to quickly be locked in externally input standard reference signal or PTP input；The system root
The local clock oscillator that different accuracy and stability are selected according to actual demand, to reach the local of different accuracy and stability
Standard clock signal.
Compared with prior art, the invention has the following advantages:
1, flexible system configuration is realized, can be configured to PTP master clock or PTP from clock；
2, timestamp can be beaten to PTP packet in physical layer, hardware can send or respond automatically PTP synchronization；
3, it provides time phase measurement and keeps the circuit of algorithm, provide brilliant retention performance.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is structure composition schematic diagram of the invention.
Fig. 2 is the structural schematic diagram in the embodiment of the present invention 1.
Specific embodiment
The recovery system of a kind of PTP from clock, comprising: PTP module beats the time to PTP data packet in PHY layer (physical layer)
Stamp, the PTP of output high-precision, high stability when system configuration is at master clock source, the response PTP synchronization request of hardware level and hard
Part self-timing sends PTP synchronization packet；It when system configuration Cheng Congzhong, can receive, send PTP synchronization event message and general report
Text selects optimal PTP master clock source according to best master clock source selection algorithm, calculates PTP synchronization circuit delay and local and PTP
The clock jitter of master clock source；Input signal processing and system clock frequency adjust module, are used to adjust clock signal of system
Frequency, be locked to system clock frequency in external perimysium reference reference signal or PTP input；And local clock module, it uses
In providing local reference clock for system, the basis as system accuracy.It further include external perimysium reference reference source input module,
When system configuration is at master clock source, system be will lock onto external perimysium reference reference signal, to be system as PTP master clock source
When accurate, stable reference source is provided；And local standard clock signal generating module, it is used to generate the local same of standard
Walk signal.
The PTP can configure system operating mode from the recovery system of clock, make system as PTP master clock source or PTP from
Clock can beat timestamp to PTP data packet in PHY layer (physical layer)；It, can be with hardware level when the system is as PTP master clock source
Response PTP from the PTP synchronization of clock request and hardware self-timing send PTP synchronization packet, thus expand PTP output capacity,
It when as PTP from clock, can receive, send PTP synchronization event message and general message, can be selected according to best master clock selection algorithm
Optimal PTP master clock source is selected, PTP synchronization circuit delay and the local clock jitter with PTP master clock source are calculated；When adjustment system
Clock frequency is to quickly be locked in externally input standard reference signal or PTP input；The system is according to actual needs
The local clock oscillator for selecting different accuracy and stability, the local standard clock to reach different accuracy and stability are believed
Number.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Embodiment 1.
As shown in Figure 1, a kind of recovery system of PTP from clock, meets subway system, high-speed railways, electric system and friendship
Requirement of the time synchronism apparatus of way system etc. to clock accuracy, including external perimysium reference reference source input module, PTP mould
Block, local clock module, input signal processing and system clock frequency adjust module, local standard clock signal generating module.
External perimysium reference reference signal input module is used such as the standard signal that GPS or Big Dipper satellite signal receiving module provide
In when system configuration is at master clock source, system be will lock onto external perimysium reference reference signal, thus when main as PTP for system
Accurate, stable reference source is provided when clock, when this system is configured to from clock, this module can not used；PTP module is used
In processing PTP synchronization data, the exportable PTP when system is configured to master clock is configured in system from clock Shi Laijin
Row PTP input, can beat timestamp to PTP data packet in PHY layer (physical layer)；Local clock module provides local ginseng for system
Clock is examined, is the basis of system accuracy；Input signal processing and system clock frequency adjustment module mainly to input reference source into
Row processing, the measurement of frequency, phase is carried out including the external perimysium reference reference signal to input, to PTP input processing, is generated local
Data needed for clock frequency adjustment refer to local standard clock lock to external perimysium reference so as to adjust system clock frequency
On signal or PTP input；Local standard clock signal generating module can produce the local synchronization signal of standard.
As shown in Fig. 2, CPU is controlled for system administration, and network communication, the realization including PTP protocol；Standard signal input
Module is for receiving external perimysium reference reference signal, and such as GPS or Big Dipper satellite signal, PTP interface module is same for receiving transmission PTP
Information is walked, external perimysium reference reference signal and PTP synchronization information can all be supplied to field programmable gate array (FPGA), in FPGA
It realizes to the adjustment locking phase of clock signal and the hardware parser of PTP synchronization.Mainly there is following functions module: input signal in FPGA
Frequency, phase processing module, frequency, phase adjustment control information-generation module, and clock frequency adjusts module, PTP module.
Clock adjustment the phase-locked function is mainly realized with FPGA, wherein input is believed when system configuration is at PTP master clock source
Number frequency, phase processing module are mainly used to handle externally input standard reference signal, mention from external perimysium reference reference signal
Reference information needed for taking out the adjustment of the system clocks such as frequency, phase；When system configuration at PTP from clock when, system will be defeated from PTP
Reference information needed for entering to extract the adjustment of the system clocks such as frequency, phase.Frequency, phase adjustment control information-generation module are main
It realizes and the information such as the frequency of reference signal, phase is converted into frequency, the control information of phase adjustment, thus control system frequency
The adjustment of rate, phase.Clock frequency adjusts module and realizes the local reference clock signal provided local high steady oscillator module
It is handled, clock frequency needed for synthesis system is locked to it in external perimysium reference reference signal.PTP module is in FPGA
Monitoring of the middle realization to ethernet communication, the main hardware level for realizing PTP parse function, make PTP synchronization communication can be in PHY layer
(physical layer) beats timestamp, and when system configuration is at PTP master clock source, CPU can configure the PTP mould in FPGA
Block allows PTP module to regularly send the response PTP synchronization request of PTP synchronization packet and hardware level；System configuration at PTP from
When clock, CPU can receive, send the event message and general message of PTP synchronization, can be according to best master clock selection algorithm
The hard timestamp for selecting optimal PTP master clock source, and being obtained according to PTP module, calculate PTP synchronization circuit delay and it is local with
The clock jitter of PTP master clock source.
It should be pointed out that being above schematical by the detailed description that preferred embodiment carries out technical solution of the present invention
And not restrictive.Those skilled in the art can be to recorded in embodiment on the basis of reading description of the invention
Technical solution modify or equivalent replacement of some of the technical features, and these are modified or replaceed, not
The essence of corresponding technical solution is set to be detached from the range of technical solution of the embodiment of the present invention.
Claims (3)
1. a kind of PTP is from the recovery system of clock characterized by comprising
PTP module is beaten timestamp to PTP data packet in PHY layer (physical layer), is exported when system configuration is at master clock source high-precision
The PTP of degree, high stability, the response PTP synchronization request of hardware level and hardware self-timing send PTP synchronization packet；System configuration
It when Cheng Congzhong, can receive, send PTP synchronization event message and general message, most according to the selection of best master clock source selection algorithm
Excellent PTP master clock source calculates PTP synchronization circuit delay and the local clock jitter with PTP master clock source；
Input signal processing and system clock frequency adjust module, are used to adjust the frequency of clock signal of system, when making system
On clock Frequency Locking to external perimysium reference reference signal or PTP input；And
Local clock module is used to provide local reference clock for system, the basis as system accuracy.
2. a kind of PTP according to claim 1 is from the recovery system of clock, which is characterized in that further include external perimysium reference reference
Source input module, when system configuration is at master clock source, system be will lock onto external perimysium reference reference signal, to be system
Accurate, stable reference source is provided when as PTP master clock source；And local standard clock signal generating module, it is used for
The local synchronization signal of generation standard.
3. a kind of PTP according to claim 1 or 2 is from the recovery system of clock, which is characterized in that the PTP is from the extensive of clock
Complex system can configure system operating mode, make system as PTP master clock source or PTP from clock, can be right in PHY layer (physical layer)
PTP data packet beats timestamp；It, can be with response PTP synchronization of the PTP from clock of hardware level when the system is as PTP master clock source
Request and hardware self-timing send PTP synchronization packet, to expand the capacity of PTP output, when as PTP from clock, can receive,
PTP synchronization event message and general message are sent, optimal PTP master clock source, meter can be selected according to best master clock selection algorithm
Calculate PTP synchronization circuit delay and the local clock jitter with PTP master clock source；Adjustment system clock frequency is to quickly lock
Onto externally input standard reference signal or PTP input；The system selects different accuracy and stability according to actual needs
Local clock oscillator, to reach the local standard clock signal of different accuracy and stability.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811620790.8A CN109495203A (en) | 2018-12-28 | 2018-12-28 | A kind of recovery system of PTP from clock |
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| CN201811620790.8A CN109495203A (en) | 2018-12-28 | 2018-12-28 | A kind of recovery system of PTP from clock |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111884749A (en) * | 2020-07-24 | 2020-11-03 | 中国科学院精密测量科学与技术创新研究院 | High-precision fixed-period PTP time synchronization method based on clock phase splitting |
| CN112910590A (en) * | 2021-01-28 | 2021-06-04 | 广州广哈通信股份有限公司 | Clock synchronization system and method |
| CN113055149A (en) * | 2021-02-20 | 2021-06-29 | 郑州中科集成电路与信息系统产业创新研究院 | Time synchronization and frequency synchronization method under radio frequency transceiver cascade system |
| CN113381829A (en) * | 2020-02-25 | 2021-09-10 | 迈络思科技有限公司 | PHC chain |
| CN113644910A (en) * | 2021-08-18 | 2021-11-12 | 合肥新港海岸科技有限公司 | Clock generation method and system based on standard frequency signal |
| CN114337890A (en) * | 2021-11-25 | 2022-04-12 | 伟乐视讯科技股份有限公司 | Multi-terminal broadcast synchronization system and method based on PTP network synchronization |
| CN114421956A (en) * | 2022-04-01 | 2022-04-29 | 浙江赛思电子科技有限公司 | Frequency and phase discrimination control system and method |
| CN115714628A (en) * | 2022-10-14 | 2023-02-24 | 成都金诺信高科技有限公司 | Communication base station time synchronization system |
| CN119254376A (en) * | 2024-12-06 | 2025-01-03 | 杭州初灵信息技术股份有限公司 | A time synchronization device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113381829A (en) * | 2020-02-25 | 2021-09-10 | 迈络思科技有限公司 | PHC chain |
| CN111884749A (en) * | 2020-07-24 | 2020-11-03 | 中国科学院精密测量科学与技术创新研究院 | High-precision fixed-period PTP time synchronization method based on clock phase splitting |
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| CN113055149B (en) * | 2021-02-20 | 2022-09-06 | 郑州中科集成电路与系统应用研究院 | Time synchronization and frequency synchronization method under radio frequency transceiver cascade system |
| CN113055149A (en) * | 2021-02-20 | 2021-06-29 | 郑州中科集成电路与信息系统产业创新研究院 | Time synchronization and frequency synchronization method under radio frequency transceiver cascade system |
| CN113644910A (en) * | 2021-08-18 | 2021-11-12 | 合肥新港海岸科技有限公司 | Clock generation method and system based on standard frequency signal |
| CN113644910B (en) * | 2021-08-18 | 2022-03-25 | 合肥新港海岸科技有限公司 | Clock generation method and system based on standard frequency signal |
| CN114337890A (en) * | 2021-11-25 | 2022-04-12 | 伟乐视讯科技股份有限公司 | Multi-terminal broadcast synchronization system and method based on PTP network synchronization |
| CN114421956B (en) * | 2022-04-01 | 2022-07-01 | 浙江赛思电子科技有限公司 | Frequency and phase discrimination control system and method |
| CN114421956A (en) * | 2022-04-01 | 2022-04-29 | 浙江赛思电子科技有限公司 | Frequency and phase discrimination control system and method |
| CN115714628A (en) * | 2022-10-14 | 2023-02-24 | 成都金诺信高科技有限公司 | Communication base station time synchronization system |
| CN119254376A (en) * | 2024-12-06 | 2025-01-03 | 杭州初灵信息技术股份有限公司 | A time synchronization device |
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