CN113053904A - Three-dimensional flash memory structure and electronic equipment - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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Abstract
本申请公开了一种三维闪存结构和电子设备，其中，三维闪存结构包括：衬底结构；介质堆叠层，设于衬底结构的一侧，介质堆叠层上设有多个存储单元以及第一选择开关，第一选择开关设于存储单元远离衬底结构的一侧，其中，衬底结构靠近介质堆叠层的一侧设有平面场效晶体管，第一选择开关和/或平面场效晶体管用于选择多个存储单元中的至少一个。本申请中，在生产过程中，仅需在介质堆叠层上设置存储单元和作为上选择开关的第一选择开关即可，将作为下选择开关的平面场效晶体管设置在衬底结构的平面位置，由于平面场效晶体管的开关特性较好，可在不影响三维闪存结构整体的架构的基础上，提升器件整体的可靠性。
The present application discloses a three-dimensional flash memory structure and an electronic device, wherein the three-dimensional flash memory structure includes: a substrate structure; A selection switch, the first selection switch is arranged on the side of the memory cell away from the substrate structure, wherein the side of the substrate structure close to the dielectric stack layer is provided with a planar field effect transistor, and the first selection switch and/or the planar field effect transistor are used for for selecting at least one of the plurality of memory cells. In the present application, in the production process, only the storage unit and the first selection switch as the upper selection switch need to be arranged on the dielectric stack layer, and the planar field effect transistor as the lower selection switch is arranged in the plane position of the substrate structure , Due to the better switching characteristics of the planar field effect transistor, the overall reliability of the device can be improved without affecting the overall architecture of the three-dimensional flash memory structure.
Description
Technical Field
The application belongs to the technical field of electronic equipment, and particularly relates to a three-dimensional flash memory structure and electronic equipment.
Background
With the continuous improvement of the storage technology, the storage density and the cost of the flash memory are comprehensively considered, compared with the planar two-dimensional flash memory structure in fig. 1, the three-dimensional flash memory with a three-dimensional structure as shown in fig. 2 is provided in the prior art, in the production process, the selection switches of the three-dimensional flash memory are all positioned in the channel etching holes, and the reliability of the whole structure work is influenced because the depth-to-width ratio of the channel holes is larger, the structure is closer to the substrate, and the process is more uncontrollable.
Disclosure of Invention
The present application is directed to a three-dimensional flash memory structure and an electronic device, which at least solve the problem of poor device characteristics of a lower selection switch.
In order to solve the technical problem, the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a three-dimensional flash memory structure, including: a substrate structure; the dielectric stack layer is arranged on one side of the substrate structure, a plurality of storage units and a first selection switch are arranged on the dielectric stack layer, the first selection switch is arranged on one side, far away from the substrate structure, of the storage units, a planar field effect transistor is arranged on one side, close to the dielectric stack layer, of the substrate structure, and the first selection switch and/or the planar field effect transistor are/is used for selecting at least one of the plurality of storage units.
According to the three-dimensional flash memory structure provided by the embodiment of the application, the substrate structure is used as a substrate of the whole switch structure, namely a main material of the flash memory structure, and the dielectric stack layer comprising the memory cells and the first selection switch is arranged on the substrate structure, so that in the using process, the stored information can be stored or read inwards through the dielectric stack layer.
Particularly, in the production process, only the memory cell and the first selection switch serving as the upper selection switch need to be arranged on the dielectric stack layer, and the planar field effect transistor serving as the lower selection switch is arranged at the planar position of the substrate structure.
It should be noted that the first selection switch is disposed on the other side of the plurality of memory cells, and in the structure, the first selection switch and the planar field effect transistor sandwich the plurality of memory cells, so as to select one or more memory cells under the combined action of the first selection switch and the planar field effect transistor.
Wherein, when selecting one or more memory cells, the selection is mainly realized by a first selection switch or a planar field effect transistor, compared with the prior art, the upper selection switch and the lower selection switch are both arranged in the channel etching hole, resulting in a structure closer to the substrate structure, the less controllable the process, the worse the device characteristics and uniformity of the lower selection switch near the substrate structure, thereby resulting in a lower reliability of operation during the time period, in the solution of the present application, by providing a planar field effect transistor on the substrate structure, it can be used as another selection switch, and by means of the above-mentioned improvement, on the basis of keeping the basic circuit unchanged, the position of lower selection switch can be changed, therefore, on the basis of not increasing larger process cost, on one hand, the switching characteristic can be greatly improved, and on the other hand, the overall reliability of the device can be improved.
In a second aspect, an embodiment of the present application provides an electronic device, including: a body; the switch structure in the above embodiment is disposed on the body.
According to the electronic device provided by the embodiment of the application, the electronic device includes a body and the switch structure of any of the above embodiments, wherein the switch structure is disposed on the body, specifically, the switch structure may be disposed on a main control board of the body or disposed on another circuit board of the body.
It is worth mentioning that the variety of electronic devices is various, such as: the mobile phone, the tablet computer, the electronic reader and other devices which need the camera module.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a two-dimensional flash memory structure in the prior art;
FIG. 2 is a schematic diagram of a three-dimensional flash memory structure according to the prior art;
FIG. 3 is a schematic structural diagram of a three-dimensional flash memory structure according to one embodiment of the present application;
FIG. 4 is a schematic structural diagram of a three-dimensional flash memory structure according to one embodiment of the present application;
FIG. 5 is a schematic structural diagram of a three-dimensional flash memory structure according to one embodiment of the present application;
FIG. 6 is a schematic structural diagram of a three-dimensional flash memory structure according to one embodiment of the present application;
FIG. 7 is a schematic structural diagram of a three-dimensional flash memory structure according to one embodiment of the present application;
FIG. 8 is a schematic structural diagram of an electronic device according to one embodiment of the present application.
Reference numerals:
100: a three-dimensional flash memory structure; 102: a substrate structure; 104: a dielectric stack layer; 1042: a storage unit; 1044: a first selection switch; 106: a planar field effect transistor; 1062: a conductive layer; 1064: a source electrode; 1066: a drain electrode; 1068: a gate electrode; 108: a sacrificial layer; 110: an isolation layer; 112: a common source electrode; 114: a channel structure; 116: a dielectric film; 200: an electronic device; 210: a body.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The features of the terms first and second in the description and in the claims of the present application may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more unless otherwise specified. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
In the description of the present application, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present application.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
A three-dimensional flash memory structure and an electronic device according to embodiments of the present application are described below with reference to fig. 3 to 8.
As shown in fig. 4, the present application provides an embodiment of a three-dimensional flash memory structure 100, which includes a substrate structure 102 and a dielectric stack layer 104, where the substrate structure 102 is used as a base of an entire switch structure, that is, a main material of the flash memory structure, and by disposing the dielectric stack layer 104 including a memory cell 1042 and a first selection switch 1044 on the substrate structure 102, during a use process, stored information can be stored or read inward through the dielectric stack layer 104, it should be emphasized that a planar field effect transistor 106 is disposed on the substrate structure 102, and the planar field effect transistor 106 and the first selection switch 1044 are respectively used as a selection switch for selecting the memory cell 1042, that is, the planar field effect transistor 106 and the first selection switch 1044 are respectively an upper selection switch and a lower selection switch, so as to select the memory cell 1042 on a corresponding word line through the planar field effect transistor 106 and the first selection switch 1044.
In particular, in the production process, only the memory cell 1042 and the first selection switch 1044 as an upper selection switch need to be disposed on the dielectric stack layer 104, and the planar field effect transistor 106 as a lower selection switch is disposed at the planar position of the substrate structure 102, so that the overall reliability of the device can be improved without affecting the overall architecture of the three-dimensional flash memory structure 100 due to the better switching characteristics of the planar field effect transistor 106.
It should be noted that the first selection switch 1044 is disposed on the other side of the plurality of memory cells 1042, and in the structure, the first selection switch 1044 and the planar field effect transistor 106 sandwich the plurality of memory cells 1042, so that one or more memory cells 1042 are selected under the combined action of the first selection switch 1044 and the planar field effect transistor 106.
Wherein the selection of one or more memory cells 1042 is achieved primarily by the first selection switch 1044 or the planar field effect transistor 106, as opposed to the prior art in which both the upper selection switch and the lower selection switch are disposed in trench etch holes, resulting in a structure closer to the substrate structure 102, the less controllable the process, the less device characteristics and uniformity of the lower selection switch disposed near the substrate structure 102, resulting in a lower reliability of operation during which, in the solution of the present application, by providing the planar field effect transistor 106 on the substrate structure 102, it can be used as another selection switch, and by means of the above-mentioned improvement, on the basis of keeping the basic circuit unchanged, the position of lower selection switch can be changed, therefore, on the basis of not increasing larger process cost, on one hand, the switching characteristic can be greatly improved, and on the other hand, the overall reliability of the device can be improved.
Further, as shown in fig. 3, the planar field effect transistor 106 specifically includes: a conductive layer 1062 and a source 1064 disposed on one side of the conductive layer 1062; and a drain 1066 disposed on the other side of the conductive layer 1062, wherein a gate 1068 is disposed at a position of the dielectric stack layer 104 corresponding to the conductive layer 1062.
Planar field effect transistor 106 includes a conductive layer 1062, a source 1064, a drain 1066 and a gate 1068, wherein the source 1064 and the drain 1066 are disposed on two sides of the conductive layer 1062, and the gate 1068 is disposed in the dielectric stack layer 104 corresponding to the conductive layer 1062, it should be understood by those skilled in the art that the source 1064, the drain 1066, and the gate 1068 are all pins, the source 1064 is used for collecting current, the drain 1066 is used for emitting, and the gate 1068 is used as a control pin of the whole planar fet 106, after applying a voltage to the gate 1068, an electric field is generated in the isolation layer 110 between the gate 1068 and the substrate structure 102 from the gate 1068 to the substrate structure 102, and two capacitors are formed on the dielectric stack 104 at this time, the gate voltage is equal to the charging voltage, and is attracted by the voltage, and a large number of electrons are collected at the other end of the capacitor to form a conductive channel, so that the planar fet 106 starts to be turned on.
Of course, the conductive layer 1062 is disposed between the source 1064 and the drain 1066 to allow electrons to move between the source 1064 and the drain 1066, so that the planar fet 106 can operate normally.
Further, the grid 1068 is a mesh-like or spiral electrode composed of metal filaments. One or more electrodes having a fine mesh or spiral shape arranged between an anode and a cathode in a multi-polar electron tube function to control the electric field intensity on the surface of the cathode to thereby change the emission current of the cathode or capture secondary emitted electrons.
Further, as shown in fig. 4, the dielectric stack layer 104 specifically includes: a plurality of sacrificial layers 108 and a plurality of isolation layers 110 are alternately disposed, wherein one isolation layer 110 is in contact with the substrate structure 102.
The dielectric stack layer 104 includes a plurality of sacrificial layers 108 and isolation layers 110, specifically, the isolation layers 110 serve as isolation, the sacrificial layers 108 are used for implementing a subsequent process for forming the memory cells 1042, wherein the sacrificial layers 108 and the isolation layers 110 are alternately disposed, that is, one isolation layer 110 is disposed on each side of each sacrificial layer 108, so as to ensure that the memory cells 1042 disposed on two adjacent sacrificial layers 108 are not connected to each other to cause short circuit during subsequent process, thereby implementing a protection circuit, furthermore, by disposing one of the isolation layers 110 in contact with the substrate structure 102, on one hand, in order to protect the memory cells 1042 generated by the subsequent process from directly contacting the substrate structure 102, thereby implementing a certain protection function, on the other hand, by disposing the planar field effect transistor 106 as a lower selection switch on the substrate structure 102, and by contacting one isolation layer 110 with the substrate structure 102, the structural requirements of the planar fet 106 can be effectively fulfilled, i.e. an electric field is generated on the isolation layer 110 in contact with the substrate structure 102, which is directed from the gate 1068 to the substrate structure 102, thereby forming two capacitors, which is advantageous for the arrangement of the planar fet 106.
Further, the plurality of sacrificial layers 108 and the plurality of isolation layers 110 are disposed in a direction perpendicular to the extending direction of the substrate structure 102.
By limiting the extension of the sacrificial layer 108 and the isolation layer 110 toward the direction perpendicular to the extending direction of the substrate structure 102, that is, the arrangement of the sacrificial layer 108 and the isolation layer 110 is perpendicular to the extending direction of the substrate structure 102, when the substrate structure 102 extends along the first direction, the arrangement direction of the sacrificial layer 108 and the isolation layer 110 is perpendicular to the first direction, so that during the manufacturing process, the memory cell 1042 in the form of a stack can be formed, which is more beneficial to improving the storage density of the flash memory structure.
As shown in fig. 7, further, the three-dimensional flash memory structure 100 further includes: and the common source 112 is arranged on the dielectric stack layer 104, one end of the common source 112 is connected to the source 1064, and the other end extends to a side far away from the substrate structure 102.
The common source 112 is disposed on the dielectric stack layer 104, and by connecting one end of the common source 112 with the source 1064 of the substrate structure 102, the current direction of the whole device can be controlled, i.e. a current channel can be formed more easily.
Wherein the common source 112 is connected to the source 1064, and the other end extends to a side away from the substrate structure 102, and a plurality of sacrificial layers 108 and isolation layers 110 are disposed on the dielectric stack layer 104 along a direction perpendicular to the extending direction of the substrate structure 102, so as to facilitate the connection between the memory cells 1042 of the first selection switch 1044 formed on the sacrificial layers 108 and the common source 112.
It will be appreciated by those skilled in the art that source 1064, which is equivalent to ground in the circuit, is usually at a lower potential and does not affect the current flow.
As shown in fig. 5 to 7, further, the three-dimensional flash memory structure 100 further includes: and a channel structure 114 disposed on the dielectric stack layer 104, wherein one end of the channel structure 114 is connected to the drain 1066, and the other end extends to a side away from the substrate structure 102.
By disposing the channel structure 114 on the dielectric stack layer 104 and connecting one end of the channel structure 114 with the drain 1066, further, the extending direction of the channel structure 114 is perpendicular to the extending direction of the substrate structure 102, so as to reduce the length of the channel structure 114, and facilitate the subsequent processing and manufacturing of the memory cell 1042 and the first selection switch 1044 on the basis of ensuring the integrity of the memory cell 1042.
Further, as shown in fig. 6 and 7, the three-dimensional flash memory structure 100 further includes: a plurality of dielectric films 116, disposed corresponding to the memory cells 1042, are deposited in the channel structure 114, and the dielectric films 116 can form a memory medium layer.
By depositing a plurality of dielectric films 116 corresponding to the memory cells 1042 in the channel structure 114, a storage dielectric layer can be formed when the dielectric films 116 are stacked, so as to facilitate the subsequent arrangement of the memory cells 1042, and further, by sequentially depositing different dielectric films 116 in the channel structure 114 by a chemical vapor deposition method, the dielectric films 116 can be stacked to form a storage dielectric layer.
Further, at least a portion of the sacrificial layer 108 and at least a portion of the isolation layer 110 on the dielectric stack layer 104 are etched by an etching process to form a channel structure 114.
The channel structure 114 is obtained by processing the sacrificial layer 108 and the isolation layer 110 through an etching process, and it can be understood that the etching process is a processing method in which a portion of the substrate to be protected is covered by a silk-screen printing or silk-screen printing method, an unnecessary portion is etched by a chemical or electrochemical method, and finally the protection film is removed to obtain a product.
The isolation layer 110 is made of silicon oxide, and the sacrificial layer 108 is made of silicon nitride.
It can be understood that the physical and chemical properties of silicon oxide are stable, which can resist chemical erosion and maintain the stability of the structure, and the sacrificial layer 108 of silicon nitride is selected for use, which can be replaced by the metal conductive layer 1062 by using the replacement gate process, so as to form the complete memory cell 1042 and the selection switch structure.
In the production of the three-dimensional flash memory structure 100 as in the previous embodiment, this is achieved by the following steps:
as shown in fig. 3, a wafer is selected, the original silicon substrate, i.e., the substrate structure 102, and a lower selection switch (i.e., the planar field effect transistor 106) is formed on the substrate structure 102: in the present application, the MOSFET can be used as a lower selection switch in a 3D NAND (i.e., three-dimensional flash memory structure 100) circuit, by forming a planar metal field effect transistor (MOSFET) using a planar MOSFET process that is now well-established at a corresponding location on a planar silicon substrate.
Subsequently, as shown in fig. 4, an active area dielectric stack layer 104 is formed: alternately depositing silicon oxide isolation layers 110 and silicon nitride sacrificial layers 108 on the surface of the silicon substrate by chemical vapor deposition.
The channel hole is machined on the basis of fig. 4, as shown in fig. 5: etching the stacked structure formed by the silicon nitride sacrificial layer 108 and the silicon oxide isolation layer 110 by an etching process to form a trench etching hole;
as further shown in fig. 6, the channel is formed: different dielectric films 116 are sequentially deposited in the channel by means of chemical vapor deposition, and the dielectric films 116 are stacked to form a basic storage dielectric layer.
Finally, as shown in fig. 7, a memory unit 1042 is formed: the common source 112 is fabricated, the sacrificial layer 108 of silicon nitride is replaced by a metal conductive layer 1062 through a replacement gate process, and finally the complete memory cell 1042 and the select switch structure are formed.
The three-dimensional flash memory structure 100 of the present application can be obtained by processing the raw material through the above process, and a metal semiconductor field effect transistor (MOSFET) (i.e., the planar field effect transistor 106) with a two-dimensional planar structure is fabricated at a corresponding position of the substrate structure 102, and through structural connection, the MOSFET can function as a lower selection switch. The structure of the application changes the position of the lower selection switch from the channel to the plane position through structure adjustment under the condition of keeping the basic circuit unchanged. The MOSFET in the plane position has a mature process and good switching characteristics, and can be used as a lower selection switch, so that the overall reliability of the device is improved. And the structure can be compatible with a peripheral circuit process, and the process cost cannot be greatly improved.
As shown in fig. 8, another embodiment of the present application provides an electronic device 200, including: a body 210; the switch structure in the above embodiments is disposed on the body 210.
According to the electronic device 200 provided in the embodiment of the present application, the electronic device 200 includes a body 210 and the switch structure of any embodiment, where the switch structure is disposed on the body 210, and specifically may be disposed on a main control board of the body 210 or disposed on another circuit board of the body 210.
It is worth noting that the variety of the electronic device 200 is various, such as: the mobile phone, the tablet computer, the electronic reader and other devices which need the camera module.
According to the three-dimensional flash memory structure and the electronic device, in the production process, only the storage unit and the first selection switch serving as the upper selection switch are needed to be arranged on the medium stacking layer, and the planar field effect transistor serving as the lower selection switch is arranged at the planar position of the substrate structure.
In the description herein, reference to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A three-dimensional flash memory structure, comprising:
a substrate structure;
a dielectric stack layer arranged on one side of the substrate structure, wherein the dielectric stack layer is provided with a plurality of memory units and a first selection switch, the first selection switch is arranged on one side of the memory units far away from the substrate structure,
wherein a side of the substrate structure adjacent to the dielectric stack is provided with a planar field effect transistor, and the first selection switch and/or the planar field effect transistor can be used for selecting at least one of the plurality of memory cells.
2. The three-dimensional flash memory structure of claim 1, wherein the planar field effect transistor comprises:
a conductive layer;
the source electrode is arranged on one side of the conducting layer;
a drain electrode arranged on the other side of the conductive layer,
and a grid electrode is arranged at the position of the dielectric stack layer corresponding to the conducting layer.
3. The three-dimensional flash memory structure of claim 2, wherein the dielectric stack layer comprises in particular:
a plurality of sacrificial layers and a plurality of isolation layers alternately arranged,
wherein one of the isolation layers is in contact with the substrate structure.
4. The three-dimensional flash memory structure of claim 3, wherein the plurality of sacrificial layers and the plurality of isolation layers are disposed in a direction perpendicular to an extension direction of the substrate structure.
5. The three-dimensional flash memory structure of claim 3, further comprising:
and the common source electrode is arranged on the medium stack layer, one end of the common source electrode is connected to the source electrode, and the other end of the common source electrode extends to one side far away from the substrate structure.
6. The three-dimensional flash memory structure of claim 3, further comprising:
and the channel structure is arranged on the medium stack layer, one end of the channel structure is connected to the drain electrode, and the other end of the channel structure extends to one side far away from the substrate structure.
7. The three-dimensional flash memory structure of claim 6, further comprising:
and the dielectric films are arranged corresponding to the storage units and deposited in the channel structures, and can form storage dielectric layers.
8. The three-dimensional flash memory structure of claim 7, wherein the channel structure is formed by etching at least a portion of the sacrificial layer and at least a portion of the isolation layer on the dielectric stack layer by an etching process.
9. The three-dimensional flash memory structure of claim 3, wherein the isolation layer is made of silicon oxide and the sacrificial layer is made of silicon nitride.
10. An electronic device, comprising:
a body;
the three-dimensional flash memory structure of any of claims 1-9, disposed on the body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110276362.3A CN113053904A (en) | 2021-03-15 | 2021-03-15 | Three-dimensional flash memory structure and electronic equipment |
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