CN118016651A - Capacitor structure and forming method thereof - Google Patents

Abstract

The present invention provides a capacitor structure and a method for forming the same, wherein the capacitor structure comprises: a substrate; a first dielectric layer located on the substrate; a first electrode portion located in the first dielectric layer, the first electrode portion comprising a plurality of first finger-shaped polar plates, the plurality of first finger-shaped polar plates being arranged in parallel along a first direction; a second electrode portion located in the first dielectric layer, the second electrode portion comprising a second electrode terminal and a plurality of second finger-shaped polar plates connected to the second electrode terminal, the second electrode terminal extending along the first direction, the plurality of second finger-shaped polar plates being arranged along the first direction, and each second finger-shaped polar plate being located between two adjacent first finger-shaped polar plates, so as to improve the storage density of the capacitor structure.

Description

Capacitor structure and method of forming the same

Technical Field

The present invention relates to the technical field of semiconductor manufacturing, and in particular to a capacitor structure and a forming method thereof.

Background technique

In semiconductor integrated circuits, integrated capacitors made on the same chip as transistor circuits are widely used. Its form mainly includes metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors. Wherein, MIM capacitors use upper and lower metals as capacitor plates. It is generally necessary to add photolithography layers to make MIM capacitors. The breakdown voltage of the capacitor dielectric layer and the capacitance size are irreconcilable contradictions. Moreover, plate capacitors generally require larger areas, which is unfavorable for the integration of devices. And MOM capacitors can make capacitors with larger capacity on a relatively small area by using the method combining finger-shaped structures and stacking. In addition, when making MOM capacitors, no extra photoresist layer and mask are needed, so that the manufacturing process is also simpler and has lower cost relative to MIM capacitors.

However, there are still many problems with the MOM capacitors in the prior art.

Summary of the invention

The problem solved by the present invention is to provide a capacitor structure and a method for forming the same, so as to improve the storage density of the capacitor structure.

To solve the above problems, the present invention provides a capacitor structure, comprising: a substrate; a first dielectric layer located on the substrate; a first electrode portion located in the first dielectric layer, the first electrode portion comprising a plurality of first finger-shaped electrode plates, and the plurality of first finger-shaped electrode plates are arranged in parallel along a first direction; a second electrode portion located in the first dielectric layer, the second electrode portion comprising a second electrode end and a plurality of second finger-shaped electrode plates connected to the second electrode end, the second electrode end extends along a first direction, the plurality of second finger-shaped electrode plates are arranged along the first direction, and each of the second finger-shaped electrode plates is located between two adjacent first finger-shaped electrode plates.

Optionally, it further includes: a first interconnect layer overlapping the second electrode terminal; and a first conductive plug structure located between the second electrode terminal and the first interconnect layer.

Optionally, it further includes: a second interconnection layer overlapped with the plurality of first finger-shaped electrode plates; each of the first finger-shaped electrode plates is connected to the second interconnection layer via a second conductive plug structure.

Optionally, the first interconnect layer and the second interconnect layer are located in the same layer or in different layers.

Optionally, when the first conductive plug structure is a plug strip, the first conductive plug structure extends along the first direction, and the length range of the first conductive plug structure in the first direction is greater than 20 nm; the width range of the first conductive plug structure in the second direction is greater than 10 nm, and the second direction is perpendicular to the first direction.

Optionally, when the first conductive plug structure is a plurality of first conductive plug units, the plurality of first conductive plug units are arranged along a first direction, and a distance between adjacent first conductive plug units in the first direction is greater than 100 nm.

Optionally, the distance between adjacent first finger-shaped electrode plates and second finger-shaped electrode plates ranges from 10 nm to 30 nm; the distance between the first finger-shaped electrode plate and the second electrode end ranges from 10 nm to 30 nm.

Optionally, a second dielectric layer is provided on the surface of the substrate, and the first interconnect layer and the second interconnect layer are located in the second dielectric layer.

Optionally, it further includes: a third dielectric layer located between the substrate and the first dielectric layer, the third dielectric layer is located on the surface of the second dielectric layer, and the first conductive plug structure and the second conductive plug structure are located in the third dielectric layer.

Correspondingly, the present invention also provides a method for forming a capacitor structure, comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a first electrode portion in the first dielectric layer, the first electrode portion comprising a plurality of first finger-shaped electrodes, the plurality of first finger-shaped electrodes being arranged in parallel along a first direction; a second electrode portion located in the first dielectric layer, the second electrode portion comprising a second electrode end and a plurality of second finger-shaped electrodes connected to the second electrode end, the second electrode end extending along a first direction, the plurality of second finger-shaped electrodes being arranged along the first direction, and each second finger-shaped electrode being located between two adjacent first finger-shaped electrodes.

Optionally, before forming the first electrode portion and the second electrode portion in the first dielectric layer, the method further includes: forming a mask structure on the first dielectric layer; and forming a sacrificial layer on the mask structure.

Optionally, after forming the sacrificial layer, it also includes: forming a plurality of first finger-shaped electrode plate grooves arranged parallel to the first direction in the sacrificial layer; forming side walls on the side wall surfaces of the first finger-shaped electrode plate grooves; etching the sacrificial layer using the side walls as a mask to form a second electrode end groove in the sacrificial layer, and a plurality of second finger-shaped electrode plate grooves respectively connected to the side walls of the second electrode end groove, and the ends of the plurality of first finger-shaped electrode plate grooves correspond to a side wall of the second electrode end groove.

Optionally, the method for forming the first electrode portion and the second electrode portion in the first dielectric layer includes: after etching the sacrificial layer using the side wall as a mask, etching the mask structure and the first dielectric layer using the sacrificial layer as a mask to form a plurality of first finger-shaped electrode target grooves, a second electrode end target groove, and a plurality of second finger-shaped electrode target grooves in the first dielectric layer; removing the sacrificial layer and the mask structure; forming the first electrode portion in the plurality of the first finger-shaped electrode target grooves, and forming the second electrode portion in the second electrode end target groove and the plurality of second finger-shaped electrode target grooves.

Optionally, before forming the first dielectric layer on the substrate, the method further includes forming a second dielectric layer on the substrate, and forming a first interconnect layer and a second interconnect layer in the second dielectric layer.

Optionally, after forming the first interconnect layer and the second interconnect layer and before forming the first dielectric layer, a third dielectric layer is formed on the surface of the second dielectric layer, the surface of the first interconnect layer and the surface of the second interconnect layer, and a first conductive plug structure and a second conductive plug structure are formed in the third dielectric layer, the first interconnect layer overlaps with the second electrode end, and the first conductive plug structure is located between the second electrode end and the first interconnect layer.

Optionally, the second interconnection layer is overlapped with a plurality of the first finger-shaped electrode plates, and each of the first finger-shaped electrode plates is connected to the second interconnection layer via the second conductive plug structure.

Optionally, the distance between adjacent first finger-shaped electrode plates and second finger-shaped electrode plates ranges from 10 nm to 30 nm, and the distance between the first finger-shaped electrode plates and the second electrode end ranges from 10 nm to 30 nm.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the method of the present invention, in addition to the capacitor between the first finger-shaped electrode plate and the second finger-shaped electrode plate, the capacitor structure can also form a capacitor between the first finger-shaped electrode plate and the second electrode terminal, so the capacitance density of the capacitor structure is improved, thereby improving the quality factor of the capacitor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of a capacitor structure;

2 to 13 are schematic structural diagrams of various steps of a method for forming a capacitor structure according to an embodiment of the present invention.

Detailed ways

As described in the background technology, there are still many problems with MOM capacitors in the prior art, which will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a capacitor structure.

Referring to FIG. 1 , a capacitor structure includes: a substrate (not shown); a first dielectric layer (not shown) located on the substrate; a first metal layer 100 and a second metal layer 103 located in the first dielectric layer; a second dielectric layer (not shown) located on the surface of the first dielectric layer, the first metal layer 100 and the second metal layer 103; a first conductive plug (not shown) and a second conductive plug (not shown) located in the second dielectric layer; a third dielectric layer (not shown) located on the surface of the second dielectric layer; a first electrode portion and a second electrode portion located in the third dielectric layer; The first electrode portion includes: a plurality of first finger-shaped pole plates 101, which are arranged in parallel along a first direction X, and a bottom surface of one end of the first finger-shaped pole plates 101 contacts a top surface of the first conductive plug; the second electrode portion includes: a plurality of second finger-shaped pole plates 104, which are arranged in parallel along the first direction X, a bottom surface of one end of the second finger-shaped pole plates 104 contacts a surface of the second conductive plug, and the plurality of first finger-shaped pole plates 101 and the plurality of second finger-shaped pole plates 104 are arranged crosswise.

In this embodiment, due to graphical limitations, the first finger-shaped electrode 101 and the second finger-shaped electrode 104 are usually along the same direction, so that the capacitance of the capacitor structure can only come from the capacitance formed between the adjacent first finger-shaped electrode 101 and the second finger-shaped electrode 104, which results in the capacitor structure having a limited capacitance density. Therefore, the storage density of the capacitor structure in this embodiment still needs to be improved.

On this basis, the present invention provides a capacitor structure and a method for forming the same. In addition to the capacitor formed between the first finger-shaped electrode plate and the second finger-shaped electrode plate, the capacitor structure can also form a capacitor between the first finger-shaped electrode plate and the second electrode terminal. Therefore, the capacitance density of the capacitor structure is improved, thereby improving the quality factor of the capacitor structure.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

2 to 13 are schematic structural diagrams of various steps of a method for forming a capacitor structure according to an embodiment of the present invention.

First, please refer to FIG. 2 , a substrate 200 is provided.

In this embodiment, the substrate 200 is made of silicon.

In other embodiments, the material of the substrate 200 may also be germanium, silicon germanium, silicon on insulator, germanium on insulator or silicon germanium on insulator.

Referring to FIG. 3 and FIG. 4 , a second dielectric layer 202 is formed on the substrate 200 , and a first interconnection layer 203 and a second interconnection layer 204 are formed in the second dielectric layer 202 .

Fig. 4 is a cross-sectional view taken along line A-A of Fig. 3 , and Fig. 3 is a top view of Fig. 4 .

In this embodiment, the first interconnect layer 203 and the second interconnect layer 204 are located in the same second dielectric layer 202 .

In other embodiments, the first interconnect layer 203 and the second interconnect layer 204 may also be located in different dielectric layers 202 .

In this embodiment, the materials of the first interconnection layer 203 and the second interconnection layer 204 are both metal.

The material of the second dielectric layer 202 includes: a low-K dielectric material; the low-K dielectric material includes: silicon oxide, silicon nitride or silicon oxynitride.

In this embodiment, the material of the second dielectric layer 202 is silicon oxide.

5 and 6 , a third dielectric layer 205 is formed on the surface of the second dielectric layer 202 , the surface of the first interconnect layer 203 , and the surface of the second interconnect layer 204 , and a first conductive plug structure 206 and a second conductive plug structure 207 are formed in the third dielectric layer 205 .

Figure 6 is a cross-sectional view of Figure 5 taken along line A-A, and Figure 5 is a top view of Figure 6.

In this embodiment, the method for forming the first conductive plug structure 206 includes: etching a portion of the third dielectric layer 205, forming through holes (not shown in the figure) arranged along the first direction (X) in the third dielectric layer 205, exposing a portion of the top surface of the first interconnection layer at the bottom of the through holes, and forming the first conductive plug structure 206 in the through holes. The first conductive plug structure 206 is in strip shape and contacts the first interconnection layer 203. This conductive plug strip structure greatly increases the contact area with the first interconnection layer 203, which helps to reduce the resistance of the formed capacitor structure and improve its electrical performance.

In this embodiment, the first conductive plug structure 206 is a strip structure.

In other embodiments, the first conductive plug structure 206 may also include a plurality of plug units, and the plurality of plug units are arranged in parallel along the second direction.

In this embodiment, the method for forming the second conductive plug structure 207 includes: etching a portion of the third dielectric layer 205, forming a plurality of through-hole units (not shown in the figure) arranged along the first direction (X) in the third dielectric layer 205, with a portion of the third dielectric layer 205 between adjacent through-hole units, and filling metal in each of the through-hole units to form the second conductive plug structure 207.

In other embodiments, the second conductive plug structure 207 may also adopt the structure of the first conductive plug structure 206 .

In this embodiment, a plurality of the second conductive plug structures 207 are arranged along the first direction (X), and a distance (a) between adjacent second conductive plug structures 207 in the first direction (X) is greater than 40 nm.

Referring to FIG. 7 and FIG. 8 , a first dielectric layer 201 is formed on the substrate 200 , a mask structure 208 is formed on the first dielectric layer 201 , and a sacrificial layer 209 is formed on the mask structure 208 .

Fig. 7 is a top view of Fig. 8, and Fig. 8 is a cross-sectional view of Fig. 7 taken along line A-A.

In this embodiment, the mask structure 208 may also adopt a single-layer structure.

In other embodiments, the mask structure 208 has a multi-layer structure.

The material of the sacrificial layer 209 includes one or more of titanium oxide and titanium nitride.

In this embodiment, the sacrificial layer 209 is made of titanium nitride.

Referring to FIG. 9 , a plurality of first finger-shaped electrode grooves 210 arranged in parallel along the first direction are formed in the sacrificial layer 209 .

The viewing direction of FIG. 9 is consistent with the viewing direction of FIG. 7 .

In this embodiment, the method for forming the first finger-shaped electrode groove 210 includes: forming a first patterned layer (not shown) on the sacrificial layer 209, the first patterned layer exposing a portion of the top surface of the sacrificial layer 209; etching the sacrificial layer 203 using the first patterned layer as a mask to form a plurality of the first finger-shaped electrode grooves 210 in the sacrificial layer 209.

In this embodiment, the bottom of the first finger plate groove 210 exposes the surface of the mask structure 208 .

Referring to FIG. 10 , a sidewall 211 is formed on the sidewall surface of the first finger-shaped electrode groove 210 .

In this embodiment, the method for forming the side wall 211 includes: forming a side wall material layer (not shown) on the side wall and bottom surface of the first finger-shaped electrode groove 210 and the top surface of the sacrificial layer 209; etching back the side wall material layer until the top surface of the sacrificial layer 209 and the bottom surface of the first finger-shaped electrode groove 210 are exposed to form the side wall 211.

The process for forming the sidewall material layer includes: atomic layer deposition process, chemical vapor deposition process or physical vapor deposition process.

In this embodiment, the spacer material layer is formed by an atomic layer deposition process.

In this embodiment, the material of the sidewall 211 is different from that of the sacrificial layer 209. The purpose is to reduce etching damage to the sidewall 211 in the subsequent process of etching the sacrificial layer 209 using the sidewall 211 as a mask to ensure the accuracy of the patterning process.

The material of the sidewall spacer 211 includes one or more of amorphous silicon, silicon oxide and silicon nitride.

In this embodiment, the material of the sidewall spacer 211 is silicon nitride.

Please refer to Figure 11. The sacrificial layer 209 is etched using the side wall 211 as a mask to form a second electrode end groove 212 and a plurality of second finger-shaped electrode plate grooves 213 respectively connected to the side walls of the second electrode end groove 212 in the sacrificial layer 209. The ends of the plurality of first finger-shaped electrode plate grooves 210 correspond to a side wall of the second electrode end groove 212.

The viewing direction of FIG. 11 is consistent with the viewing direction of FIG. 10 .

In this embodiment, the method for forming the second electrode terminal groove 212 includes: forming a second graphic layer (not shown in the figure) on the sacrificial layer 209, the second graphic layer exposing a portion of the top surface of the sacrificial layer 209; etching the sacrificial layer 209 using the side wall 211 and the second graphic layer as a mask to form the second electrode terminal groove 212.

In this embodiment, the process of etching the sacrificial layer 209 using the sidewall 211 and the second pattern layer as a mask adopts a wet etching process.

In this embodiment, in the process of etching the sacrificial layer 209 using the side wall 211 and the second graphic layer as a mask, the second finger-shaped electrode groove 213 is formed in the sacrificial layer 209 between the adjacent side walls 211 after etching, and the second finger-shaped electrode groove 213 is connected to the side wall of the second electrode end groove 212.

Please refer to Figure 12. After the sacrificial layer 209 is etched using the side wall 211 as a mask, the mask structure 208 and the first dielectric layer 201 are etched using the sacrificial layer 209 and the side wall 211 as masks to form a plurality of first finger-shaped electrode target grooves 214, a second electrode end target groove 215, and a plurality of second finger-shaped electrode target grooves 216 in the first dielectric layer 201.

The viewing direction of FIG. 12 is consistent with the viewing direction of FIG. 11 .

In this embodiment, the process of etching the mask structure 208 and the first dielectric layer 201 using the sacrificial layer 209 as a mask adopts a wet etching process.

In other embodiments, the process of etching the mask structure 208 and the first dielectric layer 201 using the sacrificial layer 209 as a mask may also be a dry etching process.

Please continue to refer to FIG. 12 . In this embodiment, after etching the mask structure 208 and the first dielectric layer 201 , the process further includes: removing the sacrificial layer 209 and the mask structure 208 .

Please refer to FIG. 13 , the first electrode portion 217 is formed in a plurality of the first finger-shaped electrode target grooves 214 , and the second electrode portion 218 is formed in the second electrode end target groove 215 and a plurality of the second finger-shaped electrode target grooves 215 .

The viewing direction of FIG. 13 is consistent with the viewing direction of FIG. 12 .

In this embodiment, the first electrode portion 217 includes a plurality of first finger-shaped electrode plates 217 a , and the plurality of first finger-shaped electrode plates 217 a are arranged in parallel along a first direction (X).

In this embodiment, the second electrode portion 218 includes a second electrode end 218a and a plurality of second finger-shaped electrode plates 218b connected to the second electrode end 218a, the second electrode end 218a extends along a first direction (X), the plurality of second finger-shaped electrode plates 218b are arranged along the first direction (X), and each of the second finger-shaped electrode plates 218b is located between two adjacent first finger-shaped electrode plates 217a.

In this embodiment, the first interconnection layer 203 overlaps with the second electrode terminal 218 b , and the first conductive plug structure 206 is located between the second electrode terminal 218 a and the first interconnection layer 203 .

In this embodiment, a plurality of the first finger-shaped electrode plates 217 a are overlapped with the second interconnection layer 204 , and each of the first finger-shaped electrode plates 217 a is connected to the second interconnection layer 204 through the second conductive plug structure 207 .

In this embodiment, in addition to the capacitor formed between the first finger-shaped electrode 217a and the second finger-shaped electrode 218b, the capacitor structure can also form a capacitor between the first finger-shaped electrode 217a and the second electrode end 218a, so the capacitance density of the capacitor structure is improved, thereby improving the quality factor of the capacitor structure.

In this embodiment, the distance between the adjacent first finger-shaped electrode plates 217a and the second finger-shaped electrode plates 218b ranges from 10 nm to 30 nm; the distance between the first finger-shaped electrode plates 217a and the second electrode end 218a ranges from 10 nm to 30 nm.

Please refer to Figures 5 and 13. In this embodiment, when the first conductive plug structure 206 is a plug strip, the first conductive plug structure 206 extends along the first direction (X), and the length (m) of the first conductive plug structure 206 in the first direction (X) is greater than 20nm and less than the maximum distance (M) between the first finger-shaped plates 217a at the edge along the first direction; the width (n) of the first conductive plug structure 206 in the second direction (Y) is greater than 10nm and less than the width of the second electrode end 218a in the second direction (Y), and the second direction is perpendicular to the first direction.

In other embodiments, when the first conductive plug structure 206 is a plurality of first conductive plug units, the plurality of first conductive plug units are arranged along a first direction (X), and a distance between adjacent first conductive plug units in the first direction (X) is greater than 100 nm.

Correspondingly, the present invention also provides a capacitor structure, please refer to Figures 1 to 13, including a substrate 200; a first dielectric layer 201 located on the substrate 200; a first electrode portion 217 located in the first dielectric layer 201, the first electrode portion 217 includes a plurality of first finger-shaped pole plates 217a, and the plurality of first finger-shaped pole plates 217a are arranged in parallel along a first direction (X); a second electrode portion 218 located in the first dielectric layer 201, the second electrode portion 218 includes a second electrode end 218a and a plurality of second finger-shaped pole plates 218b connected to the second electrode end 218a, the second electrode end 218a extends along the first direction, the plurality of second finger-shaped pole plates 218b are arranged along the first direction (X), and each second finger-shaped pole plate 218b is located between two adjacent first finger-shaped pole plates 217a.

In this embodiment, in addition to the capacitor formed between the first finger-shaped electrode 217a and the second finger-shaped electrode 218b, the capacitor structure can also form a capacitor between the first finger-shaped electrode 217a and the second electrode end 218a, so the capacitance density of the capacitor structure is improved, thereby improving the quality factor of the capacitor structure.

In this embodiment, the present invention further includes: a first interconnection layer 203 overlapping the second electrode terminal 218 a ; and a first conductive plug structure 206 located between the second electrode terminal 218 a and the first interconnection layer 203 .

In this embodiment, the first conductive plug structure 206 is a strip structure.

In other embodiments, the first conductive plug structure 206 may also include a plurality of plug units, and the plurality of plug units are arranged in parallel along the second direction.

In this embodiment, the distance between the adjacent first finger-shaped electrode plates 217a and the second finger-shaped electrode plates 218b ranges from 10 nm to 30 nm; the distance between the first finger-shaped electrode plates 217a and the second electrode end 218a ranges from 10 nm to 30 nm.

In the present embodiment, when the first conductive plug structure 206 is a plug strip, the first conductive plug structure 206 extends along the first direction (X), and the length (m) of the first conductive plug structure 206 in the first direction (X) is greater than 20 nm and less than the maximum distance (M) between the first finger-shaped plates 217a at two edges along the first direction; the width (n) of the first conductive plug structure 206 in the second direction (Y) is greater than 10 nm and less than the width of the second electrode end 218a in the second direction (Y), and the second direction is perpendicular to the first direction.

In other embodiments, when the first conductive plug structure 206 is a plurality of first conductive plug units, the plurality of first conductive plug units are arranged along a first direction (X), and a distance between adjacent first conductive plug units in the first direction (X) is greater than 100 nm.

In this embodiment, the present invention further includes: a second interconnection layer 204 overlapping with the plurality of first finger-shaped electrode plates 217 a ; and each of the first finger-shaped electrode plates 217 a is connected to the second interconnection layer 204 via a second conductive plug structure 207 .

In other embodiments, the second conductive plug structure 207 may also adopt the structure of the first conductive plug structure 206 .

In this embodiment, a plurality of the second conductive plug structures 207 are arranged along the first direction (X), and a distance between adjacent second conductive plug structures 207 in the first direction (X) is greater than 40 nm.

In this embodiment, the surface of the substrate 200 has a second dielectric layer 202 , and the first interconnect layer 203 and the second interconnect layer 203 are located in the second dielectric layer 202 .

In this embodiment, the first interconnect layer 203 and the second interconnect layer 204 are located in the same layer.

In other embodiments, the first interconnect layer 203 and the second interconnect layer 204 may also be located in different layers.

In this embodiment, it also includes: a third dielectric layer 205 located between the substrate 200 and the first dielectric layer 201 , the third dielectric layer 205 is located on the surface of the second dielectric layer 202 , and the first conductive plug structure 206 and the second conductive plug structure 207 are located in the third dielectric layer 205 .

In this embodiment, the distance between the adjacent first finger-shaped electrode plates 217a and the second finger-shaped electrode plates 218b ranges from 10 nm to 30 nm; the distance between the first finger-shaped electrode plates 217a and the second electrode end 218a ranges from 10 nm to 30 nm.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (17)

1. A capacitor structure, comprising:

A substrate;

A first dielectric layer on the substrate;

The first electrode part is positioned in the first dielectric layer and comprises a plurality of first finger-shaped polar plates which are arranged in parallel along a first direction;

The second electrode part comprises a second electrode end and a plurality of second finger-shaped polar plates connected with the second electrode end, the second electrode end extends along a first direction, the plurality of second finger-shaped polar plates are arranged along the first direction, and each second finger-shaped polar plate is positioned between two adjacent first finger-shaped polar plates.

2. The capacitor structure of claim 1, further comprising: a first interconnect layer overlapping the second electrode terminal; a first conductive plug structure located between the second electrode terminal and the first interconnect layer.

3. The capacitor structure of claim 2, further comprising: the second interconnection layers are overlapped with the plurality of first finger-shaped polar plates; each first finger electrode plate is connected with the second interconnection layer through a second conductive plug structure.

4. The capacitor structure of claim 3, characterized in that the first interconnect layer is located on the same layer or on a different layer than the second interconnect layer.

5. The capacitor structure of claim 2, wherein the first conductive plug structure extends along the first direction when the first conductive plug structure is a plug strip, the first conductive plug structure has a length in the first direction that is greater than 20nm and a width in a second direction that is perpendicular to the first direction that is greater than 10 nm.

6. The capacitor structure of claim 2, wherein when the first conductive plug structure is a plurality of first conductive plug units, the plurality of first conductive plug units are arranged along a first direction, and a distance between adjacent first conductive plug units in the first direction is greater than 100nm.

7. The capacitor structure of claim 1, characterized in that the spacing between adjacent first finger plates and second finger plates ranges from 10nm to 30nm; the distance between the first finger plate and the second electrode end ranges from 10nm to 30nm.

8. The capacitor structure of claim 3, in which the substrate surface has a second dielectric layer, the first interconnect layer and the second interconnect layer being located within the second dielectric layer.

9. The capacitor structure of claim 8, further comprising: and the third dielectric layer is positioned between the substrate and the first dielectric layer, the third dielectric layer is positioned on the surface of the second dielectric layer, and the first conductive plug structure and the second conductive plug structure are positioned in the third dielectric layer.

10. A method of forming a capacitor structure, comprising:

Providing a substrate;

Forming a first dielectric layer on the substrate;

Forming a first electrode part in the first dielectric layer, wherein the first electrode part comprises a plurality of first finger-shaped polar plates which are arranged in parallel along a first direction;

The second electrode part comprises a second electrode end and a plurality of second finger-shaped polar plates connected with the second electrode end, the second electrode end extends along a first direction, the plurality of second finger-shaped polar plates are arranged along the first direction, and each second finger-shaped polar plate is positioned between two adjacent first finger-shaped polar plates.

11. The method of forming a capacitor structure of claim 10, further comprising, prior to forming a first electrode portion and a second electrode portion within the first dielectric layer: forming a mask structure on the first dielectric layer; a sacrificial layer is formed over the mask structure.

12. The method of forming a capacitor structure of claim 11, further comprising, after forming the sacrificial layer: forming a plurality of first finger-shaped polar plate grooves which are arranged in parallel along the first direction in the sacrificial layer; forming a side wall on the side wall surface of the first finger-shaped polar plate groove; and etching the sacrificial layer by taking the side wall as a mask, forming a second electrode end groove and a plurality of second finger-shaped polar plate grooves which are respectively communicated with the side wall of the second electrode end groove in the sacrificial layer, wherein the end parts of the plurality of first finger-shaped polar plate grooves correspond to one side wall of the second electrode end groove.

13. The method of forming a capacitor structure of claim 12, wherein the method of forming a first electrode portion and a second electrode portion within the first dielectric layer comprises: etching the sacrificial layer by taking the side wall as a mask, and then etching the mask structure and the first dielectric layer by taking the sacrificial layer as a mask, wherein a plurality of first finger-shaped polar plate target grooves, second electrode end target grooves and a plurality of second finger-shaped polar plate target grooves are formed in the first dielectric layer; removing the sacrificial layer and the mask structure; and forming the first electrode part in the first electrode terminal target grooves and forming the second electrode part in the second electrode terminal target grooves and the second electrode terminal target grooves.

14. The method of forming a capacitor structure of claim 10, further comprising forming a second dielectric layer on the substrate prior to forming the first dielectric layer on the substrate, forming a first interconnect layer and a second interconnect layer within the second dielectric layer.

15. The method of forming a capacitor structure of claim 14, further comprising forming a third dielectric layer on a surface of the second dielectric layer, a surface of the first interconnect layer, and a surface of the second interconnect layer after forming the first interconnect layer and the second interconnect layer, forming a first conductive plug structure and a second conductive plug structure in the third dielectric layer, the first interconnect layer overlapping the second electrode terminal, the first conductive plug structure being located between the second electrode terminal and the first interconnect layer.

16. The method of forming a capacitor structure of claim 15 wherein said second interconnect layer is disposed overlying a plurality of said first finger plates, each of said first finger plates being connected to said second interconnect layer by a respective one of said second conductive plug structures.

17. The method of forming a capacitor structure of claim 10, wherein a spacing between adjacent ones of the first finger plates and the second finger plates ranges from 10nm to 30nm, and a spacing between the first finger plates and the second electrode tip ranges from 10nm to 30nm.