CN113053798A - Ultrathin crystal thinning and cutting process utilizing tempered glass - Google Patents
Ultrathin crystal thinning and cutting process utilizing tempered glass Download PDFInfo
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- CN113053798A CN113053798A CN202110339399.6A CN202110339399A CN113053798A CN 113053798 A CN113053798 A CN 113053798A CN 202110339399 A CN202110339399 A CN 202110339399A CN 113053798 A CN113053798 A CN 113053798A
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- 238000005520 cutting process Methods 0.000 title claims abstract description 21
- 239000013078 crystal Substances 0.000 title claims abstract description 16
- 239000005341 toughened glass Substances 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 58
- 230000008569 process Effects 0.000 claims abstract description 58
- 239000011521 glass Substances 0.000 claims abstract description 28
- 239000012790 adhesive layer Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 4
- 239000005368 silicate glass Substances 0.000 claims description 4
- 239000006058 strengthened glass Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 abstract description 56
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000012858 packaging process Methods 0.000 abstract 1
- 229920006254 polymer film Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
本发明公开一种利用强化玻璃的超薄晶减薄切割工艺，包括以下步骤：S1、完成晶圆正面制程；S2、将晶圆正面暂时键合玻璃载板；S3、通过研磨蚀刻的方式对晶圆背面减薄，然后完成晶圆背面制程；S4、将晶圆背面键合超薄玻璃载板；S5、解键合除去晶圆正面的玻璃载板，清洗除去黏着层，然后完成对晶圆切割。本发明采用两次键合及解键合的技术晶圆超薄晶圆加工，第二次键合用强化过的超薄玻璃载板取代传统的切割模框以确保晶粒可在有强度及柔性的玻璃载板上进行封装的加工制程，可确保超薄晶圆或晶粒不会产生碎裂的现象。
The invention discloses an ultra-thin crystal thinning and cutting process using tempered glass, which includes the following steps: S1, completing the front side manufacturing process of the wafer; S2, temporarily bonding the front side of the wafer to a glass carrier; S3, aligning the wafer by grinding and etching The backside of the wafer is thinned, and then the backside process of the wafer is completed; S4, the backside of the wafer is bonded to an ultra-thin glass carrier; S5, the glass carrier on the front side of the wafer is removed by debonding, and the adhesive layer is cleaned and removed, and then the wafer is cut. . The present invention adopts two bonding and debonding technologies to process wafer ultra-thin wafers, and the second bonding replaces the traditional cutting mold frame with a strengthened ultra-thin glass carrier to ensure that the chips can be processed in glass with strength and flexibility. The packaging process on the carrier board ensures that ultra-thin wafers or dies are not chipped.
Description
Technical Field
The invention relates to the field of wafer processing, in particular to an ultrathin crystal thinning and cutting process by using tempered glass.
Background
In daily life, the progress of semiconductor technology is largely reflected in the reduction of feature size, and as the feature size is reduced, the number of transistor circuits per unit area is increased, and the functions are enhanced accordingly. However, while the integration density is greatly improved, the heat source starts to form a concentrated phenomenon on the chip, and how to reduce the thermal resistance of the device and perform heat dissipation and cooling of the device becomes a key problem. In fact, one of the solutions to heat dissipation of components is grinding thinning.
The thickness of the active area of the devices and connecting circuits on the wafer is typically 5 to 10 μm, and in order to ensure their functionality, a certain support thickness is required, which has a limit of 20 to 30 μm for the thickness of the wafer. But this thickness actually occupies only a small portion of the entire wafer thickness, and the remaining thickness of the substrate is only sufficient to ensure that the silicon wafer has sufficient strength during fabrication, testing, packaging, and shipping. After the integrated circuit on the wafer is manufactured, the back of the silicon wafer needs to be thinned to reach the required thickness.
In the prior art, a bonded glass carrier plate is usually used for thinning the back of a wafer, and after the back process is finished, the ultra-thin wafer is attached to a soft polymer film for debonding and cutting the wafer. During wafer dicing, although the periphery of the polymer film is fixed by metal, the polymer film has weak stress, so when the wafer is as thin as less than 30um (8 inch and 12 inch wafers), the glass carrier is debonded, or the adhesive layer is removed, the wafer is very easy to crack.
Disclosure of Invention
In order to solve the above-mentioned drawbacks of the background art, the present invention provides a process for thinning and cutting an ultra-thin crystal by using a strengthened glass, wherein the chemically strengthened ultra-thin glass is used for secondary bonding to replace a conventional polymer film cutting mold frame, so that the wafer can be effectively prevented from being cracked after the glass carrier is debonded and bonded.
The purpose of the invention can be realized by the following technical scheme:
an ultrathin crystal thinning and cutting process utilizing tempered glass comprises the following steps:
s1, completing the front process of the wafer;
s2, bonding the glass carrier plate on the front surface of the wafer temporarily;
s3, thinning the back of the wafer by grinding and etching, and then finishing the back process of the wafer;
s4, bonding the ultrathin glass carrier plate on the back of the wafer;
and S5, debonding and removing the glass carrier plate on the front surface of the wafer, cleaning and removing the adhesive layer, and then finishing the cutting of the wafer.
Further preferably, the front surface process of the wafer includes a photolithography process, an ILD process, an ion implantation process, a metal process and an etching process.
Further preferably, the glass carrier plate in the step S2 is a normal silicate glass plate with a thickness of 400-800 μm, and the adhesive layer of the bonded glass plate in the step S2 has a thickness of more than 30 μm.
Further preferably, the wafer back side process includes a photolithography process, an ion implantation process, and a metal process.
Further preferably, the ultra-thin glass carrier plate in step S4 is a high alumina silica glass plate with a thickness of less than 100 μm, and the adhesive layer bonding the ultra-thin glass carrier plate in step S4 has a thickness of less than 30 μm.
The invention has the beneficial effects that:
the invention adopts the technology of twice bonding and debonding to process the wafer ultrathin wafer, and the strengthened ultrathin glass carrier plate is used for replacing the traditional cutting die frame for the second bonding so as to ensure that the crystal grains can be packaged on the glass carrier plate with strength and flexibility, thereby ensuring that the ultrathin wafer (crystal grains) can not generate the phenomenon of cracking.
Drawings
The invention will be further described with reference to the accompanying drawings.
FIG. 1 is a schematic view of the process of step S1 according to the present invention;
FIG. 2 is a schematic view of the process of step S2 according to the present invention;
FIG. 3 is a schematic view of the process of step S3 according to the present invention;
FIG. 4 is a schematic view of the process of step S4 according to the present invention;
fig. 5 is a schematic view of the process of step S5 according to the present invention.
In the figure:
1-wafer, 2-glass carrier plate, 3-ultrathin glass carrier plate and 4-crystal grain.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "opening," "upper," "lower," "thickness," "top," "middle," "length," "inner," "peripheral," and the like are used in an orientation or positional relationship that is merely for convenience in describing and simplifying the description, and do not indicate or imply that the referenced component or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present invention.
Example 1
An ultrathin crystal thinning and cutting process utilizing tempered glass comprises the following steps:
s1, completing the front process of the wafer;
s2, temporarily bonding a common silicate glass plate with the thickness of 500 mu m on the front surface of the wafer through an adhesive layer with the thickness of 60 mu m;
s3, thinning the back of the wafer by grinding and etching, and then finishing the back process of the wafer;
s4, bonding a high-alumina-silica glass plate with the thickness of 100 mu m on the back surface of the wafer through an adhesive layer with the thickness of 20 mu m;
and S5, debonding and removing the glass carrier plate on the front surface of the wafer, cleaning and removing the adhesive layer, and then finishing the cutting of the wafer.
The front side process of the wafer includes a photolithography process, an ILD process, an ion implantation process, a metal process, and an etching process.
The wafer backside process includes a photolithography process, an ion implantation process, and a metal process.
Example 2
An ultrathin crystal thinning and cutting process utilizing tempered glass comprises the following steps:
s1, completing the front process of the wafer;
s2, temporarily bonding a common silicate glass plate with the thickness of 600 mu m on the front surface of the wafer through an adhesive layer with the thickness of 50 mu m;
s3, thinning the back of the wafer by grinding and etching, and then finishing the back process of the wafer;
s4, bonding a high-alumina-silica glass plate with the thickness of 50 mu m on the back surface of the wafer through an adhesive layer with the thickness of 20 mu m;
and S5, debonding and removing the glass carrier plate on the front surface of the wafer, cleaning and removing the adhesive layer, and then finishing the cutting of the wafer.
The front side process of the wafer includes a photolithography process, an ILD process, an ion implantation process, a metal process, and an etching process.
The wafer backside process includes a photolithography process, an ion implantation process, and a metal process.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (5)
1. An ultrathin crystal thinning and cutting process utilizing tempered glass is characterized by comprising the following steps of:
s1, completing the front process of the wafer;
s2, bonding the glass carrier plate on the front surface of the wafer temporarily;
s3, thinning the back of the wafer by grinding and etching, and then finishing the back process of the wafer;
s4, bonding the ultrathin glass carrier plate on the back of the wafer;
and S5, debonding and removing the glass carrier plate on the front surface of the wafer, cleaning and removing the adhesive layer, and then finishing the cutting of the wafer.
2. The ultra-thin crystal thinning and cutting process using tempered glass as claimed in claim 1, wherein the front side process of the wafer comprises a photolithography process, an ILD process, an ion implantation process, a metal process and an etching process.
3. The ultra-thin crystal thinning and cutting process using strengthened glass as claimed in claim 1, wherein the glass carrier plate in step S2 is a normal silicate glass plate with thickness of 400-800 μm, and the bonding layer of step S2 is thicker than 30 μm.
4. The ultra-thin crystal thinning and cutting process using tempered glass as claimed in claim 1, wherein the wafer backside process comprises a photolithography process, an ion implantation process and a metal process.
5. The ultra-thin crystal thinning and cutting process using strengthened glass as claimed in claim 1, wherein the ultra-thin glass carrier plate in step S4 is a high alumina silica glass plate with a thickness of less than 100 μm, and the thickness of the adhesive layer bonding the ultra-thin glass carrier plate in step S4 is less than 30 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110339399.6A CN113053798A (en) | 2021-03-30 | 2021-03-30 | Ultrathin crystal thinning and cutting process utilizing tempered glass |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110339399.6A CN113053798A (en) | 2021-03-30 | 2021-03-30 | Ultrathin crystal thinning and cutting process utilizing tempered glass |
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| CN113053798A true CN113053798A (en) | 2021-06-29 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725160A (en) * | 2021-09-01 | 2021-11-30 | 浙江同芯祺科技有限公司 | Ultrathin wafer front cutting process |
| CN114242581A (en) * | 2021-12-24 | 2022-03-25 | 滁州钰顺企业管理咨询合伙企业(有限合伙) | Method for polishing back of ground wafer |
| CN114464529A (en) * | 2022-01-10 | 2022-05-10 | 绍兴同芯成集成电路有限公司 | A kind of preparation method of semiconductor device |
| CN115958308A (en) * | 2022-08-29 | 2023-04-14 | 中晟鲲鹏光电半导体有限公司 | Silicon carbide wafer slicing process |
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| WO2004009480A1 (en) * | 2002-07-17 | 2004-01-29 | Osram Opto Semiconductors Gmbh | Shatterproof ultra-thin glass and the handling thereof |
| CN111441072A (en) * | 2020-03-27 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Method for producing crystal grains by cutting crystal grains first and then electroplating on two sides |
| JP2020128339A (en) * | 2020-05-21 | 2020-08-27 | ショット グラス テクノロジーズ （スゾウ） カンパニー リミテッドＳｃｈｏｔｔ Ｇｌａｓｓ Ｔｅｃｈｎｏｌｏｇｉｅｓ （Ｓｕｚｈｏｕ） Ｃｏ．， Ｌｔｄ． | Low-cte boroaluminosilicate glass for glass carrier wafers |
| CN112259495A (en) * | 2020-10-22 | 2021-01-22 | 绍兴同芯成集成电路有限公司 | Wafer printing process |
-
2021
- 2021-03-30 CN CN202110339399.6A patent/CN113053798A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004009480A1 (en) * | 2002-07-17 | 2004-01-29 | Osram Opto Semiconductors Gmbh | Shatterproof ultra-thin glass and the handling thereof |
| CN111441072A (en) * | 2020-03-27 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Method for producing crystal grains by cutting crystal grains first and then electroplating on two sides |
| JP2020128339A (en) * | 2020-05-21 | 2020-08-27 | ショット グラス テクノロジーズ （スゾウ） カンパニー リミテッドＳｃｈｏｔｔ Ｇｌａｓｓ Ｔｅｃｈｎｏｌｏｇｉｅｓ （Ｓｕｚｈｏｕ） Ｃｏ．， Ｌｔｄ． | Low-cte boroaluminosilicate glass for glass carrier wafers |
| CN112259495A (en) * | 2020-10-22 | 2021-01-22 | 绍兴同芯成集成电路有限公司 | Wafer printing process |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725160A (en) * | 2021-09-01 | 2021-11-30 | 浙江同芯祺科技有限公司 | Ultrathin wafer front cutting process |
| CN113725160B (en) * | 2021-09-01 | 2024-06-28 | 浙江同芯祺科技有限公司 | Front cutting process of ultrathin wafer |
| CN114242581A (en) * | 2021-12-24 | 2022-03-25 | 滁州钰顺企业管理咨询合伙企业(有限合伙) | Method for polishing back of ground wafer |
| CN114464529A (en) * | 2022-01-10 | 2022-05-10 | 绍兴同芯成集成电路有限公司 | A kind of preparation method of semiconductor device |
| CN115958308A (en) * | 2022-08-29 | 2023-04-14 | 中晟鲲鹏光电半导体有限公司 | Silicon carbide wafer slicing process |
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Application publication date: 20210629 |