CN113032791A - IP core, IP core management method and chip - Google Patents
IP core, IP core management method and chip Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/575—Secure boot
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
- G06F21/101—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM] by binding digital rights to specific entities
- G06F21/1015—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM] by binding digital rights to specific entities to users
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
- G06F21/107—License processing; Key processing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
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Abstract
The IP core, the management method of the IP core and the chip provided by the invention receive the key input from the outside; further judging whether the secret key is correct, if so, processing the received data to be processed, and outputting a correct processing result; and if the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result according to a preset probability. Therefore, the complete function of the IP core can be used only when the correct key is obtained, the IP core is prevented from being abused, and intellectual property rights of products such as the IP core and the like are protected.
Description
Technical Field
The invention relates to the field of chip design, in particular to an IP core, a management method of the IP core and a chip.
Background
At present, the design scale of chips is increasingly huge, and for chip development, chip companies are difficult to finish all design works independently. Often, chip companies reduce the complexity of the design by purchasing third-party hardware IP cores, focusing limited resources on the development of the critical modules of the integrated design core. The form of the hardware IP core may be various, including software code (hardware description language), netlist, or layout (GDS). For a hardware IP core, especially for a front-end digital IP, the method has the characteristic of strong applicability, namely, the method can be quickly adapted to other chip items, which causes the problem that the IP of a hardware IP core manufacturer is easily used on unauthorized chip products, and the intellectual property right is infringed.
Disclosure of Invention
The invention provides an IP core, a management method of the IP core and a chip, and aims to protect intellectual property of the IP core.
An embodiment provides a management method of an IP core, including:
receiving an externally input key;
judging whether the secret key is correct or not, if so, processing the received data to be processed, and outputting a correct processing result; and if the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result according to a preset probability.
In the management method, the processing the received data to be processed and outputting an erroneous processing result with a preset probability includes:
judging whether the received data to be processed belongs to preset special data or not, if so, processing the data to be processed, and outputting an error processing result; otherwise, processing the data to be processed and outputting a correct processing result; the occupation ratio of the special data in all possible data to be processed is the preset probability.
In the management method, the preset probability is not more than 1%.
In the management method, the determining whether the key is correct includes:
judging whether the secret key belongs to a preset secret key set or not, if so, determining that the secret key is correct, and otherwise, determining that the secret key is incorrect; the set of keys includes a plurality of correct keys.
An embodiment provides an IP core comprising:
the key verification module is used for receiving an externally input key and judging whether the key is correct or not;
the data processing module is used for processing the received data to be processed when the secret key is correct and outputting a correct processing result; and when the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result according to a preset probability.
In the IP core, the data processing module processes the received data to be processed, and outputs an erroneous processing result with a preset probability, including:
judging whether the received data to be processed belongs to preset special data or not, if so, processing the data to be processed, and outputting an error processing result; otherwise, processing the data to be processed and outputting a correct processing result; the occupation ratio of the special data in all possible data to be processed is the preset probability.
In the IP core, the preset probability is not more than 1%.
In the IP core, the determining, by the key verification module, whether the key is correct includes:
judging whether the secret key belongs to a preset secret key set or not, if so, determining that the secret key is correct, and otherwise, determining that the secret key is incorrect; the set of keys includes a plurality of correct keys.
An embodiment provides a chip, wherein part of circuits of the chip are manufactured according to the IP core.
An embodiment provides a computer readable storage medium having a program stored thereon, the program being executable by a processor to implement a method as described above.
According to the IP core, the management method of the IP core and the chip of the embodiment, the key input from the outside is received; further judging whether the secret key is correct, if so, processing the received data to be processed, and outputting a correct processing result; and if the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result according to a preset probability. Therefore, the complete function of the IP core can be used only when the correct key is obtained, the IP core is prevented from being abused, and intellectual property rights of products such as the IP core and the like are protected.
Drawings
FIG. 1 is a block diagram of an embodiment of an IP core provided in the present invention;
FIG. 2 is a flowchart of an embodiment of a method for managing an IP core according to the present invention;
FIG. 3 is a flowchart of an embodiment of a method for managing an IP core according to the present invention;
fig. 4 is a block diagram of an IP core circuit in the chip provided by the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
As shown in fig. 1, the IP core provided by the present invention includes a key verification module 10 and a data processing module 20. The IP core is an intellectual property core or an intellectual property module. The IP core is mainly divided into a soft IP (core), a fixed IP (core), and a hard IP (core). The soft IP may be, for example, a functional block (software code) described in a hardware description language. The hard IP may be, for example, a layout (GDS) by which a mask for producing a chip is fabricated. The fixed IP is an intermediate form of the soft IP and the hard IP, such as a netlist.
The key verification module 10 is configured to receive an externally input key and determine whether the key is correct; the judgment result is output to the data processing module 20. For soft IP cores, the key verification module 10 may be a functional module. For a hard IP core, the key verification module 10 may be a digital logic circuit. For a fixed IP core, key verification module 10 may be a netlist that reflects the digital logic circuit.
The data processing module 20 is configured to process the received data to be processed when the secret key is correct, and output a correct processing result; and when the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result according to a preset probability. Therefore, the complete function of the IP core can be used only when the correct key is obtained, the IP core is prevented from being abused, and intellectual property rights of products such as the IP core and the like are protected. Moreover, the invention can output correct processing results with a certain probability when the key is wrong, so that if other people want to crack the key, correct data processing results can still be obtained after cracking fails, the key is easy to be mistaken into cracked, and finally, the abuse of the IP core once is avoided. Even if other people know that the processing result output by the IP core has a certain probability of error when the secret key is incorrect, when other people want to crack the secret key, whether the cracking is successful or not, the accuracy of the data processing result needs to be repeatedly verified, the cracking cost is high, the condition that the IP core is abused is effectively reduced, and the intellectual property of the IP core is protected. Likewise, for a soft IP core, the data processing module 20 may be a functional module. For a hard IP core, the data processing block 20 may be a digital logic circuit. For a fixed IP core, data processing block 20 may be a netlist that reflects the digital logic circuit.
As shown in fig. 2, the process of data processing by the IP core includes the following steps:
And 3, processing the received data to be processed by the data processing module 20, and outputting an error processing result according to a preset probability. In some embodiments, the predetermined probability is not more than 1%, preferably, the predetermined probability is not more than 0.3%, not more than 0.1%, or between 0.1% and 0.3%. Chips on the market are usually designed and verified at an early stage, and then are produced in mass production to form final products. The chip vendor typically evaluates the IP cores of at least one IP vendor during the chip design phase. If the IP core is encrypted by simply adopting the key, IP manufacturers need to provide the IP cores using different keys for each chip manufacturer for the same IP core, and the maintenance and management cost of the IP core is high. In addition, although the chip is designed and even verified, the chip is not always mass-produced for various reasons, which easily causes the key provided by the IP manufacturer in the early stage to be abused (stolen), is not beneficial to the protection of the IP core, and brings loss to the hardware IP core manufacturer. At present, hardware IP core manufacturers often judge whether abuse is caused by embedding a serial number in an IP product. However, since the function of the IP core is not affected by tampering the serial number, the method cannot fundamentally solve the misuse situation, and is only a method for obtaining evidence and proving. Even if the key is wrong, the data processing module 20 can correctly process more than 99% of data, so that when a chip manufacturer designs and verifies the chip, the IP manufacturer does not need to provide the key, the security of the key is improved, a public edition of the IP core can be issued to be evaluated by a plurality of chip manufacturers, and the maintenance cost of the IP core is reduced; in addition, the accuracy of more than 99 percent can also meet the requirements of chip manufacturers for designing and verifying chips. When the chip enters a mass production stage or a product stage, the IP manufacturer provides the key to the chip manufacturer, and the chip manufacturer writes the key into a starting process of the SoC, so that the IP core is prevented from being abused. The present embodiment is described by taking the preset probability of 0.3% as an example.
Specifically, the data processing module 20 includes a judging unit 210, a correct processing unit 220, and an error processing unit 230. As shown in fig. 3, this step may include:
step 3.1, the determining unit 210 determines whether the received data to be processed belongs to the preset special data, if so, step 3.2 is performed, otherwise, step 4 is performed. The occupation ratio of the special data in all possible data to be processed is the preset probability. For example, the data to be processed is n bits of binary data, n is an integer greater than 0, the determining unit 210 determines whether the k preset designated bits are preset values, if yes, it is determined that the data to be processed belongs to the preset special data, otherwise, it is determined that the data to be processed does not belong to the preset special data. k is an integer greater than 0 and less than n,
i.e. the preset probability.
And 3.2, performing second processing on the data to be processed by the error processing unit 230, and outputting an error processing result. The second process is performed in various ways, and only the wrong result needs to be output, and the number of binary bits of the wrong result can be the same as that of the data to be processed, namely n bits.
And 4, performing first processing on the received to-be-processed data by the correct processing unit 220, and outputting a correct processing result. The correct processing unit 220 performs the main or core function of the IP core, for example, if the IP core is an IP core with an addition carry, the normal processing unit 220 is used to calculate the sum of a plurality of input values, and the error processing unit 230 ignores the carry between bits and performs an addition operation without a carry.
The function of the key may be used to start the correct processing unit 220, or to run the correct processing unit 220, in other words, after inputting the correct key once, the subsequently received data to be processed is processed by the correct processing unit 220, that is, only the correct key needs to be input once; the key and the data to be processed may also be input to the IP core, and after the key is determined to be correct, the correct processing unit 220 processes the data to be processed that is input together, that is, the key needs to be input once each time the data to be processed is processed.
Specifically, the operation logic of the IP core (the key verification module 10 and the data processing module 20) may be a mapping function, and in this embodiment, the mapping function is designed based on a cryptographic algorithm and implemented by using hardware codes. The mapping function has two inputs, namely a data input to be processed and a key input; there is a data output of the same length as the data input to be processed. Under the condition that the key is correct, the input data to be processed can be output through correct calculation. In the case of an incorrect key, the output result may be made incorrect when the input is some special value, which may cause the wrong input value to be about 0.3% of the total input. This will make the entire chip work normally in most scenarios, but in some extreme cases it will work incorrectly. Only if the key is correct, it can be guaranteed that the correct output can be obtained no matter what value is input. The key may be included in an SDK (Software Development Kit) provided to a chip vendor, and the key may not be included in a hardware circuit.
The following mapping functions are illustrated.
For circuits in a conventional IP core (circuit diagrams in the fixed IP and the hard IP, and software code that can be converted into a circuit diagram, i.e., a functional block, in the soft IP), the function can be abstracted as a feature matrix B. An n-bit binary input a ═ a0 … an-1]After passing through this circuit (feature matrix B), n-bit output C ═ C is obtained0 … cn-1]。
In order to achieve the purpose of protecting the hardware IP core, we modify the feature matrix B of the existing IP core, and for some specific a (preset special data), we have a modified feature matrix B', as follows:
in this case, the output C' does not coincide with the desired output C, which may cause errors in subsequent operations. To control that only a small fraction (e.g. 0.3% probability mentioned above) of the operations are performed using B' (corresponding to the error handling unit 230), we randomly select the special A subset AX (predetermined special data) in advance, for example, we can define [ a ]0 … an-k]＝[1 … 1]B' is used in the calculation of the value of (A), so that
May cause errors (e.g., when n is 32 and k is 27, an error rate of approximately 0.3% may be satisfied). Our purpose is to avoid unauthorized use, so B' will only be introduced if not authorized. A key value k can be introduced0To ensure that when the correct k is input externally0In the case of (2), B' is not introduced and B is still kept in use (corresponding to correct processing)Unit 220).
In order to ensure the reusability of the circuit, more than one key value needs to be introduced, so that when the hardware IP core is delivered, the source can be operated by giving different key values to different customers. I.e. there are also other key values k1、k2、…、kmI.e. when the entered key value does not belong to the set K ═ K0、k1、k2、…、kmWhen the input values (data to be processed) belong to the set AX, the feature matrix B is replaced with B'. We can recombine K, AX, B and B' into a new feature matrix, which is used to replace the original feature matrix B, input these designed matrix modules into an EDA (electronic design automation) tool, and generate corresponding circuits by the EDA tool to integrate into the hardware IP core.
This key value K is ultimately given by the application software and is not provided at the chip design stage. The key value may be part of the boot firmware or the running firmware and contains a special field header that can be easily identified. After the chip is produced, the IP vendor will formally deliver the key to the chip vendor along with the SDK. Since there is more than one key, the same mapping function can be used with different correct keys as a unique identification provided to a certain chip manufacturer.
The above process is also a management method, a use method or a protection method of the IP core. By designing some of the critical operational logic in the circuit as a mapping function that requires an external input of a key, the mapping function can map its function correctly if the key is correct. In the case of incorrect key input, most inputs can be mapped to correct outputs, but mapping of a part of the inputs is incorrect, that is, correct outputs cannot be obtained, so that the function is incorrect. Thus, the key is necessary in contrast to the current use of only a serial number that is not function related as an identification. The invention does not affect the integrated evaluation and verification of the chip to the IP core under the condition of not having a correct key, and can completely carry out small-scale test evaluation under the condition of not having a correct key. The key may also serve as a unique identification number for the chip item from which source tracing and forensics may be performed. Therefore, the IP core is well protected from being embezzled and abused, and the intellectual property of the IP core is protected.
Based on the IP core, the chip provided by the invention comprises at least one IP core, in other words, partial circuit of the chip is manufactured according to the IP core. Correspondingly, as shown in fig. 4, the chip includes an IP core circuit including a key verification circuit 10 'and a data processing circuit 20'.
The key verification circuit 10 'is configured to receive an externally input key, determine whether the key is correct, and output a determination result to the data processing circuit 20'. That is, the key verification circuit 10 'functions identically to the key verification module 10, except that the key verification circuit 10' is in the form of an integrated circuit in a chip.
The data processing circuit 20' is configured to process the received data to be processed when the secret key is correct, and output a correct processing result; and when the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result according to a preset probability. Likewise, data processing circuit 20 'functions identically to data processing module 20, except that data processing circuit 20' is in the form of an integrated circuit in a chip.
Data processing circuit 20 'includes a decision sub-circuit 210', a correct processing sub-circuit 220 ', and an error processing sub-circuit 230'. The judgment sub-circuit 210 'is configured to judge whether the received data to be processed belongs to preset special data, and if so, start the error processing sub-circuit 230' to perform a second type of processing on the data to be processed, and output an error processing result; if the data to be processed does not belong to the preset special data, the correct processing sub-circuit 220' is activated to perform the first processing on the received data to be processed, and output a correct processing result. That is, the functions of the judgment sub-circuit 210 ', the correct processing sub-circuit 220 ' and the error processing sub-circuit 230 ' are respectively the same as the judgment unit 210, the correct processing unit 220 and the error processing unit 230 of the above embodiments, but each sub-circuit is presented in the form of an integrated circuit in a chip, and details are not described herein.
Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by computer programs. When all or part of the functions of the above embodiments are implemented by a computer program, the program may be stored in a computer-readable storage medium, and the storage medium may include: a read only memory, a random access memory, a magnetic disk, an optical disk, a hard disk, etc., and the program is executed by a computer to realize the above functions. For example, the program may be stored in a memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above may be implemented. In addition, when all or part of the functions in the above embodiments are implemented by a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a removable hard disk, and may be downloaded or copied to a memory of a local device, or may be version-updated in a system of the local device, and when the program in the memory is executed by a processor, all or part of the functions in the above embodiments may be implemented.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A method for managing an IP core, comprising:
receiving an externally input key;
judging whether the secret key is correct or not, if so, processing the received data to be processed, and outputting a correct processing result; and if the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result according to a preset probability.
2. The method for managing as claimed in claim 1, wherein said processing the received data to be processed to output an erroneous processing result with a predetermined probability comprises:
judging whether the received data to be processed belongs to preset special data or not, if so, processing the data to be processed, and outputting an error processing result; otherwise, processing the data to be processed and outputting a correct processing result; the occupation ratio of the special data in all possible data to be processed is the preset probability.
3. The management method according to claim 1 or 2, characterized in that said preset probability does not exceed 1%.
4. The method of managing of claim 1, wherein the determining whether the key is correct comprises:
judging whether the secret key belongs to a preset secret key set or not, if so, determining that the secret key is correct, and otherwise, determining that the secret key is incorrect; the set of keys includes a plurality of correct keys.
5. An IP core, comprising:
the key verification module is used for receiving an externally input key and judging whether the key is correct or not;
the data processing module is used for processing the received data to be processed when the secret key is correct and outputting a correct processing result; and when the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result according to a preset probability.
6. The IP core according to claim 5, wherein the data processing module processes the received data to be processed, and outputs an erroneous processing result with a predetermined probability, and the processing result includes:
judging whether the received data to be processed belongs to preset special data or not, if so, processing the data to be processed, and outputting an error processing result; otherwise, processing the data to be processed and outputting a correct processing result; the occupation ratio of the special data in all possible data to be processed is the preset probability.
7. The IP core of claim 5 or 6, wherein the predetermined probability does not exceed 1%.
8. The IP core of claim 5, wherein the key verification module to determine whether the key is correct comprises:
judging whether the secret key belongs to a preset secret key set or not, if so, determining that the secret key is correct, and otherwise, determining that the secret key is incorrect; the set of keys includes a plurality of correct keys.
9. A chip, characterized in that part of the circuitry of the chip is fabricated according to the IP core of any of claims 5-8.
10. A computer-readable storage medium, characterized in that the medium has stored thereon a program which is executable by a processor to implement the method of any one of claims 1 to 4.
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