CN111125789A - A chip key management method with multiple hardware IP cores - Google Patents
A chip key management method with multiple hardware IP cores Download PDFInfo
- Publication number
- CN111125789A CN111125789A CN201911218132.0A CN201911218132A CN111125789A CN 111125789 A CN111125789 A CN 111125789A CN 201911218132 A CN201911218132 A CN 201911218132A CN 111125789 A CN111125789 A CN 111125789A
- Authority
- CN
- China
- Prior art keywords
- hardware
- core
- bit
- updating
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007726 management method Methods 0.000 title claims abstract description 9
- 239000011159 matrix material Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000013598 vector Substances 0.000 claims abstract description 26
- 239000004576 sand Substances 0.000 claims description 3
- 230000017105 transposition Effects 0.000 claims description 3
- 239000000523 sample Substances 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
Abstract
本发明公开了一种具有多个硬件IP核的芯片密钥管理方法，包括加密过程和解密过程，在加密过程中引入内嵌多端口物理不可克隆函数对硬件IP核中预设的特征矢量进行更新，然后基于更新后的特征矢量构建正交混淆矩阵后对每个硬件IP核分别进行加密，在芯片用户对已授权硬件IP核进行解密时，芯片用户输入芯片厂家提供的芯片的128位二进制秘钥，当输入的128位二进制秘钥与该芯片中已授权的硬件IP核的解密秘钥匹配时才能实现已授权硬件IP核的解锁；优点是可以对芯片内每个硬件IP核独立的进行防护，避免芯片内部各个独立硬件IP核被旁道攻击和芯片探针等方式攻击，灵活性好，且防护性能高。The invention discloses a chip key management method with multiple hardware IP cores, including an encryption process and a decryption process. In the encryption process, a built-in multi-port physical unclonable function is introduced to perform a function on a preset feature vector in the hardware IP core. Update, and then construct an orthogonal confusion matrix based on the updated feature vector and encrypt each hardware IP core separately. When the chip user decrypts the authorized hardware IP core, the chip user enters the 128-bit binary code of the chip provided by the chip manufacturer. Secret key, when the input 128-bit binary secret key matches the decryption secret key of the authorized hardware IP core in the chip, the authorized hardware IP core can be unlocked; the advantage is that each hardware IP core in the chip can be independently Provide protection to prevent each independent hardware IP core inside the chip from being attacked by side-channel attacks and chip probes, with good flexibility and high protection performance.
Description
Technical Field
The invention relates to a chip key management method, in particular to a chip key management method with a plurality of hardware IP cores.
Background
In recent years, the integrated circuit industry has been rapidly developed, the chip scale is increased due to continuously updated integrated circuit process nodes, more and more examples of chips are cooperatively designed by multiple teams, and meanwhile, the hardware threat caused by internal information leakage among teams is increased.
The existing typical chip encryption method usually adopts an encryption mode of directly matching keys, and the principle is that a string of binary data sequence with the length of 16/32/64bit is prestored in a chip by using a ROM, an external input key is received, and only when the input key of the chip is equal to the binary data sequence prestored in the chip, a hardware IP core in the chip can normally work, so that the encryption of the hardware IP core is realized.
The current encryption method for directly matching the key uses an explicit key, a designer needs to set a chip key independently, and the explicit key in the multi-party cooperative design means that the designer can directly obtain hardware IP cores of all parties through the key, which is not beneficial to the common benefits of multi-party teams. In addition, the existence of the explicit key needs to set a ROM array or a register file in a chip as hardware support, an attacker can easily obtain the chip key through a chip probe and other modes, the protection effect is poor, the simple key matching method mainly aims at the protection of the whole chip, but each internal independent hardware IP core is easily attacked by a side channel attack, a chip probe and other modes, and the safety performance is low.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a chip key management method with a plurality of hardware IP cores, which can independently protect each hardware IP core in a chip, avoid the attack of each independent hardware IP core in the chip by a side channel attack, a chip probe and the like, and has good flexibility and high protection performance.
The technical scheme adopted by the invention for solving the technical problems is as follows: a chip key management method with a plurality of hardware IP cores comprises an encryption process and a decryption process, wherein each hardware IP core is respectively encrypted in the encryption process, and each hardware IP core is respectively decrypted in the decryption process;
the encryption process specifically comprises the following steps:
①, acquiring the total number of hardware IP cores in the chip, recording the total number as N, wherein N is an integer less than or equal to 50, sorting the N hardware IP cores according to the weight of each hardware IP core set by a hardware IP core designer from large to small, wherein the 1 st hardware IP core is the hardware IP core with the largest weight, the 2 nd hardware IP core is the hardware IP core with the second largest weight, and so on, the Nth hardware IP core is the hardware IP core with the smallest weight, and recording the serial number of the ith hardware IP core as IPi, i is 1, 2, …, N;
② presetting a feature vector in each hardware IP core, each feature vector comprises N-1 binary numbers of 8 bits, and recording the feature vector preset in the ith hardware IP core as KIPi，KIPi＝[ai1ai2…ai(N-2)ai(N-1)]Wherein a isijFor the preset characteristic vector K in the ith hardware IP coreIPiThe j-th 8-bit binary number, j is 1, 2, …, N-1;
③ embedding a multi-port physical unclonable function in a chip, wherein the multi-port physical unclonable function is used for providing 2N 8-bit binary numbers, the 2N 8-bit binary numbers provided by the multi-port physical unclonable function are randomly divided into N groups of 8-bit binary numbers, each group of 8-bit binary numbers respectively comprises two 8-bit binary numbers, and the two 8-bit binary numbers in the i-th group of 8-bit binary numbers are respectively marked as ei1And ei2；
Respectively updating the feature vectors preset in the 1 st to Nth hardware IP cores, wherein the specific mode is as follows: adding two 8-bit binary numbers in the ith group of 8-bit binary numbers to the feature vector K of the ith hardware IP coreIPiIn, to KIPiUpdating, the updated KIPiExpressed by formula (1):
KIPi＝[ai1ai2…ai(N-2)ai(N-1)ei1ei2](1)
④, constructing an orthogonal confusion matrix by using the current feature vectors of the 1 st to Nth hardware IP cores, and marking the orthogonal confusion matrix as O, wherein the orthogonal confusion matrix O is expressed by adopting an expression (2):
⑤ set KIPiThe simplified feature vector variable of (2) is,it is denoted as K'IPiSetting fixed point number, and recording the fixed point number as p, to K'IPiAnd the orthogonal confusion matrix O is respectively and sequentially updated for the first time, the first updating process comprises N-1 rounds, and the method specifically comprises the following steps:
s1, setting a first updating round variable and recording the first updating round variable as T;
s2, setting an updating frequency variable and recording the updating frequency variable as t;
s3, carrying out initialization assignment on T, and enabling T to be 1;
s4, initializing T, and enabling T to be T;
s5, entering into the Tth round and the T-th update: using the formula p ═ a(t+1)1÷a11Updating the fixed point number p for the t time, reserving two decimal places for the obtained p, and then adopting a formula K'IP(t+1)＝KIP(t+1)-KIP1X p to K'IP(t+1)Updating for the t 'th time, adopting K'IP(t+1)Updated value pair KIP(t+1)Is updated, and then the orthogonal confusion matrix O is updated again to ensure that K is in the orthogonal confusion matrix OIP(t+1)Is the latest value, p and K are calculated each time in the updating processIP(t+1)、KIP1、a(t+1)1And a11All the values of (A) are the current latest values;
s6, judging whether the current value of T is equal to N-1, if not, adopting the sum of the current value of T plus 1 to update the value of T, returning to the step S5 to carry out the next update, if so, judging whether the current value of T is equal to N-1, if not, adopting the sum of the current value of T plus 1 to update the value of T, returning to the step S4 to carry out the next update, if so, ending the first update, and entering the step ⑥.
⑥ to K'IPiAnd respectively and sequentially updating the orthogonal confusion matrix O again, wherein the updating process comprises N-1 rounds, and the specific steps are as follows:
A. setting a re-updating round variable, marking the re-updating round variable as G, and setting an intermediate parameter H;
B. setting an updating frequency variable and recording the updating frequency variable as g;
C. carrying out initialization assignment on H, and enabling H to be N-1;
D. assigning G, and enabling G to be N-H;
E. initializing G rows, and enabling G to be G;
F. entering the G-th update of the G-th round:
using the formula p ═ aHN÷aNNUpdating the fixed point number p, keeping two decimal places for p, and adopting a formula K'IPH＝KIPH-KIPNX p to K'IPHUpdating is carried out, K 'is adopted'IPHUpdated value pair KIPHUpdating the orthogonal confusion matrix O to KIPHIs the latest value, p and K in the formula are calculated each time in the updating processIPH、KIPN、aHNAnd aNNAre all their current latest values;
G. judging whether the current value of G is equal to N-1, if not, adopting the sum of the current value of G plus 1 to update the value of G, returning to the step F to carry out next updating, if so, judging whether the current value of G is equal to N-1, if not, adopting the difference of the current value of H minus 1 to update the value of H, returning to the step D to carry out next updating, if so, ending the updating again, and entering the step ⑦;
⑦ after the first N-1 update and the second N-1 update in steps ⑤ and ⑥, the orthogonal confusion matrix O obtained at this time is represented by equation (3):
⑧ the encryption process ends.
The decryption process specifically comprises the following steps:
① when a user of the chip needs to decrypt one or several hardware IP cores in the chip authorized by the chip manufacturer, the user inputs the 128-bit binary key of the chip provided by the chip manufacturer into the chip, the 1 st bit to the 16 th bit of the 128-bit binary key are configuration bits of the chip manufacturer, wherein the 1 st bit to the 4 th bit are all 0, the 6 th bit binary data composed of the 5 th bit to the 10 th bit is the number of the hardware IP cores authorized by the chip manufacturer, the 11 th bit isThe 16 th bit is a word length bit, the 6-bit binary data composed of the 11 th bit to the 16 th bit is a word length bit data, the word length bit data is denoted as W, and the value of W satisfies the condition: (N +1) × W is less than or equal to 112, the 17 th bit to the 128 th bit of the 128-bit binary key are set as chip manufacturer secret key positions, binary data selection is carried out from the 17 th bit of the 128-bit binary key according to the rule of once selecting every W-bit binary data until N + 1W-bit binary data are selected, and the W-bit binary data selected at the f-th time is recorded as kfAnd f is 1, 2, …, N +1, and a matrix is constructed by adopting the selected N + 1W-bit binary numbers, and the matrix is Kuser，KuserExpressed by formula (4):
Kuser＝[k1,k2,…,kN,kN+1]T(4)
wherein, the superscript T in the formula (4) represents the transposition of the matrix;
② calculation of O and KuserAnd (3) recording the calculated matrix as P, wherein the matrix P is expressed by an equation (5):
in the formula (5), psThe element representing the s-th row in the matrix P, s ═ 1, 2, …, N;
③ determination of psAnd if not, unlocking the s-th hardware IP core incorrectly, wherein the s-th hardware IP core is not authorized by the chip manufacturer and is not unlocked.
Compared with the prior art, the invention has the advantages that the invention updates the preset feature vector in the hardware IP core by introducing the embedded multi-port physical unclonable function in the encryption process, then encrypts each hardware IP core respectively after constructing the orthogonal confusion matrix based on the updated feature vector, when the chip user decrypts the authorized hardware IP core of the chip manufacturer, the chip user inputs the 128-bit binary key of the chip provided by the chip manufacturer, when the input 128-bit binary key is matched with the decryption key of the authorized hardware IP core, the unlocking of the hardware IP cores can be realized, thereby the invention can independently protect each hardware IP core in the chip, avoid the independent hardware IP cores in the chip from being attacked by the side channel attack, the chip probe and other modes, and has good flexibility, and the protective performance is high.
Detailed Description
The present invention will be described in further detail with reference to examples.
Example (b): a chip key management method with a plurality of hardware IP cores comprises an encryption process and a decryption process, wherein each hardware IP core is respectively encrypted in the encryption process, and each hardware IP core is respectively decrypted in the decryption process;
the encryption process specifically comprises the following steps:
①, acquiring the total number of hardware IP cores in the chip, recording the total number as N, wherein N is an integer less than or equal to 50, sorting the N hardware IP cores according to the weight of each hardware IP core set by a hardware IP core designer from large to small, wherein the 1 st hardware IP core is the hardware IP core with the largest weight, the 2 nd hardware IP core is the hardware IP core with the second largest weight, and so on, the Nth hardware IP core is the hardware IP core with the smallest weight, and recording the serial number of the ith hardware IP core as IPi, i is 1, 2, …, N;
② presetting a feature vector in each hardware IP core, each feature vector comprises N-1 binary numbers of 8 bits, and recording the feature vector preset in the ith hardware IP core as KIPi，KIPi＝[ai1ai2…ai(N-2)ai(N-1)]Wherein a isijFor the preset characteristic vector K in the ith hardware IP coreIPiThe j-th 8-bit binary number, j is 1, 2, …, N-1;
③ embedding a multi-port physically unclonable function in a chip, the multi-port physically unclonable function providing 2N 8-bit binary numbers, providing 2N 8-bit binary numbers using the multi-port physically unclonable function, and embedding the multi-port physically unclonable function in the chip2N 8-bit binary numbers provided by the unclonable function are randomly and equally divided into N groups of 8-bit binary numbers, each group of 8-bit binary numbers respectively comprise two 8-bit binary numbers, and two 8-bit binary numbers in the i-th group of 8-bit binary numbers are respectively marked as ei1And ei2；
Respectively updating the feature vectors preset in the 1 st to Nth hardware IP cores, wherein the specific mode is as follows: adding two 8-bit binary numbers in the ith group of 8-bit binary numbers to the feature vector K of the ith hardware IP coreIPiIn, to KIPiUpdating, the updated KIPiExpressed by formula (1):
KIPi＝[ai1ai2…ai(N-2)ai(N-1)ei1ei2](1)
④, constructing an orthogonal confusion matrix by using the current feature vectors of the 1 st to Nth hardware IP cores, and marking the orthogonal confusion matrix as O, wherein the orthogonal confusion matrix O is expressed by adopting an expression (2):
⑤ set KIPiIs denoted as K'IPiSetting fixed point number, and recording the fixed point number as p, to K'IPiAnd the orthogonal confusion matrix O is respectively and sequentially updated for the first time, the first updating process comprises N-1 rounds, and the method specifically comprises the following steps:
s1, setting a first updating round variable and recording the first updating round variable as T;
s2, setting an updating frequency variable and recording the updating frequency variable as t;
s3, carrying out initialization assignment on T, and enabling T to be 1;
s4, initializing T, and enabling T to be T;
s5, entering into the Tth round and the T-th update: using the formula p ═ a(t+1)1÷a11Updating the fixed point number p for the t time, reserving two decimal places for the obtained p, and then adopting a formula K'IP(t+1)＝KIP(t+1)-KIP1X p to K'IP(t+1)Updating for the t 'th time, adopting K'IP(t+1)Updated value pair KIP(t+1)Is updated, and then the orthogonal confusion matrix O is updated again to ensure that K is in the orthogonal confusion matrix OIP(t+1)Is the latest value, p and K are calculated each time in the updating processIP(t+1)、KIP1、a(t+1)1And a11All the values of (A) are the current latest values;
s6, judging whether the current value of T is equal to N-1, if not, adopting the sum of the current value of T plus 1 to update the value of T, returning to the step S5 to carry out the next update, if so, judging whether the current value of T is equal to N-1, if not, adopting the sum of the current value of T plus 1 to update the value of T, returning to the step S4 to carry out the next update, if so, ending the first update, and entering the step ⑥.
⑥ to K'IPiAnd respectively and sequentially updating the orthogonal confusion matrix O again, wherein the updating process comprises N-1 rounds, and the specific steps are as follows:
A. setting a re-updating round variable, marking the re-updating round variable as G, and setting an intermediate parameter H;
B. setting an updating frequency variable and recording the updating frequency variable as g;
C. carrying out initialization assignment on H, and enabling H to be N-1;
D. assigning G, and enabling G to be N-H;
E. initializing G rows, and enabling G to be G;
F. entering the G-th update of the G-th round:
using the formula p ═ aHN÷aNNUpdating the fixed point number p, keeping two decimal places for p, and adopting a formula K'IPH＝KIPH-KIPNX p to K'IPHUpdating is carried out, K 'is adopted'IPHUpdated value pair KIPHUpdating the orthogonal confusion matrix O to KIPHIs the latest value, p and K in the formula are calculated each time in the updating processIPH、KIPN、aHNAnd aNNAre all their current latest values;
G. judging whether the current value of G is equal to N-1, if not, adopting the sum of the current value of G plus 1 to update the value of G, returning to the step F to carry out next updating, if so, judging whether the current value of G is equal to N-1, if not, adopting the difference of the current value of H minus 1 to update the value of H, returning to the step D to carry out next updating, if so, ending the updating again, and entering the step ⑦;
⑦ after the first N-1 update and the second N-1 update in steps ⑤ and ⑥, the orthogonal confusion matrix O obtained at this time is represented by equation (3):
⑧ the encryption process ends.
The decryption process specifically comprises the following steps:
① when a chip user needs to decrypt one or several hardware IP cores in the chip authorized by the chip manufacturer, the chip user inputs the 128 bit binary key of the chip provided by the chip manufacturer into the chip, the 1 st bit to the 16 th bit of the 128 bit binary key are configuration bits of the chip manufacturer, wherein the 1 st bit to the 4 th bit are all 0, the 6 bit binary data formed by the 5 th bit to the 10 th bit is the number of the hardware IP cores authorized by the chip manufacturer, the 11 th bit to the 16 th bit are word length bits, the 6 bit binary data formed by the 11 th bit to the 16 th bit is word length data, the value of the word length data is marked as W, the value of the W satisfies the conditions that (N +1) W is not more than 112, the 17 th bit to the 128 th bit of the 128 bit binary key are set as the chip manufacturer key, the binary data is selected once from the 17 th bit of the 128 bit binary key according to the rule of binary data selection once per W bit until the binary data with N + 1W is selected, the f bit of the binary data is marked as kfAnd f is 1, 2, …, N +1, and a matrix is constructed by adopting the selected N + 1W-bit binary numbers, and the matrix is Kuser，KuserExpressed by formula (4):
Kuser＝[k1,k2,…,kN,kN+1]T(4)
wherein, the superscript T in the formula (4) represents the transposition of the matrix;
② calculation of O and KuserAnd (3) recording the calculated matrix as P, wherein the matrix P is expressed by an equation (5):
in the formula (5), psThe element representing the s-th row in the matrix P, s ═ 1, 2, …, N;
③ determination of psAnd if not, unlocking the s-th hardware IP core incorrectly, wherein the s-th hardware IP core is not authorized by the chip manufacturer and is not unlocked.
Claims (1)
1. A chip key management method with a plurality of hardware IP cores comprises an encryption process and a decryption process, and is characterized in that each hardware IP core is respectively encrypted in the encryption process, and each hardware IP core is respectively decrypted in the decryption process;
the encryption process specifically comprises the following steps:
①, acquiring the total number of hardware IP cores in the chip, recording the total number as N, wherein N is an integer less than or equal to 50, sorting the N hardware IP cores according to the weight of each hardware IP core set by a hardware IP core designer from large to small, wherein the 1 st hardware IP core is the hardware IP core with the largest weight, the 2 nd hardware IP core is the hardware IP core with the second largest weight, and so on, the Nth hardware IP core is the hardware IP core with the smallest weight, and recording the serial number of the ith hardware IP core as IPi, i is 1, 2, …, N;
② presetting a feature vector in each hardware IP core, each feature vector comprises N-1 binary numbers of 8 bits, and recording the feature vector preset in the ith hardware IP core as KIPi，KIPi＝[ai1ai2…ai(N-2)ai(N-1)]Wherein a isijFor the preset characteristic vector K in the ith hardware IP coreIPiThe j-th 8-bit binary number, j is 1, 2, …, N-1;
③ embedding a multi-port physical unclonable function in a chip, wherein the multi-port physical unclonable function is used for providing 2N 8-bit binary numbers, the 2N 8-bit binary numbers provided by the multi-port physical unclonable function are randomly divided into N groups of 8-bit binary numbers, each group of 8-bit binary numbers respectively comprises two 8-bit binary numbers, and the two 8-bit binary numbers in the i-th group of 8-bit binary numbers are respectively marked as ei1And ei2；
Respectively updating the feature vectors preset in the 1 st to Nth hardware IP cores, wherein the specific mode is as follows: adding two 8-bit binary numbers in the ith group of 8-bit binary numbers to the feature vector K of the ith hardware IP coreIPiIn, to KIPiUpdating, the updated KIPiExpressed by formula (1):
KIPi＝[ai1ai2…ai(N-2)ai(N-1)ei1ei2](1)
④, constructing an orthogonal confusion matrix by using the current feature vectors of the 1 st to Nth hardware IP cores, and marking the orthogonal confusion matrix as O, wherein the orthogonal confusion matrix O is expressed by adopting an expression (2):
⑤ set KIPiIs denoted as K'IPiSetting fixed point number, and recording the fixed point number as p, to K'IPiAnd the orthogonal confusion matrix O is respectively and sequentially updated for the first time, the first updating process comprises N-1 rounds, and the method specifically comprises the following steps:
s1, setting a first updating round variable and recording the first updating round variable as T;
s2, setting an updating frequency variable and recording the updating frequency variable as t;
s3, carrying out initialization assignment on T, and enabling T to be 1;
s4, initializing T, and enabling T to be T;
s5, entering into the Tth round and the T-th update: using the formula p ═ a(t+1)1÷a11Updating the fixed point number p for the t time, reserving two decimal places for the obtained p, and then adopting a formula K'IP(t+1)＝KIP(t+1)-KIP1X p to K'IP(t+1)Updating for the t 'th time, adopting K'IP(t+1)Updated value pair KIP(t+1)Is updated, and then the orthogonal confusion matrix O is updated again to ensure that K is in the orthogonal confusion matrix OIP(t+1)Is the latest value, p and K are calculated each time in the updating processIP(t+1)、KIP1、a(t+1)1And a11All the values of (A) are the current latest values;
s6, judging whether the current value of T is equal to N-1, if not, adopting the sum of the current value of T plus 1 to update the value of T, returning to the step S5 to carry out the next update, if so, judging whether the current value of T is equal to N-1, if not, adopting the sum of the current value of T plus 1 to update the value of T, returning to the step S4 to carry out the next update, if so, ending the first update, and entering the step ⑥.
⑥ to K'IPiAnd respectively and sequentially updating the orthogonal confusion matrix O again, wherein the updating process comprises N-1 rounds, and the specific steps are as follows:
A. setting a re-updating round variable, marking the re-updating round variable as G, and setting an intermediate parameter H;
B. setting an updating frequency variable and recording the updating frequency variable as g;
C. carrying out initialization assignment on H, and enabling H to be N-1;
D. assigning G, and enabling G to be N-H;
E. initializing G rows, and enabling G to be G;
F. entering the G-th update of the G-th round:
using the formula p ═ aHN÷aNNUpdating the fixed point number p, keeping two decimal places for p, and adopting a formula K'IPH＝KIPH-KIPNX p to K'IPHUpdating is carried out, K 'is adopted'IPHUpdated value pair KIPHUpdating the orthogonal confusion matrix O to KIPHIs the most importantNew value, p, K in formula at each calculation in the updating processIPH、KIPN、aHNAnd aNNAre all their current latest values;
G. judging whether the current value of G is equal to N-1, if not, adopting the sum of the current value of G plus 1 to update the value of G, returning to the step F to carry out next updating, if so, judging whether the current value of G is equal to N-1, if not, adopting the difference of the current value of H minus 1 to update the value of H, returning to the step D to carry out next updating, if so, ending the updating again, and entering the step ⑦;
⑦ after the first N-1 update and the second N-1 update in steps ⑤ and ⑥, the orthogonal confusion matrix O obtained at this time is represented by equation (3):
⑧ the encryption process ends.
The decryption process specifically comprises the following steps:
① when a chip user needs to decrypt one or several hardware IP cores in the chip authorized by the chip manufacturer, the chip user inputs the 128 bit binary key of the chip provided by the chip manufacturer into the chip, the 1 st bit to the 16 th bit of the 128 bit binary key are configuration bits of the chip manufacturer, wherein the 1 st bit to the 4 th bit are all 0, the 6 bit binary data formed by the 5 th bit to the 10 th bit is the number of the hardware IP cores authorized by the chip manufacturer, the 11 th bit to the 16 th bit are word length bits, the 6 bit binary data formed by the 11 th bit to the 16 th bit is word length data, the value of the word length data is marked as W, the value of the W satisfies the conditions that (N +1) W is not more than 112, the 17 th bit to the 128 th bit of the 128 bit binary key are set as the chip manufacturer key, the binary data is selected once from the 17 th bit of the 128 bit binary key according to the rule of binary data selection once per W bit until the binary data with N + 1W is selected, the f bit of the binary data is marked as kfAnd f is 1, 2, …, N +1, and a matrix is constructed by adopting the selected N + 1W-bit binary numbers, and the matrix is Kuser，KuserExpressed by formula (4):
Kuser＝[k1,k2,…,kN,kN+1]T(4)
wherein, the superscript T in the formula (4) represents the transposition of the matrix;
② calculation of O and KuserAnd (3) recording the calculated matrix as P, wherein the matrix P is expressed by an equation (5):
in the formula (5), psThe element representing the s-th row in the matrix P, s ═ 1, 2, …, N;
③ determination of psAnd if not, unlocking the s-th hardware IP core incorrectly, wherein the s-th hardware IP core is not authorized by the chip manufacturer and is not unlocked.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911218132.0A CN111125789B (en) | 2019-12-03 | 2019-12-03 | Chip key management method with multiple hardware IP cores |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911218132.0A CN111125789B (en) | 2019-12-03 | 2019-12-03 | Chip key management method with multiple hardware IP cores |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111125789A true CN111125789A (en) | 2020-05-08 |
| CN111125789B CN111125789B (en) | 2023-03-14 |
Family
ID=70497123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911218132.0A Active CN111125789B (en) | 2019-12-03 | 2019-12-03 | Chip key management method with multiple hardware IP cores |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111125789B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113032791A (en) * | 2021-04-01 | 2021-06-25 | 深圳市纽创信安科技开发有限公司 | IP core, IP core management method and chip |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103198268A (en) * | 2013-03-18 | 2013-07-10 | 宁波大学 | Reconfigurable multi-port physical unclonable functions (PUF) circuit |
| CN104283549A (en) * | 2014-09-15 | 2015-01-14 | 宁波大学 | A PUF Circuit Based on MOSFET Zero Temperature Coefficient Point |
| CN104318181A (en) * | 2014-09-22 | 2015-01-28 | 宁波大学 | PUF circuit based on threshold deviation delay |
| CN104320246A (en) * | 2014-09-22 | 2015-01-28 | 宁波大学 | Configurable multi-bit key output TVD-PUFs (Threshold Variation Delay-Physical Unclonable functions) circuit |
| CN105676942A (en) * | 2016-03-08 | 2016-06-15 | 宁波大学 | Deviation signal producing circuit and multiport configurable PUF circuit |
| CN109543467A (en) * | 2018-10-31 | 2019-03-29 | 宁波大学 | A kind of chip means of defence with multiple Hardware I P cores |
| CN110309574A (en) * | 2019-06-25 | 2019-10-08 | 北京智涵芯宇科技有限公司 | The PUF circuit and chip of chip production manufacture and use circuit physical integrality can be perceived |
-
2019
- 2019-12-03 CN CN201911218132.0A patent/CN111125789B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103198268A (en) * | 2013-03-18 | 2013-07-10 | 宁波大学 | Reconfigurable multi-port physical unclonable functions (PUF) circuit |
| CN104283549A (en) * | 2014-09-15 | 2015-01-14 | 宁波大学 | A PUF Circuit Based on MOSFET Zero Temperature Coefficient Point |
| CN104318181A (en) * | 2014-09-22 | 2015-01-28 | 宁波大学 | PUF circuit based on threshold deviation delay |
| CN104320246A (en) * | 2014-09-22 | 2015-01-28 | 宁波大学 | Configurable multi-bit key output TVD-PUFs (Threshold Variation Delay-Physical Unclonable functions) circuit |
| CN105676942A (en) * | 2016-03-08 | 2016-06-15 | 宁波大学 | Deviation signal producing circuit and multiport configurable PUF circuit |
| CN109543467A (en) * | 2018-10-31 | 2019-03-29 | 宁波大学 | A kind of chip means of defence with multiple Hardware I P cores |
| CN110309574A (en) * | 2019-06-25 | 2019-10-08 | 北京智涵芯宇科技有限公司 | The PUF circuit and chip of chip production manufacture and use circuit physical integrality can be perceived |
Non-Patent Citations (4)
| Title |
|---|
| JIAWEI WANG 等: "AN ORTHOGONAL OBFUSCATION METHOD ON EXTEND INSTRUCTION SETS FOR SEQURITY RISC-V CIRCUIT" * |
| ZHAO PAN 等: "Obfuscation Algorithm Design Based on Fully Homomorphism" * |
| 张跃军;潘钊;汪鹏君;丁代鲁;李刚;: "基于状态映射的AES算法硬件混淆设计" * |
| 汪鹏君;张学龙;张跃军;: "基于最优控制电压的高鲁棒性PUF电路设计" * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113032791A (en) * | 2021-04-01 | 2021-06-25 | 深圳市纽创信安科技开发有限公司 | IP core, IP core management method and chip |
| CN113032791B (en) * | 2021-04-01 | 2024-05-31 | 深圳市纽创信安科技开发有限公司 | IP core, IP core management method and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111125789B (en) | 2023-03-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11507705B2 (en) | Determining cryptographic operation masks for improving resistance to external monitoring attacks | |
| EP3770751B1 (en) | High speed encryption key generating engine | |
| Khan et al. | A new hybrid image encryption algorithm based on 2D-CA, FSM-DNA rule generator, and FSBI | |
| KR20180002069A (en) | A protection method and device against a side-channel analysis | |
| CN108964872B (en) | Encryption method and device based on AES | |
| CN108055120B (en) | A method for detecting AES-OTR algorithm against differential fault attack | |
| CN110197076B (en) | A Software Optimization Implementation Method of SM4 Encryption Algorithm | |
| CN1989726B (en) | Method and device for executing cryptographic calculation | |
| CN109347633B (en) | Fuzzy key communication system based on deep learning and countermeasure network system | |
| KR20090041408A (en) | Cryptographic apparatus, recording media, and methods | |
| CN106327414A (en) | Plaintext feature-based double-chaos image encryption method | |
| Li et al. | Cryptanalyzing an image encryption algorithm underpinned by 2-D lag-complex logistic map | |
| Deepthi et al. | Cryptanalysis of Salsa and ChaCha: revisited | |
| Duan et al. | Differential power analysis attack and efficient countermeasures on PRESENT | |
| Mazumdar et al. | Power analysis attacks on ARX: an application to Salsa20 | |
| CN109543467B (en) | Chip protection method with multiple hardware IP cores | |
| Deepthi Kakumani et al. | Improved related-cipher attack on Salsa and ChaCha: revisited | |
| CN111125789A (en) | A chip key management method with multiple hardware IP cores | |
| Crowley | Improved cryptanalysis of Py | |
| Ambili et al. | Reinforcing lightweight authenticated encryption schemes against statistical ineffective fault attack | |
| Taher et al. | Best S-box amongst differently sized S-boxes based on the avalanche effect in the advance encryption standard algorithm | |
| EP3832945A1 (en) | System and method for protecting memory encryption against template attacks | |
| Riazi et al. | PriSearch: Efficient search on private data | |
| US20050147244A1 (en) | Method for cryptographic transformation of binary data blocks | |
| Wen et al. | A novel PUF architecture against non-invasive attacks |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |