CN112992964B - Light-emitting diode structure and manufacturing method thereof - Google Patents

Abstract

The application discloses a light emitting diode structure and a manufacturing method thereof. The light emitting diode structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes: a bonding layer formed on the substrate; a first doping type semiconductor layer formed on the bonding layer; a second doping type semiconductor layer formed on the first doping type semiconductor layer; a passivation layer formed on the second doping type semiconductor layer and a portion of the first doping type semiconductor layer; and an electrode layer formed on a portion of the passivation layer and in contact with the second doping type semiconductor layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first doping type semiconductor layer of the first LED unit horizontally extends to the first doping type semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are independently operable LED units.

Description

Light-emitting diode structure and manufacturing method thereof

Cross References to Related Applications

This application claims priority to U.S. Provisional Patent Application No. 63/007,829, filed April 9, 2020, entitled "Semiconductor Array and Method of Monolithic Integration," and also claims 2021 Priority to U.S. Official Patent Application No. 17/162,515, entitled "LIGHT EMITTING DIODE STRUCTURE AND METHOD FOR MANUFACTURING THESAME," filed January 29, 2011, the disclosure of which is hereby adopted References are incorporated in their entirety.

technical field

The present application relates to a light-emitting diode (LED) structure and a method of manufacturing the LED structure, and more particularly, to an LED structure having a plurality of individually operable LED units while sharing a doped layer and a method of manufacturing the same .

Background technique

In recent years, LEDs have become popular in lighting applications. As a light source, LEDs have many advantages, including higher light efficiency, lower energy consumption, longer lifetime, smaller size, and faster switching speed.

Micro-LED displays have arrays of micro-LEDs (micro-LEDs) with multiple single-pixel elements. A pixel is a tiny illuminated area on a display screen, and many pixels can make up an image. In other words, pixels can be small discrete elements that together make up an image on a display. Pixels are usually arranged in a two-dimensional (2D) matrix and represented using dots, squares, rectangles, or other shapes. A pixel can be the basic unit of a display or a digital image and has geometric coordinates.

When manufacturing micro-LEDs, processes such as dry etching or wet etching are often used to electrically isolate individual micro-LEDs. In order to produce multiple fully isolated functional micro-LED pixels, conventional processes typically completely etch away the continuous functional epitaxial layer. However, when transferring conventional Micro LED pixels onto a substrate such as a driving circuit substrate or after transfer, completely isolated functional Micro LED pixels may be easily peeled off from the substrate due to weak adhesion of the Micro LED pixels. This problem gets worse when Micro LED pixels get smaller. Furthermore, during the conventional etching process to isolate the Micro-LED pixels, the sidewalls of the Micro-LED pixels may be damaged and affect the optical and electrical properties of the LED structure.

Embodiments of the present application solve the above-mentioned problems by providing an LED structure having a plurality of individually operable LED units and a method of manufacturing the same while sharing a doped layer or a bonding layer.

Contents of the invention

Embodiments of an LED structure and a method of forming the LED structure are disclosed herein.

In one embodiment, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes: a bonding layer formed on the substrate; a first doped semiconductor layer formed on the bonding layer; a second doped semiconductor layer formed on the first doped semiconductor layer on; a passivation layer formed on the second doping type semiconductor layer and a part of the first doping type semiconductor layer; and an electrode layer formed on a part of the passivation layer and connected to the second doping type semiconductor layer layer contact. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first doped semiconductor layer of the first LED unit extends horizontally and is physically connected to the first doped semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED Units are LED units that work individually.

In another embodiment, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes: a p-n diode layer formed on the substrate; a passivation layer formed on the p-n diode layer; and an electrode layer formed on the passivation layer and in contact with the p-n diode layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first LED unit and the second LED unit have a common anode, and the first LED unit and the second LED unit are individually operable LED units.

In a further embodiment, a method for fabricating an LED structure is disclosed, comprising:

forming a semiconductor layer on the first substrate, the semiconductor layer including a first doped type semiconductor layer and a second doped type semiconductor layer;

performing a first etching operation to remove a portion of the second doped semiconductor layer and expose a portion of the first doped semiconductor layer;

performing a second etching operation to remove a portion of the first doped semiconductor layer and expose a portion of the first substrate having a pixel circuit contact;

forming a passivation layer on the second doped semiconductor layer and the exposed first doped semiconductor layer;

performing a third etching operation to form a first opening on the passivation layer on the second doped semiconductor layer, and forming a second opening on the passivation layer on the first substrate having pixel circuit contacts;

An electrode layer is formed on the passivation layer covering the first opening and contacting the second doping type semiconductor layer and covering the second opening and contacting the second doping type semiconductor layer.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to further explain the application and enable those skilled in the art to make and use the application.

Figure 1 shows a top view of an illustrative LED structure according to some embodiments of the present application.

Figure 2 shows a cross-sectional view of an illustrative LED structure according to some embodiments of the present application.

Figure 3 shows another cross-sectional view of an illustrative LED structure according to some embodiments of the present application.

Figure 4 shows another top view of an illustrative LED structure according to some embodiments of the present application.

5 shows a top view of another illustrative LED structure according to some embodiments of the present application.

6A-6H show cross-sectional views of illustrative LED structures at various stages of the fabrication process, according to some embodiments of the present application.

7 is a flowchart of an illustrative method for fabricating an LED structure according to some embodiments of the present application.

Embodiments of the present application will be described below with reference to the drawings.

Detailed ways

While specific configurations and arrangements are discussed, it should be understood that this is done for illustration purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of the present application. Moreover, the present application may be employed in a variety of other applications as well. Functional and structural features described in this application may be combined, adjusted and modified with each other and in various ways not specifically shown in the drawings, so that these combinations, adjustments and modifications are within the scope of this application.

In general, terms can be understood at least in part from contextual usage. For example, the term "one or more" as used herein may be used to describe any component, structure or feature in the singular or a combination of components, structures or features in the plural, depending at least in part on the context. Similarly, terms such as "a", "an" or "the" may also be read to convey singular usage or to convey plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may instead allow for the presence of additional factors that do not necessarily have to be explicitly described, depending at least in part on the context.

It should be readily understood that the meanings of "on", "over" and "over" in this application should be interpreted in the broadest possible manner, so that "on" does not only mean "directly on something "on", but also means "on something" that includes an intermediate component or layer that exists between the two, and "on something" or "on something" not only means "on something " or "on something", but also includes the meaning of "on something" or "over something" in which there is no intermediate component or layer in between.

In addition, for the convenience of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe an element or part and an accompanying relationship to another element or component shown in the figure. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material comprising a region having a certain thickness. A layer may extend across the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. Layers may extend horizontally, vertically and/or along the tapered surface. A substrate can be one layer, can include one or more layers therein, and/or can have one or more layers thereon, above, and/or below. A layer can include multiple layers. For example, a semiconductor layer may comprise one or more doped or undoped semiconductor layers, and may be of the same or different materials.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. Materials added to the top of the substrate can be patterned or can remain unpatterned. Additionally, the substrate may include a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic or a sapphire wafer. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

As used herein, the terms "micro" LED, "miniature" p-n diode, or "micro" device refer to descriptive dimensions of certain devices or structures according to embodiments of the application. As used herein, the term "micro" device or structure is intended to mean the scale of 0.1 to 100 μm. It should be understood, however, that embodiments of the present application are not necessarily so limited, and that certain aspects of the embodiments may be applicable to larger and possibly smaller scales.

Embodiments of the present application describe LED structures or micro-LED structures and a method for fabricating the structures. To fabricate micro-LED displays, the epitaxial layer is bonded to a receiving substrate. The receiving substrate may be, for example but not limited to, a display substrate including a CMOS backplane or a TFT glass substrate. The epitaxial layer is then formed with a micro LED array on the receiving substrate. When micro-LEDs are formed on a receiving substrate, since the adhesion of small functional pixels on the receiving substrate is weak and proportional to the pixel size, multiple small functional pixels may be peeled off from the receiving substrate, resulting in Causes display failures (dead pixels) during the manufacturing process. To address the above issues, the present application introduces a solution in which the functional epitaxial layer is partially patterned/etched and allows a thin continuous functional layer and bonding layer to remain to avoid potential functional pixel lift-off. In addition, the manufacturing method described in this application can further reduce the physical damage of the sidewall of the functional pixel, reduce the damage of the quantum well structure as the light emitting region of the LED, and improve the optical and electrical properties of the functional pixel.

1 shows a top view of an exemplary LED structure 100 according to some embodiments of the present application, and FIG. 2 shows a cross-sectional view of an exemplary LED structure 100 along line AA' according to some embodiments of the present application. . In order to better explain the present application, the top view of the LED structure 100 in FIG. 1 and the cross-sectional view of the LED structure 100 in FIG. 2 will be described together. The LED structure 100 includes a first substrate 102 and a plurality of LED units 116 (eg, LED units 116-1, 116-2, 116-3, and 116-4 as shown in FIG. 2). The LED unit 116 is bonded on the first substrate 102 through the bonding layer 104 . In some embodiments, the first substrate 102 may include a semiconductor material, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide. In some implementations, the first substrate 102 may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer. In some embodiments, the first substrate 102 may have a driving circuit formed therein, and the first substrate 102 may be a CMOS backplane or a TFT glass substrate. The drive circuit provides an electrical signal to the LED unit 116 to control brightness. In some embodiments, the driver circuit may comprise an active matrix driver circuit, wherein each individual LED unit 116 corresponds to an independent driver. In some embodiments, the driving circuit may include a passive matrix driving circuit, wherein a plurality of LED units 116 are arranged in an array and connected to data lines and scan lines driven by the driving circuit.

The bonding layer 104 is an adhesive material layer formed on the first substrate 102 to bond the first substrate 102 and the LED unit 116 . In some implementations, the bonding layer 104 may include a conductive material, such as a metal or metal alloy. In some embodiments, the bonding layer 104 may include Au, Sn, In, Cu, or Ti. In some embodiments, the bonding layer 104 may include a non-conductive material, such as polyimide (PI), polydimethylsiloxane (PDMS). In some implementations, the bonding layer 104 may include a photoresist, such as SU-8 photoresist. In some embodiments, the bonding layer 104 can be hydrogen silsesquioxane (HSQ) or divinylsiloxane-bis-benzocyclobutene (DVS-BCB). It should be understood that the description of the material of the bonding layer 104 is only exemplary rather than limiting, and those skilled in the art may make changes according to requirements, and all these changes are within the scope of the present application.

Referring to FIG. 2 , each LED unit 116 includes part of the bonding layer 104 , the first doped semiconductor layer 106 and the second doped semiconductor layer 108 . The first doped semiconductor layer 106 is formed on the bonding layer 104 . In some implementations, the first doped semiconductor layer 106 and the second doped semiconductor layer 108 may include materials based on II-VI materials (such as ZnSe or ZnO) or III-V nitride materials (such as GaN, AlN, InN , InGaN, GaP, AlInGaP, AlGaAs and their alloys) one or more layers.

In some embodiments, the first doped semiconductor layer 106 can be p type semiconductor layer. For example, the first doped semiconductor layer 106 of the LED unit 116-2 extends to its adjacent LED units 116-1 and 116-3, similarly, the first doped semiconductor layer 106 of the LED unit 116-3 extends to its adjacent LED units 116-2 and 116-4. In some embodiments, the first doped semiconductor layer 106 extending across the LED unit can be relatively thin. In some embodiments, the thickness of the first doped semiconductor layer 106 may be between about 0.05 μm and about 1 μm. In some other embodiments, the thickness of the first doped semiconductor layer 106 may be between about 0.05 μm and about 0.7 μm. In some alternative embodiments, the thickness of the first doped semiconductor layer 106 may be between about 0.05 μm and about 0.5 μm. By having a continuous thin layer of the first doped semiconductor on each LED unit, the bonding area between the substrate 102 and the plurality of LED units 116 is not limited to the area under the second doped semiconductor layer 108, but also extends to the area between the individual LED units. In other words, by having a continuous thin layer of the first doped type semiconductor 106, the area of the bonding layer 104 is increased. Therefore, the bonding strength between the substrate 102 and the plurality of LED units 116 is enhanced, and the risk of delamination of the LED structure 100 can be reduced.

In some embodiments, the first doped semiconductor layer 106 may be p-type GaN. In some embodiments, the first doped semiconductor layer 106 may be formed by doping GaN with magnesium (Mg). In some embodiments, the first doped semiconductor layer 106 may be p-type InGaN. In some embodiments, the first doped semiconductor layer 106 may be p-type AlInGaP. Each LED unit 116 has an anode and a cathode connected to a driving circuit, for example, formed in the substrate 102 (the driving circuit is not explicitly shown in the figure). For example, each LED unit 116 has an anode connected to a constant voltage source and a cathode connected to a source/drain of a driver circuit. In other words, by forming a continuous first doped semiconductor 106 across each LED unit 116 , multiple LED units 116 have a common anode formed by the first doped semiconductor layer 106 and the bonding layer 104 .

In some embodiments, the second doped semiconductor layer 108 can be an n-type semiconductor layer and forms the cathode of each LED unit 116 . In some embodiments, the second doped semiconductor layer 108 may be n-type GaN. In some embodiments, the second doped semiconductor layer 108 may be n-type InGaN. In some embodiments, the second doped semiconductor layer 108 may be n-type AlInGaP. The second doped semiconductor layer 108 of different LED units 116 are electrically isolated so that each LED unit 116 can have a cathode at a different voltage level than the other units. As a result of the disclosed embodiments, a plurality of individually operable LED units 116 are formed whose first doped semiconductor layer 106 extends horizontally across adjacent LED units and whose second doped semiconductor layer 108 Adjacent LED units are electrically isolated.

Each LED unit 116 further includes a multiple quantum well (MQW) layer 110 formed between the first doped semiconductor layer 106 and the second doped semiconductor layer 108 . The MQW layer 110 is the active area of the LED unit 116 . In some embodiments, the thickness including the first doped semiconductor layer 106 and the second doped semiconductor layer 108 may be between about 0.3 μm and about 5 μm. In some other embodiments, the thickness including the first doped semiconductor layer 106 , the MQW layer 110 and the second doped semiconductor layer 108 may be between about 0.4 μm and about 4 μm. In some alternative embodiments, the thickness including the first doped semiconductor layer 106 , the MQW layer 110 and the second doped semiconductor layer 108 may be between about 0.5 μm and about 3 μm.

As shown in FIG. 2 , a passivation layer 112 is formed on a portion of the second doped semiconductor layer 108 and the first doped semiconductor layer 106 . Passivation layer 112 may serve to protect and isolate LED unit 116 . In some embodiments, the passivation layer 112 may include SiO ₂ , Al ₂ O ₃ , SiN, or other suitable materials. In some embodiments, passivation layer 112 may comprise polyimide, SU-8 photoresist, or other photo-patternable polymers. The electrode layer 114 is formed on a part of the passivation layer 112 , and the electrode layer 114 is electrically connected to the second doped semiconductor layer 108 through the opening on the passivation layer 112 . In some embodiments, the electrode layer 114 may be a conductive material such as indium tin oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge, or Ni.

Figure 3 shows another cross-sectional view of an illustrative LED structure 100 along line B-B' according to some embodiments of the present application. The first substrate 102 has a driving circuit for driving the LED unit 116 formed therein. The contact 118 of the driving circuit is exposed between the two LED units 116 , and the contact 118 is electrically connected to the second doped semiconductor layer 108 through the electrode layer 114 . In other words, the electrical connection between the second doped semiconductor layer 108 and the contact 118 of the driving circuit is completed by the electrode layer 114 . As mentioned above, the second doped semiconductor layer 108 forms the cathode of each LED unit 116, so the contact 118 provides the cathode for each LED unit 116 from the driving circuit to the second doped semiconductor layer 108 through the electrode layer 114. the drive voltage.

FIG. 4 shows another top view of an LED structure 100 according to some embodiments of the application. In FIG. 4, the electrode layer 114 and the layers below the passivation layer 112 are shown with dashed lines for explanatory purposes. In FIG. 4 , the LED structure 100 includes 16 LED units 116 . Each LED unit 116 includes a p-n diode layer formed by the first doped semiconductor layer 106 and the second doped semiconductor layer 108 and the multiple quantum well 110 . A passivation layer 112 is formed on the p-n diode, and an electrode layer 114 is formed on the passivation layer 112 .

An opening 120 is formed on the passivation layer 112 exposing the second doped semiconductor layer 108 , and an opening 122 is formed on the passivation layer 112 exposing the contact 118 . The electrode layer 114 is formed on the portion of the passivation layer 112 covering the opening 120 and the opening 122 , and thus, the electrode layer 114 is electrically connected to the second doped semiconductor layer 108 and the contact 118 . As shown illustratively in FIG. 4 , opening 120 is located at the center of each LED unit 116 and opening 122 is located at the gap between adjacent LED units 116 . It should be understood that the location and design (such as shape and size) of the openings 120, 122, and electrode layer 114 may deviate from the example shown in FIG. 4 based on requirements, and are not limited thereto.

In FIG. 4, the LED structure 100 includes 16 LED units 116, and each LED unit 116 can work independently. The first doped semiconductor layer 106 is located under the second doped semiconductor layer 108 and the passivation layer 112 , and the first doped semiconductor layer 106 is a common anode of the 16 LED units 116 . According to the present application, when the first doped semiconductor layers 106 of these LED units (for example, 16 LED units 16) are electrically connected not only during the manufacturing process of forming the LED structure 100 but also after the manufacturing process, and each LED unit Multiple LED units are said to be "independently operable" when they can be independently driven by different driving circuits.

FIG. 5 shows a top view of another LED structure 500 according to some embodiments of the application. In the top view in FIG. 5, the shape of the second doped semiconductor layer 108 is circular, which is the same as the shape of the second doped semiconductor layer 108 in the top view of the LED structure 100 shown in FIG. different. It should be understood that, in some embodiments, the position and shape of the second doped semiconductor layer 108 in the top view can be changed according to various designs or applications, and the second doped semiconductor layer 108 in the top view or the LED The shape of the unit 116 is not limited thereto. In some embodiments, the positions and shapes of the opening 120 , the opening 122 , the electrode layer 114 or the contact 118 in the top view may also vary according to various designs and applications, and are not limited thereto.

6A-6H show cross-sectional views of an exemplary LED structure 100 during a fabrication process according to some embodiments of the present application, and FIG. 7 is an illustration for fabricating an LED structure 100 according to some embodiments of the present application. A flowchart of the method 700. In order to better explain the present application, the flowcharts in FIGS. 6A to 6H and FIG. 7 will be described together. In FIG. 6A , a driving circuit is formed in the first substrate 102 and includes contacts 118 . For example, the drive circuit may include a CMOS device fabricated on a silicon wafer, and some wafer-level packaging layers or fan-out structures are stacked on the CMOS device to form contacts 118 . For another example, the driving circuit may include TFTs fabricated on a glass substrate, and some wafer-level packaging layers or fan-out structures are stacked on the TFTs to form contacts 118 . A semiconductor layer is formed on the second substrate 124 , and the semiconductor layer includes the first doped semiconductor layer 106 , the second doped semiconductor layer 108 and the MQW layer 110 .

In some embodiments, the first substrate 102 or the second substrate 124 may include a semiconductor material such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide. In some embodiments, the first substrate 102 or the second substrate 124 may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer. In some embodiments, the first substrate 102 may have a driving circuit formed therein, and the first substrate 102 may include a CMOS backplane or a TFT glass substrate. In some implementations, the first doped semiconductor layer 106 and the second doped semiconductor layer 108 may include materials based on II-VI materials (such as ZnSe or ZnO) or III-V nitride materials (such as GaN, AlN, InN , InGaN, GaP, AlInGaP, AlGaAs and their alloys) one or more layers. In some embodiments, the first doped semiconductor layer 106 may include a p-type semiconductor layer, and the second doped semiconductor layer 108 may include an n-type semiconductor layer.

In FIG. 6B , a bonding layer 104 is formed on the first substrate 102 . In some implementations, the bonding layer 104 may include a conductive material, such as a metal or metal alloy. In some embodiments, the bonding layer 104 may include Au, Sn, In, Cu, or Ti. In some embodiments, the bonding layer 104 may include a non-conductive material, such as polyimide (PI), polydimethylsiloxane (PDMS). In some implementations, the bonding layer 104 may include a photoresist, such as SU-8 photoresist. In some embodiments, the bonding layer 104 can be hydrogen silsesquioxane (HSQ) or divinylsiloxane-bis-benzocyclobutene (DVS-BCB). In some implementations, the conductive layer 126 may form a common electrode covering the first doped semiconductor layer 106 . In some embodiments, the conductive layer 126 can form an ohmic contact on the first doped semiconductor layer 106 . In some embodiments, the conductive layer 126 and the bonding layer 104 may be collectively referred to as one layer in subsequent operations.

Referring to FIG. 6C and operation 702 of FIG. 7, the second substrate 124 and the semiconductor layers including the first doped semiconductor layer 106, the second doped semiconductor layer 108 and the MQW layer 110 are turned over and passed through the bonding layer 104 and the conductive Layer 126 is bonded to first substrate 102 . Then, the second substrate 124 may be removed from the semiconductor layer. FIG. 6C shows the bonding layer 104 between the first substrate 102 and the first doped semiconductor layer 106. However, in some embodiments, the bonding layer 104 may include one or more layers to bond the first substrate 102 and the first doped semiconductor layer 106 . For example, bonding layer 104 may include a single conductive or non-conductive layer. For another example, the bonding layer 104 may include an adhesive material and a conductive or non-conductive layer. In some implementations, after operation 702, bonding layer 104 and conductive layer 126 may be collectively referred to as one layer. It should be understood that the description of the material of the bonding layer 104 is only illustrative rather than restrictive, and those skilled in the art may make changes according to requirements, and all such changes are within the scope of the present application.

In FIG. 6D , a thinning operation may be performed on the second doped semiconductor layer 108 to remove a portion of the second doped semiconductor layer 108 . In some embodiments, the thinning operation may include a dry etching or a wet etching operation. In some embodiments, the thinning operation may include a chemical mechanical polishing (CMP) operation. In some embodiments, the thickness including the first doped semiconductor layer 106 , the MQW layer 110 and the second doped semiconductor layer 108 may be between about 0.3 μm and about 5 μm. In some other embodiments, the thickness including the first doped semiconductor layer 106 , the MQW layer 110 and the second doped semiconductor layer 108 may be between about 0.4 μm and about 4 μm. In some alternative embodiments, the thickness including the first doped semiconductor layer 106 , the MQW layer 110 and the second doped semiconductor layer 108 may be between about 0.5 μm and about 3 μm.

Referring to FIG. 6E and operation 704 of FIG. 7 , a first etching operation may be performed to remove a portion of the second doping type semiconductor layer 108 and expose a portion of the first doping type semiconductor layer 106 . A portion of the first doped semiconductor layer 106 is exposed until a predefined thickness of the first doped semiconductor layer 106 remains on the first substrate 102 . In some embodiments, the remaining first doped semiconductor layer 106 extends horizontally across a plurality of LED units 116 in the LED structure 100, such as the four LED units 116 shown in Figure 6E. In some embodiments, the predefined thickness of the first doped semiconductor layer 106 may be between about 0.05 μm and about 1 μm. In some embodiments, the predefined thickness of the first doped semiconductor layer 106 may be between about 0.05 μm and about 0.7 μm. In some alternative embodiments, the predefined thickness of the first doped semiconductor layer 106 may be between about 0.05 μm and about 0.5 μm. After operation 704, the second doping type semiconductor layer 108 and the MQW layer 110 of each LED unit 116 may be electrically separated, and adjacent LED units 116 (such as LED units 116-1, 116-2, 116-3, and 116-4) of the first doping type semiconductor layer 106 may be electrically connected.

In some embodiments, during operation 704 , a first etching operation may be performed to remove a portion of the second doped semiconductor layer 108 and expose a portion of the MQW layer 110 . A portion of the MQW layer 110 is exposed until a predetermined thickness of the first doped type semiconductor layer 106 and the MQW layer 110 remain on the first substrate 102 . In some embodiments, the remaining first doped semiconductor layer 106 and the MQW layer 110 extend horizontally across a plurality of LED units 116 in the LED structure 100 , such as the four LED units 116 shown in FIG. 6E . In some embodiments, the predefined thicknesses of the first doping type semiconductor layer 106 and the MQW layer 110 may be between about 0.05 μm and about 1 μm. In some embodiments, the predefined thicknesses of the first doping type semiconductor layer 106 and the MQW layer 110 may be between about 0.05 μm and about 0.7 μm. In some alternative embodiments, the predefined thicknesses of the first doping type semiconductor layer 106 and the MQW layer 110 may be between about 0.05 μm and about 0.5 μm. After operation 704, the second doped semiconductor layer 108 of each LED unit 116 can be electrically separated, and adjacent LED units 116 (such as LED units 116-1, 116-2, 116-3, and 116-4 ) of the first doped semiconductor layer 106 and the MQW layer 110 may be electrically connected.

Referring to FIG. 6F , a second etching operation may be performed to remove a portion of the first doped type semiconductor layer 106 and expose the contact 118 . The second etching operation may be a dry etching or a wet etching operation. In a dry etching operation or a wet etching operation, a hard mask (eg, photoresist) may be formed on a portion of the second doped type semiconductor layer 108 and the first doped type semiconductor layer 106 through a photolithography process. Then, the uncovered portion of the first doped semiconductor layer 106 is removed by dry etching plasma or wet etching solution to expose the contact 118 .

Referring to FIG. 6G and operation 706 of FIG. 7 , a passivation layer 112 is formed on the second doped semiconductor layer 108 , the exposed first doped semiconductor layer 106 and the exposed contacts 118 . In some embodiments, the passivation layer 112 may include SiO ₂ , Al ₂ O ₃ , SiN, or other suitable materials for isolation and protection. In some embodiments, passivation layer 112 may comprise polyimide, SU-8 photoresist, or other photo-patternable polymers. In operation 708 of FIG. 7 , opening 120 and opening 122 are formed, as shown in FIG. 6G . The opening 120 exposes a portion of the second doped semiconductor layer 108 , and the opening 122 exposes the contact 118 . In some implementations, operation 708 may be performed by a third etch operation to remove a portion of passivation layer 112 and form opening 120 and opening 122 . In some further embodiments, the provided passivation layer 112 is formed by a photosensitive material (eg, polyimide, SU-8 photoresist, or other photopatternable polymer), and operation 708 may be performed by photolithography Operations are performed to pattern passivation layer 112 and expose opening 120 and opening 122 .

Referring to FIG. 6H and operation 710 of FIG. 7 , an electrode layer 114 is formed on the passivation layer 112 covering the opening 120 and the opening 122 . Therefore, the electrode layer 114 electrically connects the second doped semiconductor layer 108 and the contact 118 , and forms an electrical path to connect the LED unit with the driving circuit in the substrate 102 . The driving circuit can control the voltage and current level of the second doped semiconductor layer 108 through the contact 118 and the electrode layer 114 . In some embodiments, the electrode layer 114 may include a conductive material, such as indium tin oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge, or Ni, among others.

The present application provides an LED structure and a method for manufacturing the LED structure, wherein the functional epitaxial layers such as the first doped type semiconductor layer 106 and the second doped type semiconductor layer 108 are partially patterned/etched , to allow a thin continuous functional layer (such as the first doped type semiconductor layer 106 ) to remain from potential peeling off. In addition, the present application provides another option to keep the MQW layer on the first doped semiconductor layer 106 . In addition, the manufacturing method introduced in this application can further reduce the physical damage of the sidewall of the functional pixel (such as the LED unit 116), reduce the damage of the quantum well structure as the LED light-emitting area, and improve the optical and electrical properties of the functional pixel. characteristic.

According to an aspect of the present application, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes a bonding layer formed on the substrate, a first doped semiconductor layer formed on the bonding layer, a second doped semiconductor layer formed on the first doped semiconductor layer, and a second doped semiconductor layer formed on the a passivation layer on a part of the second doping type semiconductor layer and the first doping type semiconductor layer; and an electrode layer formed on a part of the passivation layer and in contact with the second doping type semiconductor layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first doped semiconductor layer of the first LED unit extends horizontally to the first doped semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit can be independently Working LED unit.

In some embodiments, the second doped semiconductor layer of the first LED unit is electrically isolated from the second doped semiconductor layer of the second LED unit. In some embodiments, each LED unit further includes a multiple quantum well (MQW) layer formed between the first doped semiconductor layer and the second doped semiconductor layer.

In some embodiments, the first doped semiconductor layer is a p-type semiconductor layer and is a common anode of the first LED unit and the second LED unit. In some embodiments, the second doped semiconductor layer is an n-type semiconductor layer and is a cathode of the first LED unit and the second LED unit.

In some embodiments, the substrate includes driver circuitry to drive the plurality of LED units. In some embodiments, the electrode layer of each LED unit is connected to the driving circuit through the opening on the first doped semiconductor layer.

According to another aspect of the present application, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes a p-n diode layer formed on a substrate, a passivation layer formed on the p-n diode layer, and an electrode layer formed on the passivation layer and in contact with the p-n diode layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first LED unit and the second LED unit have a common anode, and the first LED unit and the second LED unit are individually operable LED units.

In some embodiments, the p-n diode layer includes a p-doped layer, an n-doped layer, and a multiple quantum well (MQW) layer formed between the p-doped layer and the n-doped layer. In some embodiments, the p-doped layer is a common anode of the first LED unit and the second LED unit. In some embodiments, the n-doped layers of the first LED unit and the second LED unit are electrically isolated.

In some embodiments, each LED unit further includes a bonding layer formed between the substrate and the p-n diode layer. In some embodiments, the substrate includes driver circuitry to drive the plurality of LED units. In some embodiments, the electrode layer of each LED unit is connected to the driver circuit through an opening in the p-n diode layer.

According to a further aspect of the present application, a method for fabricating an LED structure is disclosed. A semiconductor layer is formed on the first substrate. The semiconductor layer includes a first doped type semiconductor layer and a second doped type semiconductor layer. A first etching operation is performed to remove a portion of the second doped type semiconductor layer and expose a portion of the first doped type semiconductor layer. A passivation layer is formed on the second doped semiconductor layer and the exposed first doped semiconductor layer. A first opening is formed on the passivation layer. An electrode layer is formed on the passivation layer covering the first opening and contacting the second doped semiconductor layer.

In some embodiments, performing the first etching operation further includes removing a portion of the second doped type semiconductor layer, and exposing a portion of the first doped type semiconductor layer, until a predefined thickness of the first doped type semiconductor layer remains on the on the first substrate. The remaining first doped semiconductor layer extends horizontally across the plurality of LED cells of the LED structure.

In some embodiments, forming the semiconductor layer on the first substrate further includes bonding the semiconductor layer to the first substrate through a bonding layer. In some embodiments, forming the semiconductor layer on the first substrate further includes: forming a driving circuit in the first substrate; forming a semiconductor layer on the second substrate; bonding the semiconductor layer to the first substrate through a bonding layer; and Remove the second substrate.

In some embodiments, forming the first opening on the passivation layer further includes forming a second opening on the passivation layer to expose contacts of the driving circuit. In some embodiments, forming an electrode layer on the passivation layer covering the first opening and contacting the second doped semiconductor layer further includes forming an electrode layer on the passivation layer covering the first opening and the second opening to electrically Connecting the second doped semiconductor layer with the contact of the driving circuit.

The above description of specific embodiments can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

The breadth and scope of the present application should not be limited by any of the above-described illustrative embodiments, but should be defined only in accordance with the appended claims and their equivalents.

Claims (7)

1. A micro-LED display, characterized in that, comprising: a substrate comprising a drive circuit and contacts of the drive circuit; A plurality of LED units, the plurality of LED units are formed on the substrate, each LED unit is a functional micro-LED pixel, and includes: a bonding layer formed on the substrate; a first doped semiconductor layer, the first doped semiconductor layer is formed on the bonding layer; a second doped semiconductor layer, the second doped semiconductor layer is formed on the first doped semiconductor layer; a multiple quantum well layer formed between the first doped semiconductor layer and the second doped semiconductor layer; a passivation layer formed on the second doping type semiconductor layer and on a part of the first doping type semiconductor layer; and an electrode layer formed on a portion of the passivation layer and in contact with the second doped semiconductor layer, Wherein, the plurality of LED units include a first LED unit and a second LED unit adjacent to the first LED unit, wherein the first doped semiconductor layer of the first LED unit extends horizontally to the first doped semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are independently operable LED units; The drive circuit is used to drive the LED unit, the contacts of the drive circuit are electrically connected to the second doped semiconductor layer of the corresponding LED unit through the electrode layer, and each of the contacts is exposed to two adjacent between LED units; Moreover, the electrode layer of each LED unit is connected to the driving circuit through the opening on the first doped semiconductor layer. 2. The micro-LED display according to claim 1, wherein the second doped semiconductor layer of the first LED unit and the second doped semiconductor layer of the second LED unit Galvanic isolation. 3. The micro-LED display according to claim 1, wherein the first doped semiconductor layer is a p-type semiconductor layer, and is a common anode of the first LED unit and the second LED unit . 4. The micro-LED display according to claim 1, wherein the second doped semiconductor layer is an n-type semiconductor layer, and is a cathode of the first LED unit and the second LED unit. 5. A micro-LED display, characterized in that it comprises: a substrate comprising a drive circuit and contacts of the drive circuit; A plurality of LED units, the plurality of LED units are formed on the substrate, each LED unit is a functional micro-LED pixel, and includes: A p-n diode layer, the p-n diode layer is formed on the substrate, the p-n diode layer includes a p-doped layer, an n-doped layer, and a layer formed between the p-doped layer and the n-doped layer Multiple quantum well layers; a passivation layer formed on the p-n diode layer; and an electrode layer formed on the passivation layer and in contact with the p-n diode layer, a bonding layer formed between the substrate and the p-doped layer; Wherein, the plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit, wherein the p-doped layer extends horizontally across the plurality of LED units and serves as the The common anode of the first LED unit and the second LED unit, and the first LED unit and the second LED unit are LED units that can work independently, and the driving circuit is used to drive the LED unit, The contacts of the drive circuit are electrically connected to the n-doped layer of the corresponding LED unit through the electrode layer; The electrode layer of each LED unit is connected to the driving circuit through an opening in the p-n diode layer. 6. The micro-LED display according to claim 5, wherein the n-doped layer of the first LED unit and the second LED unit are electrically isolated. 7. A method for manufacturing a micro-LED display, comprising: forming a driving circuit and contacts of the driving circuit on the first substrate; A semiconductor layer is formed on the second substrate, and the semiconductor layer includes a first doped semiconductor layer, a second doped semiconductor layer, and Multiple quantum well layers between; bonding the semiconductor layer to the first substrate via a bonding layer; removing the second substrate; performing a first etching operation, comprising: removing a portion of the second doped type semiconductor layer, and exposing a portion of the first doped type semiconductor layer until a predetermined thickness of the first doped type semiconductor layer remains A plurality of LED units are formed on the first substrate, wherein each LED unit is a functional micro-LED pixel, and the remaining first doped semiconductor layer spans horizontally across multiple micro-LED displays. LED unit extension; forming a passivation layer on the second doped semiconductor layer and on the exposed first doped semiconductor layer; forming a first opening exposing the second doped type semiconductor layer and a second opening exposing a contact of the driving circuit on the passivation layer; and An electrode layer is formed on the passivation layer covering the first opening and contacting the second doped semiconductor layer, so as to connect the contact of the driving circuit with the second doped semiconductor layer of the corresponding LED unit. Electrically connected so that multiple LED units can work independently.

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